Design of Fast and Robust State Elements

Transcription

1 Design of Fast and Robust State Elements Yuen Hui Chee and Cheongyuen Tsang Abstract With drastic device scaling and power reduction, latches and flip-flops now face increasing soft error rates (SER). To reduce SER, SER hardening techniques are employed at the expense of speed and circuit complexity. In this paper, we proposed a simple design methodology using logical effort analysis to size state elements for optimal speed with SER reliability constraint. We applied this methodology to the design of a transmission gate latch and dynamic latch using TSMC 0.8um process at VDD=.V. Optimized values obtained from SPICE simulations for various input capacitances and fan-outs are within 0% of the calculated values, thus verifying the validity of this design methodology.. Introduction Technology scaling is the key factor in performance improvement of CMOS technologies. Unfortunately, scaling results in reduced node capacitance and supply voltage and these lead to increased susceptibility to soft error rates (SER) [- ]. Soft error rates are mainly due to alpha particles emitted by decaying radioactive impurities in packaging and interconnect materials and neutrons from cosmic rays []. These energetic particles traversed through the silicon bulk and create minority carriers, which are collected at the source/drain junctions. If the collected charges exceed the critical switching charge Q crit, the logic state of the node will be flipped. As technology node approaches 0.µm, soft error rates induced by these cosmic neutrons and alpha particles are becoming more significant in integrated circuits. It is predicted that the energy and flow of these energetic particles are sufficient for creating unacceptable soft error rates in future IC generations, even at ground level. The situation is worsening at flight altitudes (<60kft) [4]. Traditionally, SER main ly affect memories because memories use small size transistor to increase their memory density. This results in smaller node capacitance and increases their SER susceptibility. Thus, memories are protected efficiently with error detecting and correction (EDC) codes. However, for distributed memory elements (e.g. latches), EDC codes result in high hardware overhead. These unprotected state elements are traditionally large in size and SEUs are not significantly. Unfortunately, as device shrinks in deep sub-micron technology, SEUs are no longer trivial in these unprotected state elements, especially in dynamic nodes [2]. To overcome SER reliability issues, several soft error hardening circuit techniques have been proposed in recent literatures [2,5-7]. Zhang et al [5] proposed to increase the storage node capacitance by adding gate or interconnect capacitance to reduce SER. Rockett [6] added a keeper or state redundant device to compensate for the charge loss due to particle strike. The hardened data latch can sustains a pc hit without logic upset with 40% area penalty. Karnik et al [2] employed stack tapering and added an explicit capacitance at the storage node. The hardened latch provides a 2 times soft error rate tolerance at the expense of 0% setup time and 4% power penalty. Weaver et al [7] observed that the probability of correlated strikes is very small and propose soft error protection using asymmetric response latches with redundancy circuits. These perturbation tolerant latches/flip flops typically trade SER reliability with speed and circuit complexity. Another approach to reduce SER is simply upsize the state elements till they are SER tolerant. However, this frequently does not yield the optimal speed. This paper aims to provide a design methodology to design state elements for the optimal speed with SER considerations. We first provide an empirical model for the SER and extract the model parameters from existing experimental data. Logical effort analysis is then used to size the flip flop/latches for the optimal speed under SER reliability considerations. To illustrate this design methodology, we apply it to the design of a static transmission gate latch (TGL) and a dynamic latch (DL) and verify this methodology with SPICE simulations.

2 2. Burst Generation Model Several theoretical models have been proposed to model SER [8-0]. However, these models are complex and are not commercially available. A simpler and yet accurate model is the modified burst generation model (BGR) []. In the modified BGR model, the soft error rates in FIT/bit can be expressed in terms as follows:? Q? = crit SER ( FIT / bit) CS x F x K x exp, ()? Q s? where CS is the charge collection cross sectional area, F is the incident neutron flux given as neutrons/cm 2 /s [] at ground level, K is a technology independent constant given as 2.2x0-5 [], Q crit is the critical charge required to flip the state of the node and Q s is the collection slope. As this model is empirical, we use the experimental data from [2] to calibrate the model. In [2], 4 million latches fabricated in 0.8µm CMOS technology are used to characterize the soft errors in 7 designs ( different areas of p-diffusion and n- diffusion each and fault tolerant design). The latches are tested using accelerated neutron beams experiments in Los Alamos National Lab with energy spectrum of the beam similar to that of terrestrial cosmic rays. For the minimum size transistors with source/drain diffusion areas of 0.2µm 2, the number of 0-> and ->0 soft errors at VDD=.V are 50 and 800 respectively. Q crit can be determined from SPICE simulations using current pulses to model the injected charge at the critical node. The duration of the current pulse used is 50ps, which corresponds to typical cosmic pulse lifetime of around 25ps to 75ps []. Simulation was done using TSMC 0.8um transistor models at VDD=.V, assuming that the transistor characteristics are similar to that used in [2]. With values of Q crit from SPICE simulations, Qs are determined from equation () and their values are summarized in Table. These values are in agreement with values predicted in [-4]. Error Type Q s Q crit 0-> error 24. fc 29.6 fc ->0 error 4.9 fc 5.6 fc Table : BGR model parameters for TSMC 0.8µm process. SER Reliability of TGL and DL The SER reliability of a node depends on () the critical switching charge Q crit required to flip the state of the node and (2) the area of source/drain diffusion which determine the minority charge collection area. The critical switching charge Q crit depends on the node capacitance, which determines the initial charge stored at the node, and the restoring current as in the case of staticized storage nodes [2]. The schematic of the transmission gate latch (TGL) and dynamic latch (DL) is shown in Fig. in in BUFFIN INVIN TG TG int (a) (b) TG2 INVFW INVFB BUFFOUT Fig.: Circuit diagram of (a) transmission gate latch and (b) dynamic latch. In the TGL, both nodes int and fb are possible critical nodes. Node int has more charge collection diffusion area than node fb as it is connected to two transmission gates. Typically, BUFFOUT is bigger than INVFB as it needs to drive a large load and hhence node int has a larger node capacitance. As SER is linearly dependent on charge collection area but exponentially dependent on Q crit, node fb will be the critical node if the restoring current of both nodes are the same. Q crit can be determined using SPICE simulations as described in the previous sn INVOUT out out CL fb CL 2

3 section and the SER reliability can be determined from equation (). Fig 2 shows the SER reliability and Q crit for various sizes of INVFW. The size of INVFW is given as a multiple z of a minimum size 2 to PMOS/NMOS inverter. FIT/bit.E-0.E-05.E-07.E-09.E-.E-.E-5 Fig 2: SER Reliability for various sizes of INVFW for TGL In the case of DL, the critical node is sn. As there is no restoring current, the critical charge is solely determined by the node capacitance (i.e. Q crit? C node *VDD/2). The Q crit for various sizes of INVOUT is given in Fig. The size of INVOUT is given as a multiple z of a minimum size 2 to PMOS/NMOS inverter. As shown in Fig., the Q crit for DL is lower than that of the staticized case (i.e. TGL) for comparable node capacitance due to the lack of restoring current. Qcrit (fc) to 0 Error 0 to Error Total Inverter Size Ratio z 0 to Error (TGL) to 0 Error (TGL) 0 to Error (DL) to 0 Error (DL) Inverter Size Ratio, z Fig : Q crit for various sizes of BUFFOUT for DL and TGL 4. Logical Effort Analysis Transmission Gate Latch (TGL) Logical effort analysis [] is used to size the transistors for speed. The reference inverter is defined as a minimum sized CMOS inverter with 2 to PMOS/NMOS size ratio. By definition, the logical effort of this inverter equals to one, and has pull-up and pull-down resistances of R. It has unit driving strength, three unit input capacitance (C) and unit parasitic delay. For the TGL, we designed such that the Q crit of node int is slightly higher than node fb. This is ensure that node fb is the critical node but with minimum penalty on the delay. This is achieved by setting the driving strength of INVFB+TG2 to be slightly higher than INVFB. Clocks and _bar are used to ensure that TG2 is off when data is written to the latch and on during when data is stored. Fig 4. shows the detailed transistor level schematic of the TGL. in BUFFIN 2v in v TG 2w w INVFW int Fig 4: Schematic of Transmission Gate Latch The delay due to the transmission gate TG can be taken into account by considering BUFFIN and TG as a single stage. Although the NMOS and PMOS operate in parallel while driving the output, their equivalent resistance is not equal to R/2. This is because NMOS(PMOS) transistors are good at transmitting 0() but poor at transmitting ()0. If NOMS(PMOS) transistors transmit (0), we assume 4x 2x BUFFOUT TG2 2x x 2z z 4x 2x out CL fb INVFB

4 Stage g h b f=ghb p BUFFIN+ w z x + z ( w )(x w TG w v z BUFFOUT Note: C L g = stage logical effort, h=stage electrical effort, b=stage branching effort, f=stage effort, p=stage parasitic delay. Table 2: T DQ logical effort analysis for TGL Stage g h b f=ghb p BUFFIN+T w x x + z ( w )(x w G w v x INVFW 2 2 C L Table : T SU logical effort analysis for TGL that its resistance is approximately twice compare to the resistance when NOMS(PMOS) transistors transmit (0). Hence the equivalent resistance of a PMOS/NMOS = 2w/w transmission gate has equivalent resistance of 2/w [4]. With this assumption, the combined driving strength of BUFFIN and TG is equals to /(w+2v) of the reference inverter. For calculating data to output delay (T DQ ), we note that the signal path consists of BUFFIN, TG and BUFFOUT. The logical effort analysis is summarized in Table 2. The data to output delay T DQ is given as: (w )(x CL w T DQ = (2) For the TGL, the setup time T SU is the minimum time that is required to store the data in node fb before TG closes without invoking too much penalty in T DQ. To simplify the analysis, we approximate T SU as the delay from input to node fb. The signal path under consideration now consists of BUFFIN, TG and INVFW. The logical effort analysis is summarized in Table. The setup time is T SU is given as: (w )(x w T SU = () For the TGL, the clock to output delay (T CQ ) is the delay when TG opens to the time the data reaches the output. When TG opens, BUFFIN has to drive the node int and BUFFOUT, which in turns drive the load. For fast rising inputs and clocks, this situation is similar to that of the case of T DQ. Hence, we approximate T CQ to be equal to T DQ to simplify the analysis. Typically, latches are used in unbalanced pipeline designs with slack passing and time borrowing. The maximum combination logic that can be processed per pipeline stage, neglecting clock jitter and slew, is given as [5] T CL,max =.5T CY (T CQ +T DQ +T SU ) (4) Thus, to maximize T CL,max, timing overhead due to the latches T D =T CQ +T DQ +T SU should be minimized. From equations (2) and (),?(w )(x? 2C T D?? + L + 2?? w? + +?? (5) 4

5 Stage g h b f=ghb p INVIN+ w z z( w ) w TG w v INVOUT C L C L Table 4: Logical effort analysis for DL The size of BUFFIN and C L is determined by the driving capability of the previous stage and load respectively. The size of INVFB and INVFW is determined from Fig. 2 by the required SER reliability. Hence, by differentiating equation (5) with respect to w and z and solving for w and z numerically, we obtain the values of w and z result in the minimum delay for a given input capacitance, load and SER reliability. Dynamic Latch The schematic of a dynamic latch (DL) is shown in Fig 5. in invin 2v v in Fig 5: Schematic of Dynamic Latch Logical effort analysis is used to optimize the timing overhead due to latches. Again, INVIN and TG are considered as a single stage. The logical effort analysis for data to output delay, T DQ is summarized in Table 4. The T DQ is given as: z(w ) CL w T DQ = (6) Similar to the case of TGL, the setup time T SU can be approximated as the delay from input to node sn to simplify the analysis. The setup time is given as: z( w ) w T SU = + TG 2w w sn invout 2z z out CL (7) As in the case of the TGL, we approximate T CQ to be equal to T DQ to simplify the analysis. Hence the timing overhead due to the latches T D is given as:? z(w )? 2? + 2? T D? CL w v? vw? z? v? (8) The size of INVIN and C L are determined by the driving capability of the previous stage and load respectively. Hence, differentiating equation (8) with respect to w and z and solving for w and z numerically, we obtained the values of w and z for the minimum T D without SER reliability considerations. To take SER reliability into consideratio n, we note that the critical node in the DL is node sn. As there is no restoring current, the SER reliability is determined solely by the node capacitance and the diffusion charge collection area at node sn. Thus the SER reliability will determined the minimum size of INVOUT (i.e. z min ). If the calculated value of z is more than z min, this value of z is used to size INVOUT. Otherwise, z min is used and equation (8) is minimized with respect to w to obtain the new value of w. The resulting w and z will lead to minimum T D for a given input capacitance, load and SER reliability. Assumptions In the proposed design methodology, several assumptions are made:. The required SER accuracy is sufficient given by the values predicted by the modified BGR model. 2. Accurate SER data are available for the CMOS process. In this paper, we assumed that the TSMC 0.8µm process are similar to that used in [2].. The clocks and input signals are sufficiently fast enough for logical effort analysis to be valid. 5

6 4. The approximation of T CQ?T DQ and T SU is approximately the delay from the input to the storage node holds sufficient well for TGL and DL. If this assumption is not valid, the logical effort equations for these delays have to be determined. 5. Sizing for speed Transmission Gate Latch To illustrate the proposed design methodology, we apply it to the design of a TGL to achieve optimal speed with reliability constraint. As an example, we require the TGL to have a SER reliability of.6x0 - FIT/bit with an input capacitance equivalent to three reference inverters and a fan-out of 4. If a reference inverter has an input capacitance of C, we have v= and C L =6C. From Fig. 2, having a SER reliability of.6x0 - requires INVFW to have the same size as a reference inverter. Hence, x is equal to. Using these values and minimizing equation (6) with respect to w and z, we obtain z opt =.7, w opt =.9. To verify the values calculated using logical effort analysis, SPICE simulations are carried out with VDD=.V, x= and v= for various values of integer values of w and z. T D was determined and the results are shown in Fig. 6. From Fig. 6, we obtained w opt =.4 and z opt =.5. These values are in good agreement with the calculated values using the proposed design methodology. The optimized values, w opt and z opt, are obtained without any constraint on the clock load. If the clock load is constrained such that w has to be less than w opt, then the global minimum T D will not be achieved. In this case, the values of w and z are chosen from Fig. 6 to achieve the local minimum T D for the maximum allowable w (w < w opt ). Fig. 7 shows the simulated T D for various sizes of BUFFOUT and INVFW (determine SER reliability) when TG is constrained to the minimum size to reduce the clock load. The input capacitance is times of the reference inverter and fan-out is 4. Delay T D (ps) Size of INVFW, x 4 2 Fig 7: Simulated delay for various values of x and z for TGL with w= Size of BUFFOUT, z Size of BUFFOUT (z) Size of TG (w) Fig 6: Simulated delay for various values of w and z for TGL Delay,T D (ps) Dynamic Latch As another example, we apply the design methodology to size the dynamic latch for optimal speed with reliability constraint. Suppose the required Q crit is 20fC, input capacitance is three reference inverters and fan-out is 6. Hence v= and C L =44C. Minimizing equation (8) with these values yield w opt =4, z opt =8. Again, SPICE simulations are carried out with VDD=.V, v=, C L =44C for various values of integer values of w and z. T D was determined and the results are shown in Fig. 7. From Fig 7, we obtained w opt =.5, z opt =7.5. These values are in good agreement with the calculated values using the proposed design methodology. 6

7 Size TG (w) Delay, T D (ps) Size of INVOUT (z) [2] T. Karnik, B. Bloechel, K. Sourmyanth., V. De and Shekhar Borkar, Scaling Trends of Cosmic Rays induced Soft Errors in static latches beyond 0.8u, 200 Symposium on VLSI Circuits Digest of Technical Papers, pp [] P. Hazucha and C. Svensson, Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate, IEEE Trans. Nuclear Science, vol. 47, no. 6, Dec. 2000, pp [4] P. Hazucha and C. Svensson, Cosmic -Ray Soft Error Rate Characterization of a 0.6um CMOS process, IEEE Journal of Solid State Circuits, vol 5, no 0, Oct. 2000, pp Fig 7: Simulated delay for various values of w and z for DL To take into account the SER reliability considerations, we note from Fig. that Q crit =20fC requires INVOUT to be at least have 6 times the size of the reference inverter. Hence, z min =6. Since z opt > z min, we satisfy the reliability constraint and z opt can be used to size INVOUT. Conclusion We proposed a design methodology based on logical effort to design state elements for optimal speed with reliability constraints. This methodology is simple to use and converges to the optimal design quickly. It is sufficiently accurate for first order analysis. We applied this design methodology to size a transmission gate latch and a dynamic latch for some required reliability, input capacitance and fan-out. The optimal transistor s sizes obtain from simulated results are within 0% of the calculated values, hence verifying the validity of this design method. References [] S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta and C. Dai, Impact of CMOS process scaling and SOI on soft error rates of logical processes, 200 Symposium on VLSI Circuits Digest of Technical Papers, pp [5] K. Zhang, S. Hareland, B. Senyk and J. Maiz, Methods for Reducing Soft Errors in Deep Submicron Integrated Circuits, Proc. International Conf. on Solid State and Integrated Circuit Technology 998, pp [6] L. R. Rockett, An SEU Hardened CMOS Data Latch Design, IEEE Trans. on Nuclear Science, vol. 5. no. 6. Dec. 998, pp [7] H. T. Weaver, W. T. Corbett and J. M. Pimbley, Soft Error Protection using Asymmetric Response Latches, IEEE Trans. on Electron Devices, vol. 8. no. 6. Jun. 99, pp [8] G. R. Srinivasan, H. K. Tang and P. C. Murley, Parameter free, predictive modeling of single event upsets due to protons, neutrons, and pions in terrestrial cosmic rays, IEEE Trans. Nuclear Science, vol 4, pp , Dec 994. [9] Y. Tosaka, S. Satoh and T. Itakura, Neutroninduced soft error simulator and its accurate predictions, 997 Conf. Simulation of Semiconductor Processes and Devices, 997, pp

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