ALU A functional unit
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1 ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1 B n-2... B 1 B 0 C 0 ALU F n-1 F n-2... F 1 F 0 F n M Mode Select Copyright 2003 A. Veidenbaum & A.Nicolau S 1 S 0 Operation Select 1
2 ALU Design A i Logic B i Mux F i Arithmetic C i C i+1 Copyright 2003 A. Veidenbaum & A.Nicolau S 1 S 0 M 2
3 Simple ALU Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 3
4 Arithmetic Logic Units (2) Figure Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity. 4
5 Logic Unit Ai NOT(Ai) Ai XOR Bi Ai XNOR Bi Fi S 1 S 0 Copyright 2003 A. Veidenbaum & A.Nicolau 5
6 Arithmetic Unit C i C i+1 Ai Bi X s1 s0 X Y 0 0 A A A B Y 1 1 A B s1.b s0 XOR A Full Adder Fi S 1 S 0 Copyright 2003 A. Veidenbaum & A.Nicolau 6
7 Where are we headed? Overall Goal: understand how a computer works simple one, not Pentium4 To do this need to know how to design basic building block» ALU, boolean functions, MUX, Memory what a computer does to process instructions» Instruction Set Architecture (later) know how to design logic that controls execution» control unit design Copyright 2003 A. Veidenbaum and A. Nicolau 7
8 Where are we now? Learned how to design combinational logic circuits» implementing boolean functions from gates, no feedback» basic building blocks of the data path Still need to learn sequential circuits and memory design how to put it all together Copyright 2003 A. Veidenbaum and A. Nicolau 8
9 Storage Elements So far saw only memoryless digital functions (Combinational Logic) Need to store program data and intermediate values (Sequential Logic) Know from ISA that there are registers and memory where does data in ADD R4, R6 reside? What are these R4, R6 registers? how do they work? How are they constructed? will explain using gates» in a way similar to combinational logic Copyright 2003 A. Veidenbaum and A. Nicolau 9
10 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 10
11 Storage Elements (continued) Are made from sequential circuits But require feedback:» new state = F(current state, inputs) Require timing to be taken into account will assume non-zero gate delay will introduce the concept of clock New state: a boolean function which depends on inputs from T earlier state from T earlier A combinational circuit with latency T output changes T seconds after an input change but the change is continuous as long as inputs change Copyright 2003 A. Veidenbaum and A. Nicolau 11
12 SR Latch Circuit Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 12
13 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 13
14 S-R latch Truth Table Q t S t R t Q t+1 S R Q Q ? ? 14
15 SR Latch R Q Q S S=R=1 leads to an unstable state. The output Q may oscillate before settling down to 1 or 0. Copyright 2003 A. Veidenbaum and A. Nicolau 15
16 SR Latch - Cont d SR inputs and the resulting state SR = 10 Q=1, Q =0 ( 1 state)» when SR goes to 00 state remains the same: Q=1, Q =0 SR = 01 Q=0, Q =1 ( 0 state)» when SR goes to 00 state remains the same: Q=0, Q =1 SR = 00 then Q remains unchanged SR = 11 is not allowed» electronically unstable state... Can only be in a state such that Q = NOT Q output change requires S=1 or R=1 to be applied Once input is removed the latch remembers stays in the same state Copyright 2003 A. Veidenbaum and A. Nicolau 16
17 S-R latch Timing S Q R Q S R 2 t 0 1 Q t 0 1 Q t 2 t 0 17
18 Problem with SR latch If S,R change then Q will change with many levels of gates the change propagates for a while» may not settle in time How to make sure changes to registers occur when desired once per cycle Modify the latch incorporate a clock signal as one of the inputs Copyright 2003 A. Veidenbaum and A. Nicolau 18
19 Clock Will design a computer with many latches How to make sure things happen when required? Consider a basic arithmetic operation Take data from 2 registers Run through the ALU Store to another register Need to make sure these three steps occur at the right time Solution: generate and distribute a special signal called clock» keeps time acts as a conductor for an orchestra or a drummer in a band Copyright 2003 A. Veidenbaum and A. Nicolau 19
20 Clock Any state change in the system is referenced to clock The clock is also a basic time unit for executing instructions although an instruction may take several clocks to execute Will start assuming that gates take time to propagate typical gate delay today is less than 100ps (10^-10 second) Copyright 2003 A. Veidenbaum and A. Nicolau 20
21 Clocked SR Latch R C S reset set Q Q Clocked SR Latches: C determines when the state can be changed. Copyright 2003 A. Veidenbaum and A. Nicolau 21
22 How does it look? One Clock Cycle Clock S Q T1 T2 R S,R come from somewhere else in the system >> can only effect change after the clock ( T1) Q changes T2 later due to propagation delay through gates Copyright 2003 A. Veidenbaum and A. Nicolau 22
23 Avoiding S=R=1: The D Latch D Q Clock Q 23
24 D Latch D Clock Now have only one input: D. Q Q If D is a 1 when the clock becomes 1, the circuit will remember the value 1 (Q=1). If D is a 0 when the clock becomes 1, the circuit will remember the value 0 (Q=0). 24
25 D Flip-Flop Timing D C Q
26 8 Bit Memory We can use 8 D Latches to create an 8 bit memory. We have 8 inputs that we want to store, all are written at the same time. all 8 latches use the same clock. 26
27 D clock D Latch Q 8 Bit Memory/(Reg) D 0 D Latch Q 0 D 1 D Latch Q 1 D 2 D Latch Q 2 D 3 D Latch Q 3 D 4 D Latch Q 4 D 5 D Latch Q 5 D 6 D Latch Q 6 D 7 clock D Latch Q 7 27
28 Flip-Flops D-Latches still have a problem with input changes during time clock is 1 Another (better?) solution to SR latch problem of input change Edge-triggered flip-flops» change can occur only on clock edge or transition from 0 to 1 28
29 Edge-triggered D Flip-Flop D D Q C >C Q C D Q - D and Q change in response to the rising edge of the clock. - Change in D leads to the change in Q after the next rising edge of C 29
30 Master-Slave D FF 30
31 Master-Slave D FF Gated D latch is level sensitive For master latch When Clk = 1, Q m = D For slave latch When Clk = 1, Q s = Q m 31
32 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 32
33 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 33
34 Master-Slave D FF The blue dotted line indicates period when Q s = D When clk is high (period a) Q m changes to D When clock is low (period b) Q s changes to Q m As the value of the output changes at the clock edge that fall from 1 to 0, this D FF is negative edge triggered 34
35 Flip-Flops (3) Figure D latches and flip-flops. 35
36 N bits stored as a unit Registers load all N at once when enable is 1 Enable is on for 1 clock cycle Enable Data_in[7:0] A Data_out[7:0] Clock 36
37 Topics covered Circuit design (Truth table, logic/boolean functions), using gates to design the circuit Design of Building blocks such as Mux, decoder, encoder (truth table and logic function) Design of Adder/Subtractor, logic functions ALU design (n-bit from 1-bit ALU, 1-bit ALU design to run various functions) Sequential design/storage: S-R latch timing diagram (truth table), D-latch, D flipflop and n-bit register from n D flipflops. Assembly: Follow your TA guidance 37
38 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 38
39 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 39
40 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 40
41 Topics covered Lecture Notes, Book chapters, Homework problems and sample problems. Quiz 2 is scheduled on Thursday, May 10 in class for min. 41
42 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 42
43 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 43
44 Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 44
45 System and CPU Organization Control Unit ALU CPU I/O Devices Registers REGISTERS Memory Disk Printer BUS 45
46 Register File in CPU Registers are made from two D-flip flops. Copyright A. Veidenbaum & A. Nicolau Do not duplicate or distribute 46
47 Drawing conventions Thick lines are buses - multiple bits wide Dotted line is clock Dashed lines are control signals 47
48 Memory Chips Memory IC is typically organized as a cell matrix NxN At each position is a single cell To get wider output - replicate the matrix 128Mbx8b IC may have 8 blocks (individual NxN matrices) Memory is built out of multiple chips 256MB DIMM may have Mx8b Ics» Eight are read (written) at once delivering 64b of data 48
49 Memory Organization and Decoding Usually organized as an NxN matrix of cells good for layout A decoder circuit selects the appropriate word in the memory based on the address provided. First, a row is read out of cell, N bits at once Second, a bit is selected from a row and output output goes though a tri-state buffer» 3 states are: 0, 1, floating floating means electrically disconnected The larger the memory the longer it takes to read Control signals chip select CS» nothing happens inside a memory unless selected output enable OE R/W» allows direct connect of IC outputs 49
50 A register file Data_in D C Enable R0 Q decoder D C Enable R1 Q Mux Data_out Clock D C Enable R7 Q Address 3 50
51 Data_in Memory IC organization NxN, 1b wide - singe cell N Row Address ColumnAddress Output Enable (OE) N Data_out 51
52 Memory Organization (3) 52
53 Memory Organization (1) 53
54 Memory Organization (2a) 54
55 Memory Organization (2b) 55
56 Memory Chips (1) Two ways of organizing a 4-Mbit memory chip. 56
57 Memory Chips (2) Two ways of organizing a 512-Mbit memory chip. 57
58 RAM Control Multiple chips connected together to get a wider word get larger memory Need to be able to select a chip enable its output Control signals chip select CS» nothing happens inside a RAM unless selected output enable OE» allows direct connect of IC outputs R/W 58
59 A 4-chip memory system Data_Bus Din Addr R/W CS RAM0 Dout OE Din Addr R/W CS RAM1 Dout OE 2 Din Addr R/W CS RAM3 Dout OE Address Output_enable R/W 59
60 More Memory Types RAMs static dynamic synchronous ROMs PROM EPROM EEPROM Flash EPROM 60
61 Memory cell organization - Static Memory (SRAM) Data_in Clock Write D C En Q Data_out SRAM bit is a latch - Dynamic Memory (DRAM) Controls access to bit value Bit cell - stores charge Write: put charge in Read: let charge flow out DRAM bit is a special transistor 61
62 Random Acces Memory (RAM) Access time from address to data out Constant access time independent of address unlike tape or disk Semiconductor memory: RAM ROM Many bits on one IC Each bit is a latch Depending on type get Static (SRAM) Dynamic (DRAM) SRAM is faster than DRAM Speed, cost, size relationship: Speed Cost Capacity 62
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