Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

Transcription

1 Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1

2 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember things memory elements Today s topic how to make computers remember things Overview latches transparent latches flip-flops CS031 Lecture 6 2

3 The Big Picture CS031 Lecture 6 3

4 Abstraction Hierarchy Programming Language Assembly Language Machine Language Sequential Circuit Combinational Circuit Binary Value Voltage CS031 Lecture 6 4

5 Memory Elements How to remember things with gates and wires? Two stable states X = 1 and X = 0 X = 0 and X = 1 This circuit can store one-bit of information What do we need now? How to assign a state? How to change the state? CS031 Lecture 6 5

6 R-S Latch A word is Each bit is represented by a latch CS031 Lecture 6 6

7 R-S Latch Initial State: [ Q = 1 and Q = 0 ] What if Q Q S=0 & R=1 CS031 Lecture 6 7

8 R-S Latch Initial State: [ Q = 1 and Q = 0 ] What if Q Q S=0 & R=1 0 1 CS031 Lecture 6 8

9 R-S Latch Initial State: [ Q = 1 and Q = 0] What if Q Q S=1 & R=0 CS031 Lecture 6 9

10 R-S Latch Initial State: [ Q = 1 and Q = 0] What if Q Q S=1 & R=0 1 0 CS031 Lecture 6 10

11 R-S Latch Initial State: Q = 0 and Q = 1 What if Q Q S=1 & R=0 CS031 Lecture 6 11

12 R-S Latch Initial State: Q = 0 and Q = 1 What if Q Q S=1 & R=0 1 0 CS031 Lecture 6 12

13 R-S Latch Initial State: Q = 0 and Q = 1 What if Q Q S=1 & R=1 CS031 Lecture 6 13

14 R-S Latch Initial State: Q = 0 and Q = 1 What if Q Q S=1 & R=1 0 0 CS031 Lecture 6 14

15 R-S Latch Initial State: Q = 0 and Q = 0 What if Q Q S=0 & R=0 CS031 Lecture 6 15

16 R-S Latch 1 Initial State: Q = 0 and Q = 0 What if Q Q S=0 & R=0 (S 1 st ) 0 1 CS031 Lecture 6 16

17 R-S Latch 1 Initial State: Q = 0 and Q = 0 What if Q Q S=0 & R=0 (R 1 st ) CS031 Lecture 6 17

18 R-S Latch 1 Initial State: Q = 0 and Q = 0 What if Q Q S=0 & R=0 (R 1 st ) 1 0 CS031 Lecture 6 18

19 R-S Latch 1 1 Initial State: Q = 0 and Q = 0 What if Q Q S=0 & R=0 (same time)?? CS031 Lecture 6 19

20 Problems with Latches Race conditions unpredictability of results Possibilities Q =0 and Q=1 Q =1 and Q=0 Instability CS031 Lecture 6 20

21 Clocks Circuits with feedback loops are difficult to control Need to worry about timing Main abstraction in circuit design Ignoring propagation time Basic solution Using a clock What is a clock? It is a free running signal Clock CS031 Lecture 6 21

22 Transparent Latches How to avoid timing problems? state changes only occur when the clock is asserted transparent latch that enforces Q=Data CS031 Lecture 6 22

23 Transparent D-Latch 1 1 CS031 Lecture 6 23

24 Transparent JK-Latch 1 1 CS031 Lecture 6 24

25 Shifting Shift right What does shifting right do to a number? Divides the number by 2. CS031 Lecture 6 25

26 Look Ma, my latch is leaking The results are still unpredictable The value of the first latch can be assigned to the second, the third, or any of the connected latches depending on propagation times and the clock cycle. Annoying to build shifting registers How to remedy this problem? CS031 Lecture 6 26

27 Edge-Triggered Methodology State Changes only occur on a clock edge Flip-flops latches which are only updated on a clock edge bits in words are flip-flops Flip-Flops CS031 Lecture 6 27

28 Shift Register Again CS031 Lecture 6 28

29 R-S Latch A R-S Latch was easy to implement in hardware. What about a flip-flop? CS031 Lecture 6 29

30 Edge-Triggered Flip-Flop S can only change when C = 0 Q can only change when C = 1 Q changes on next rising clock edge after Data changes A flip-flop is made of two latches! CS031 Lecture 6 30

31 Edge-Triggered Flip-Flops Basic constraint (rising edge flip-flop) The input D must be stable for a short period of time before the clock edge The input D must be stable for a short period of time after the clock edge In practice Setup times are enforced by making sure that the clock cycle is long enough Hold times are generally 0 or very very small CS031 Lecture 6 31

32 (Clocked) Sequential Circuit CS031 Lecture 6 32

33 D (data) More Flip-Flops JK (refinement of RS) T (toggle) CS031 Lecture 6 33

34 Excitation Tables If we want a flip-flop to make a certain state transition, what signals should we apply? JK Characteristic Table JK Excitation Table CS031 Lecture 6 34

35 Dynamic Discipline A (clocked) sequential circuit only clocked sequential devices and combinational devices no combinational cycles: every cycle contains a memory element the input values of every memory element must be stable before the clock edge, i.e. the clock cycle must be long enough for the combinational part to propagate CS031 Lecture 6 35

36 (Clocked) Sequential Circuit CS031 Lecture 6 36