Lecture 10: Sequential Networks: Timing and Retiming

Transcription

1 Lecture 10: Sequential Networks: Timing and Retiming CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

2 So far. Combinational Logic-level analysis

3 This lecture Combinational Our seemingly logically correct design can go wrong How can we design a circuit that works under real constraints?

4 Timing Constraints of flip flops The input to a flip-flop should be stable for a period of time around the rising edge of the clock D Q Q 4

5 Input Constraints: Set up and hold time D Q Q D t setup t hold I. Setup time: t setup t a Time before the clock edge that data must be stable (i.e. not change) II. Hold time: t hold Time after the clock edge that data must be stable Aperture time: t a Time around clock edge that data must be stable (t a = t setup + t hold ) 5

6 PIQ: Which of the following signals can cause a setup-time violation for this flip flop? Q(t) D(t) Q D A. The input signal D(t) Q B. The output signal Q(t) C. Both A and B D. None of the above 6

7 Output characteristics of flip flops D Q Q I. Minimum delay of Q II. Time after the clock edge for which Q is sure to not change Maximum delay of Q Time after the clock edge following which Q is sure to have stabilized 7

8 Output characteristics of flip flops D Q Q Q t ccq t pcq I. Min delay of flip flop, also called Contamination delay or min to Q delay: t ccq Time after clock edge that Q might be unstable (i.e., start changing) II. Max delay of flip flop, also called Propagation delay or maximum to Q delay: t pcq Time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) 8

9 Fact 1: Once a flip flop has been built we are stuck with its timing characteristics: t setup, t hold, t ccq, t pcq D1 R1 Combinational R2 Now let s look at the timing characteristics of the combinational part 9

10 Combinational Logic Timing I. Min delay of a gate, also called Contamination delay: t cd Minimum time from when an input changes until the output starts to change II. Max delay of a gate, also called Propagation delay: t pd Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing) 10

11 Combinational Logic: Output timing constraints A B C D Y PI Q: Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A. Green path B. Red path C. Both D. Neither 11

12 Combinational Logic: Output timing constraints A B C D Y PI Q: Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A. Green path B. Red path C. Both D. Neither 12

13 Timing Issues If the input to a flip flop doesn t stabilize in time BEFORE the rising edge of the clock we have a setup time violation C L (a) R1 R2 T c (b) 13

14 Why would the input () not stabilize in time? changes because of Flip flop has maximum delay, stabilizes after this maximum delay from the clock edge The combinational circuit has a maximum delay, so even after has stabilized, takes a while to stabilize If doesn t stabilize on time we have a setup violation C L (a) R1 R2 T c (b) 14

15 Timing Issues If the input to a flip flop changes too quickly AFTER the rising edge of the clock we have a hold time violation C L (a) R1 R2 T c (b) 15

16 Why would the input () change too quickly? changes because of Flip flop has minimum delay, will start changing only after this minimum delay The combinational circuit has a minimum delay, after which the output of CL () will start reacting to a changing input. If starts changing too quickly we have a hold time violation C L R1 R2 (a) T c (b) 16

17 Why timing in Sequential Circuits can go wrong? Which of the following violations would occur if the min delay of R1 was 0 and the combinational circuit was just a wire? A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1 D. Setup violation for R1 E. None of the above (a) R1 C L T c R2 (b) 17

18 Meeting the hold time constraint Input to a flip-flop comes from the output of another flip flop, through a combinational circuit The flipflop and combinational circuit have a min and max delay C L (a) R1 R2 To meet the hold time constraint: T c t hold < min delay(flipflop) + min delay(combinational) (b) 18

19 Why timing in Sequential Circuits can go wrong? Input to a flip-flop comes from the output of another flip flop, through a combinational circuit The flipflop and combinational circuit have a min and max delay (a) R1 C L T c R2 Which of the following violations would occur if the max delay of R1 was 0 and the max delay of the combinational circuit was equal to the clock period (b) A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1 D. Setup violation for R1 E. None of the above 19

20 Meeting the setup time constraint Input to a flip-flop comes from the output of another flip flop, through a combinational circuit The flipflop and combinational circuit have a min and max delay C L (a) R1 R2 To meet the setup time constraint: T c T c max delay(flipflop) + max delay(combinational)+ t setup (b) 20

21 Formalizing the hold time constraint in Sequential Circuits C L To meet the hold time constraint: R1 R2 t hold < min delay(flipflop) + min delay(combinational) t hold < t ccq + t cd t ccq t cd t hold 21

22 Formalizing the setup time constraints in Sequential Circuits To meet the setup time constraint: R1 C L T c R2 T c max delay(flipflop) + max delay(combinational)+ t setup T c t pcq + t pd + t setup t pcq t pd t setup 22

23 Timing Analysis Timing Characteristics t ccq = 30 ps A B t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D t pd (CL)= t cd (CL)= Setup time constraint: T c f c = 1/T c = X' Y' X Y t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t cd (CL)> t hold? 23

24 Timing Analysis Timing Characteristics t ccq = 30 ps A B t pcq = 50 ps t setup = 60 ps t hold = 70 ps C X' X Y' D t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t cd > t hold? ( ) ps > 70 ps? No! 24

25 Fixing Hold Time Violation Add buffers to the short paths: A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D t pd = X' Y' X Y t pd = 35 ps t cd = 25 ps t cd = Setup time constraint: Hold time constraint: T c t ccq + t cd > t hold? f c = 25

26 Fixing Hold Time Violation Add buffers to the short paths: A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D X' X Y' Y t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t cd > t hold? ( ) ps > 70 ps? Yes! 26

27 Midterm review SR latch 27

28 SR latch timing diagrams 28

29 29 What do inputs A & B do?

30 FSM design example Design an overlapping finite string pattern recognizer output is 1 whenever the input sequences 101 and 011 are observed 30

31 Sequential circuit design Present Next state Output State W=0 W=1 Z

32 FSM Design Example Write the state table and implement the following state machine: 32