Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab
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1 CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Memory Elements and other Circuits ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview. Bi stable circuits Metastability 2. Latches Flip FlopsFlops 3. Pipelines 4. Mono stable circuits 5. Clock generators The PLL 6. Schmitt trigger circuits VLSI Systems and Computer Architecture Lab 7. Charge pumps
2 Sequential Logic outputs= f(inputs, state) Inputs Combinational Logic Circuit Outputs Inputs Registers Logic Registers Outputs Sate Clock Clock Finite State Machine FSM Pipeline Memory Elements 3 Bistable Circuits Operating Principle V o V V / 2 V i2 V V / 2 Vertical mirroring and 9 ο clockwise rotation V / 2 V i V V / 2 V o2 V V i V o V i2 V 2 V V i2 =V o V o2 i2 o V / 2 A C V o2 V i V / 2 B V i =V o2 V Memory Elements 4 2
3 Metastable & Stable Operating Points V in V out A loop gain < loop gain > 2 V V out V / 2 C Α and Β = stable operating points C = metastable operating point δ 2 δ V / 2 V in V B Memory Elements 5 Metastability Memory State t In case that signals and are making transitions almost concurrently with the clock signal, then the following scenario is possible: the clock signal enters the memory state while the voltage level of both internal nodes and is close to the transition threshold of the two inverters. As a result the latch will arrive to its final state after a quite long time interval, while the logic level of this state depends on random factors, like the noise! Memory Elements 6 3
4 Latches Memory Elements 7 Multiplexer Based Latch Negative Latch MUX MUX Positive Latch Latch: Level sensitive circuit Complementary (non overlapping) clock CMOS design Memory Elements 8 4
5 Latch Timing Negative Latch Positive Latch MUX MUX Latch memory state Latch transparent state Latch memory state stable follows Stable follows Memory Elements 9 Controllable Feedback Latch A latch is sensitive to the level of the clock signal. One level stands for the transparent mode of operation where the input data pass to the circuit output. The other level stands for the memory mode of operation where the lth latch output t holds the last value of the input bf before the transition of the clock from the transparency level to the memory level. The feedback inverter can be designed with the k p,n factor of the transistors to be small. In that case the following pass gate can be eliminated. Memory Elements 5
6 Latch Timing Characteristics PW m T t setup t hold t c q t d q Hold Time (t hold ) Setup Time (t setup ) = Memory Elements Feedback Latch Setup Time Hold Time V V V 2 Valid Input ata Not Valid Input ata 3 Not Valid Input ata t Memory Elements 2 6
7 Flip Flops Memory Elements 3 Master Slave Flip FlopFlop Latch A Flip Flop is an edge triggered memory element. It is sensitive to a clock edge and not to a clock level. Only at this specific edgetheinput data pass to the output. 2 cascaded Latches with complementary clocks Master Slave Flip Flop Master Latch Slave Latch Static Flip Flop Memory Elements 4 7
8 Master Slave Flip Flop Flop Operation = low = high Memory Elements 5 Multiplexer Based Flip FlopFlop Static Flip Flop Master Slave MUX MUX Memory Elements 6 8
9 Flip Flop Flop Timing Characteristics T t t setup t hold t c q Setup Time (t setup ) Hold Time (t hold ) Memory Elements 7 Flip Flop Flop Timing Combinational Logic T t hold t setup t setup Must stand that: and t pcq T t pcq + t plogic + t setup t hold t cdflip flop + t cdlogic t plogic t plogic = logic propagation delay (worst case) t cdflip flop /t cdlogic = minimum delay (contamination delay) flip flop/logic Memory Elements 8 9
10 Setup and Hold Times Setup Time Hold Time Valid Input ata 2 Not Valid Input ata 3 Not Valid Input ata t Memory Elements 9 Two Phase C 2 MOS Flip Flop Flop ynamic Flip Flop V V Φ Φ 2 Φ Φ 2 Φ Φ 2 t Memory Elements 2
11 Non Overlapping Phases Generation Φ Φ 2 Memory Elements 2 ouble Edge Triggered Flip FlopFlop = V Active High ynamic Latch V = V V V ouble Edge Triggered FF (ETFF) Active Low ynamic Latch Memory Elements 22
12 Pipelines Ι a REG Initial Circuit a REG Pipelined Circuit + log Out + REG R REG R REG log REG Out b REG b REG T min, org t c q t p_add tp_abs tp_log tsu T min, pipe then t c q T max in case that min,pipe T tp_add,tp_abs,tp_log tsu t p_ add min,org t 3 p_abs t p_log Memory Elements 23 Pipelines ΙΙ Logic Logic Logic Logic Stage Stage Stage Stage IF I EX MEM r Register Register r Register r 2 Register r 3 r Register Clock Cycles IF I EX MEM IF I EX MEM IF I EX MEM Instructions IF I EX IF I MEM EX Memory Elements 24 2
13 Other Circuits Memory Elements 25 Monostable Circuits In Out elay t d In Out t d t d Memory Elements 26 3
14 Non Stable Circuits f osc Ring Oscillator n (t t ) d n = # βαθμίδων d V V V V V P Voltage Controlled Oscillator... V N n... Memory Elements 27 Clock Generation Phase Locked Loops (PLLs) εξ Phase Frequency etector Up own Charge Pump A Filter V cntrl VCO Voltage Controlled Oscillator =n εξ / n ivider n High frequency clock generation from a low frequency reference clock εξ Memory Elements 28 4
15 Phase Frequency etector I V εξ Up εξ /n Reset Up /n Reset own own V εξ /n εξ εξ /n Up= own= Up= own= Up= own= Up /n own εξ /n Memory Elements 29 Charge Pump and Filter II V V cp Up own Charge Pump V cp R Filter V cntrl R 2 C V V /2 2π ΔΦ 2π (deg) V SS == V cp V 4π V cntrl Filter Transfer Function: V cntrl jωr2c V jω(r R )C 2 cp t Memory Elements 3 5
16 Voltage Controlled Oscillator (VCO VCO) III f Curve slope: K VCO f 2π V max max f V min min f max f center f min V V cntrl Current Starved VCO V min V /2 V max V V V V V Voltage Controlled Oscillator Bias... V cntrl... (f) Memory Elements 3 Frequency ivider IV / 6 (f / 6) (f) Binary Counter f T Memory Elements 32 6
17 Clock istribution Buffers Logic Block Logic Block 2 Logic Block 3 Logic Block 4 Logic Block 5 Logic Block 6 Logic Block 7 Logic Block 8 Logic Block 9 Clock Sub omain Memory Elements 33 Grid Clock istribution Memory Elements 34 7
18 Central Clock istribution n 2 ex n Memory Elements 35 Η Tree Clock istribution (Ι) Clock Sub omain Buffer Memory Elements 36 8
19 Η Tree Clock istribution (ΙΙ) Buffer ex PLL Memory Elements 37 The Schmitt Trigger Circuit V in V out V sph V in V out V spl t t V out V V V in V out V spl V sph V in Memory Elements 38 9
20 Voltage Generators V in V V i V i V i+ V N V N V out C out R L V N V out V i V i+ V R V in V V The Charge Pump Concept Memory Elements 39 MOS Positive Charge Pump V V out > V C out Ring Oscillator with Enable Enable Memory Elements 4 2
21 MOS Negative Charge Pump V out < C out V out < Charge Pump with MOS Capacitors C out Memory Elements 4 2
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