CHAPTER 9: SEQUENTIAL CIRCUITS

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1 CHAPTER 9: ASYNCHRONOUS SEUENTIAL CIRCUITS

2 Chapter Objectives 2 Sequential circuits that are not snchronized b a clock Asnchronous circuits Analsis of Asnchronous circuits Snthesis of Asnchronous circuits Hazards that cause incorrect behavior of a circuit

3 Asnchronous sequential circuits 3 Snchronous sequential circuits state variables : F/Fs controlled b a clock operate in pulse mode Asnchronous sequential circuits do not operate in pulse mode do not use F/Fs to represent state variables Changes in state are dependent on whether each of inputs to the circuit has the logic level 0 or at an given time To achieve reliable operation (focus on the simplest case) the inputs to the circuit must change one at a time there must be sufficient time between the changes in input signals to allow the circuit to reach a stable state A circuit that adheres to these constraints is said to operate in the fundamental mode

4 Asnchronous behavior 4 R S Y (a) Circuit with modeled gate dela two NOR gate dela Present Next state Y = ( + S) + R state SR = Y Y Y Y stable state (b) State-assigned table

5 FSM model for the SR latch 5 Present Next state Output state SR = A A A B A 0 B B A B A (a) State table Moore-tpe FSM SR A 0 B (b) State diagram

6 Snthesis of an asnchronous circuit 6 Present Nextstate Output state SR = A A A B A 0 B B A B A (a) State table Present Nextstate state SR = Y Y Y Y R S Y z = R ( S + ) = R ( S + ) = ( R + ( S + )) = ( R + ( S + )) = Y (b) State-assigned table

7 Meal representation of the SR latch 7 Present Next state Output, state SR = A A A B A B B A B A 00/0 0/0 /0 (a) State table SR/ 0/ there is little to be gained in tring to make output go to a little sooner 00/ A B 0/ = R ( S + 0 (b) State diagram Y = R ( S + ) = ( R + ( S + ) )) = ( R + ( S + )) =

8 Terminolog 8 Asnchronous circuits state table -> flow table state-assigned table -> transition table or excitation table We will use the term flow table and excitation table

9 9 Analsis of Asnchronous Circuits

10 Analsis of Asnchronous circuits 0 D C Y Present Next state state CD = Y Y Y Y Y = = = = (a) gated D latch = ( C D) (( C D) ) ( C D) + (( C D) ) CD + (( C + D ) ) ( ) CD + C + CD + C D redundant d term to solve a hazard CD 0x x0 (b) Excitation table Present Next state state CD = A A A A B 0 B B B A B (c) Flow table A 0 B 0 (d) State diagram 0x x

11 Analsis of the circuit in example 9.3 Y z w w 2 Y 2 2 Y + Y = 2 + w 2 ww 2 2 z = = w 2 + w 2 + w w 2

12 2 Excitation and flow tables for the circuit in example 9.3 Present Nextstate state w 2 w = Output 2 Y 2 Y Y 2 Y Y 2 Y Y 2 Y z (a) Excitation table Present Nextstate Output state w 2 w = z A A B C D 0 B D B D D 0 C A C C C D D C C C 0 (b) Flow table

13 Modified flow table for Example Present Next state Output state w 2 w = z A A B C 0 B D B D 0 C A C C C D D C C C 0

14 State table for Example w 2 w 0 A/0 B/ x x C/ x D/0 00 x

15 5 Flow table for a simple vending machine Present Nextstate Output state w 2 w = z A A B C 0 B D B 0 C A C C D D C C 0 w 2 dime w nickel

16 Steps in the Analsis Process 6 Each feedback path is cut A dela element is inserted at the point where the cut is made A cut can be made anwhere in a particular loop formed b feedback connection, as long as there is onl one cut per (state variable) loop Next-state and output expressions are derived from the circuit The excitation table is derived A flow table is obtained A corresponding state diagram is derived from the flow table if desired

17 7 Snthesis of Asnchronous Circuits

18 Snthesis of Asnchronous Circuits 8 the same basic steps used to snthesize the snchronous circuits Devise a state diagram for an FSM Derive the flow table and reduce the number of states t if possible Perform the state assignment and derive the excitation table Obtain the next-state and output expressions Construct a circuit that implements these expressions

19 Example: serial parit generator 9 Serial parit generator input w : pulses are applied to w output z z= if the number of previousl applied pulses is odd w z 0 0 A/0 B/ 0 0 D/0 C/ 0 (a) State diagram

20 Parit-generating asnchronous FSM 20 0 A/0 B/ 0 0 D/0 C/ 0 (a) State diagram Present Nextstate Output State w = 0 w = z A A B 0 B C B C C D D A D 0 (b) Flow table

21 State assignment 2 Present Next state state w = 0 w = Output 2 Y 2 Y z (a) Poor state assignment Present Next state state w = 0 w = Output 2 Y 2 Y z (b) Good state assignment State assignment (a) has a major flaw state D = : w=0 -> state A 2 = -> 2 =00 the values of the next-state variables determined b the networks of logic gates with varing delas suppose changes first 2 =0 -> state C(0) state C is stable when w=0 suppose 2 changes first 2 =0-> state B (0) tr to change to 2 =0 when w=0 if changes first, 2 =00 race condition occurs

22 Circuit that implements the FSM 22 Y Y 2 z = = w = w w w z w 2 D z w Snchronous solution Asnchronous solution

23 23 Circuit that implements a paritgenerating asnchronous FSM The asnchronous implementation is more complex than the snchronous one? It s anegative-edge-triggered edge triggered master/slave F/F With the complement of its output connected to its D input

24 Master-slave slave D F/F(example 9.2) Analze snchronous circuit it as if it were an asnchronous circuit. Actuall all circuits are asnchronous Y = CD + C + D in the previous example of gated D - Latch D Master D m Slave D s Y = CD + C + m m D m C Clk Clk Y = C + C + s m s m s Circuit for the master-slave D flip-flop.

25 Excitation table for example Present Next state state CD = Output m s Y m Y s (a) Excitation table

26 Flow tables for Example 9.2 Present Next state Output state CD = S S S S S3 0 S2 S S S 2 S4 S3 S4 S4 S S 3 0 S4 S 4 S 4 S2 S 4 (b) Flow table Present Next state Output state CD = S S S S S3 0 S2 S S 2 S4 S3 S4 S S 3 0 S4 S 4 S 4 S2 S 4 (c) Flow Table with unspecified entries

27 State diagram for the master-slave D Flip/Flop 0x x0 CD S 0 0 S3 0 0x 0x 0 S2 S4 0 0x x

28 28 Parit generating FSM and Master- slave D F/F Y Y 2 = z = = w w w w Y = CD + C + of D in the previous example gated D - Latch Y = CD + C + D Y m s = C m + C m s + m m s = w = m, 2 s = C, 2 = D, z = = m D w Master D Clk =z Slave D Clk 2

29 29 Hazard and Glitches

30 Hazards and glitches 30 In asnchronous circuits it undesirable glitches on signals should not occur hazards the glitches cause b the structure of a given circuit and propagation delas in the circuit two tpes of hazards static the signal undergoes a momentar change in its required value dnamic when a signal is supposed to change from to 0 or from 0 to a change involves a short oscillation before the signal settles into its new level

31 Definition of hazards 3 0 (a) Static hazard (b) Dnamic hazard

32 Hazards and glitches 32 Usual solutions wait until signals are stable b using a clock preferable easiest to design when there is a clock snchronous circuits design hazard-free circuits sometimes necessar asnchronous design

33 Static hazards 33 x 2 p x f f = x x2 + x x f = x + x2 + xx3 x2x3 3 x 3 q (a) Circuit it with a hazard x 2 x x x 2 x x 3 f 0 (b) Karnaugh map (c) Hazard-free circuit hazard-free if more than one bit hazard free if more than one bit of inputs change simultaneousl?

34 34 Two-level implementation of master-slave D flip-flop Present Next state state CD = Output m s Y m Y s (a) Excitation table CD m s CD m s Y = CD + C + m m Y = C + C + s m s D m m s 0 0 (b) Karnaugh maps for Y m and Y s in Figure 9.6a

35 35 Two-level implementation of master-slave D flip-flop (2) m D p D Y m C m q Y m Y s C s r Y s (a) Minimum-cost circuit s (c) Hazard-free circuit Y = CD + C + m m Y = C + C + s m s D m m s

36 36 Static hazard in a POS circuit (0- hazard) x x 2 p f x x 2 x 3 q (a) Circuit with a hazard x 3 f x x 2 x (c) Hazard-free circuit (b) Karnaugh map

37 dnamic hazards 37 there exist multiple l paths for a given signal change to propagate along x neither eas to detect nor eas to deal with using two-level l hazard-free circuits b x 2, x 3, x 4 a b One gate dela x x 2 x 3 a c d f c d x 4 f (a) Circuit it (b) Timing diagram

38 38 CLOCK SYNCHRONIZATION (CHAPTER 0.3)

39 Clock skew 39 the clock signal arrives at different times at different F/Fs with or without clock enable circuits wires whose lengths var appreciabl Data D Clock E Data D Clock

40 An H-tree clock distribution network 40 ff ff ff ff ff ff Clock ff ff ff ff ff ff ff ff ff ff

41 F/F timing parameters 4 setup time t su hold time t h register dela or propagation dela t rd output dela time t od required for the change in to propagate to an output pin on the chip t Data Chip ppackage pin Data Clock A B D Out t Clock t od A flip-flop in an integrated circuit

42 F/F timing parameters, cont d 42 t co dela : active clock edge -> outputchange at an output pin t Clock + t rd + t od Example t Clock =.5ns, t rd =ns, t od =2ns -> t co =4.5 ns F/F timing in a chip t Clock =.5 ns, t Data =4.5 ns, t su =3 ns Clock Data aa A B 3ns 4.5ns.5ns setup time violation

43 43 Metastabilit and Asnchronous Inputs Asnchronous Inputs Are Dangerous! Since the take effect immediatel, glitches can be disastrous Snchronous inputs are greatl preferred! But sometimes, asnchronous inputs cannot be avoided e.g., reset signal, memor wait signal

44 44 Metastabilit and Asnchronous Inputs Handling Asnchronous Inputs Asnc Input Clocked Snchronous Sstem D 0 Asnc Input D Snchronizer D 0 Clock Clock D D Clock Clock Never allow asnchronous inputs to be fanned out to more than one FF within the snchronous sstem

45 45 Metastabilit and Asnchronous Inputs What Can Go Wrong In 0 Clk Setup time violation! In is asnchronous Fans out to D0 and D One FF catches the signal, one does not impossible state might be reached! Single FF that receives the asnchronous signal is a snchronizer

46 46 Metastabilit and Asnchronous Inputs Snchronizer Failure When FF input changes close to clock edge, the FF ma In enter the metastable state: neither a logic 0 nor a logic D out It ma sta in this state an indefinite amount of time, although this is not likel in real circuits Logic Logic 0 Logic Logic 0 T ime Small, but non-zero probabilit that the FF output will get stuck in an in-between state Oscilloscope Traces Demonstrating Snchronizer Failure and Eventual Deca to Stead State

47 47 Metastabilit and Asnchronous Inputs Solutions to Snchronizer Failure the probabilit of failure can never be reduced to 0, but it can be reduced slow down the sstem clock this gives the snchronizer more time to deca into a stead state snchronizer failure becomes a big problem for ver high speed sstems use fastest possible logic in the snchronizer this makes for a ver sharp "peak" upon which to balance S or AS TTL D-FFs are recommended cascade two snchronizers Asnchronous Input D D Snchronized Input Clk Snchronous Sstem

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