EE371 - Advanced VLSI Circuit Design

Transcription

1 EE371 - Advanced VLSI Circuit Design Midterm Examination May 7, 2002 Name: No. Points Score TOTAL / 70 In recognition of and in the spirit of the Stanford University Honor Code, I certify that I will neither give nor receive unpermitted aid on this examination. Signature: Although your answers are important, your REASONS for giving those answers are even more important. Please, please, please, explain what you are doing and why. This will make it a whole lot easier for me to judge your mastery of the material. 1

2 1. Wires a) Assume that you are working in a 0.35µ process (λ = 0.2µ). You find the following entries in a cap table for this technology: W H T S Ctotal Cgnd Cadj in λ in λ cap values are ff/µ air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x m3 / m2 / m m3 / m2 / m m3 / m2 / m m3 / m2 / m m3 / m2 / m m3 / m2 / m The numbers in the table are good to about 10%. There is no need for high-precision answers, so if you can find the data you need, estimate it from the data you have. i) (4 pts) If a 4λ wire is in the middle of a bus that is on a 10λ, pitch, what is the minimum effective capacitance of the wire? Maximum? Assume that there are no wires above or below the M2 bus wires. ii) (4 pts) Now assume that there are wires both above and below the M2 wires, which don t transition when the bus wires transition. Please give the value of the min and max effective capacitance values. (Bonus: Explain from basic physics why the min and coupling caps changed in the direction they did) 2

3 b) Wire capacitance and resistance are functions of the wire geometry - width W, length L, spacing between wires S, wire thickness T, distance to wire layers above and below this wire, H. Once the technology is set, a designer can only change W, S, and L. Assume that Cap = ( *W/H *T/S)fF/µ R/sq = 0.03Ωµ/T i) (4 pts) What is the RC delay of a wire? (Give as a function of the parameters) ii) (2 pts) If we scale a circuit so it uses a smaller technology, we would like both the gate and wire delays to scale by the same factor. If this was the case, how should the wire delay per lambda (RC/λ 2 ) depend on the scaling factor α (where α is less than 1) iii) (4 pts) We have said that the thickness of wires has scaled more slowly than widths and spacing to try to decrease the wire RC problem. Assume that T and H are held constant at the same value, and that W and S are the same and equal to αt. Please determine the wire RC/λ 2 as a function of α. Then plot the result in the area given. The plot should give the total and also show the contribution of the different components. RC/λ 2 0 α 1.0 3

4 2. Transistors / Corners a) (4 pts) In a bus where you can have coupling effects, we say you should use the worst-case coupling situation to estimate the effective wire capacitance for the repeater optimization problem. Why is that the correct value to use? What result is being optimized? (e.g. is it the nominal delay, the minimum delay, the power, etc.) What is the right transistor corner to use for this calculation b) (2 pts) You plot Vth vs. L for various operating conditions and generate this plot. Would you have faith in your model? What is likely to have caused this type of behavior. c) (4 pts) Ace comes to you very confused. He was working on a static CMOS low power chip, (which runs at.9v), and found that the slowest operating corner was low voltage, cold, rather than low voltage hot. He thinks the models might be wrong, but they look fine. If the models are ok, what could be going on? 4

5 d) For the following situations please give the corner (or corners) you would use to test the circuits. Please give all the parameters that you think matter. If you don t think a certain parameter is important, please say that too. For each circuit, please explain what transistor/circuit issue you are testing and how the corner you pick stresses this issue. You need this for full credit i) (4 pts) You are using a pmos transistor as a resistor in a circuit, and you are worried about the linearity of the resistor. The gate voltage is set by a bias circuit to make the nominal resistance track an external resistor. ii) (4 pts) You have designed a CMOS circuit for a watch chip. Since it runs at 32KHz, performance is not much of an issue but power is a key concern. iii) (4 pts) You are interested in the sensitivity of your nmos current sources to substrate noise. To measure this, you place a square wave voltage source on the substrate (which is nominally at Gnd) and move it 100mV. Assume that the control voltage is heavily filtered to Gnd, and is generated from a bias generator so the current from each current source is to first order independent of processing and operating corner. 5

6 3. Adders and Clocking a) Show in the figure is the simple self-timing pipeline that was giving in the lecture notes. Assume that the function blocks are using dual-rail signals and that the function block is operating on 32bit data. C C C D D D D Function Function Function Reset Reset Reset i) (4 pts) Assuming you want to detect the state of the data by looking at all the input data lines. What is the logical function the D block must perform to determine when the input is valid? ii) (4 pts) Assuming the logical effort of the function in part i) plus the C element is 16 (this might not be the correct number), and that the clock load on for each bit is 2x the allowed load that the D unit can place on the inputs lines. Estimate the delay from the data settling and the firing of the function unit. b) (4 pts) For saturating arithmetic, you need to detect overflow and then set the output to the max positive or max negative value. For an 16 bit adder, please write the equation that gives two outputs +overflow and -overflow. Full credit will be given to answers need the fewest late arriving signals. 6

7 c) Some adders use P= A exor B, and others use A or B. i) (2 pts) If both will work, which function would you choose and why? ii) (2 pts) As an input to a dynamic gate to compute Group G iii) (2 pts) As the input to a manchester carry chain that generates C0-C3 for a group of 4 bits d) A flip-flop is built from two latches. Each latch has a setup time of 50ps, a hold time of 100ps, and a data-q/ Clk-Q delay of 150ps. The two latches are set up back to back to create a flop. i) (6 pts) If Clk and Clk_b are perfect (there is no skew between them), what is the setup, hold, and clk-q delay for the flop. For our simple model we will define the setup time to be the time where the Clk-Q delay is constant (so overhead is setup+clk-q). Please draw a diagram that shows the clock edge and the delays to explain your answer. ii) (6 pts) Assume we want to create a flop using these latches that has a soft timing edge, with a transparency window of 200ps. Assume that Clk has no skew, but you are allowed to move Clk_b. What is the timing of Clk_b, and what is the setup, hold, and clk-q for this flop 7