Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY

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1 1 McGill University Faculty of Engineering DIGITAL SYSTEM DESIGN ECSE-323 FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Signature: Associate Examiner: Prof. Miguel Marin Signature: Date: December 4, 2008 Time: 2:00 pm INSTRUCTIONS: SEE NEXT PAGE.

2 McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 Fall 2008 FINAL EXAM 2 Question Maximum Points Points Attained Please write down your name: Total 180 Please write your student ID:ANSWERKEY Instructions/Please read carefully! This is a closed book exam. No books or notes are allowed. You may use a faculty standard calculator. All work is to be done on the attached sheets and under no circumstances are booklets or loose sheets to be used. Write your name at the top of every sheet. Read the question carefully. If something appears ambiguous, write down your assumption. The points have been assigned according to the formula that 1 point = 1 exam minute, so please pace yourself accordingly.

3 3 Question 1 :Boolean Logic Theory (15 points) The following function, F(A,B,C,D), is given by its k-map representation. K-MAP OF FUNCTION F(A,B,C,D) AB CD There are two minimal sum-of-products forms of F. (5 points) a) Give the two minimal sum-of-products forms of F, showing the answer on the given k-maps. (5 points) b) Using the Quine-McCluskey method, determine the set of prime implicants of F. (5 points) c) Using the covering table method and the corresponding Petrick function, find the two minimal sum-of-products forms of F. ANSWER FIRST MINIMAL FORM OF F AB CD SECOND MINIMAL FORM OF F AB CD F min = A B C + A C D + B C D + A B C F min = A C D + A B D + A B D + B C D b) First and only reduction ID A B C D Prime implicant GROUP A B C D P1 (0,1) P2 (0,4) P3 (1,3) P4 (4,12) P5 (3,7) P6 (12,14) P7 (7,15) P8 (14,15)

4 4 The prime implicants of F are Prime implicants A B C D P A B C P A C D P A B D P B C D P A C D P A B D P B C D P A B C c) COVERING TABLE Minterms Prime implicant GROUP A B C D P1 (0,1) P2 (0,4) P3 (1,3) P4 (4,12) P5 (3,7) P6 (12,14) P7 (7,15) P8 (14,15) Petrick function : P = (P1 + P2) (P1 + P3) (P3 + P5) (P2 + P4)(P5 + P7) (P4 + P6) (P6 + P8)(P7 + P8) P = (P1 + P2P3)(P5 + P3P7)(P4 + P2P6)(P8 +P6P7) P = P1P5P4P8 + P2P3P6P7 The two minimal sum-of-products forms are F min = A B C + A C D + B C D + A B C

5 5 F min = A C D + A B D + A B D + B C D

6 6 Question 2 : CMOS Technology (10 points) Using only Transmission Gates (TG s) and one inverter draw the circuit of a 1-bit decoder. A 1-bit decoder is a logic circuit that has one input, I, and two outputs, A, B. Each output assumes the value 1 for each one of the binary values of the input. Thus, for each value of the input, there is only one output equal to 1, and the other output equals to 0. The truth table of the 1-bit decoder is shown below INPUT OUTPUTS I A B Marking scheme: 5 points for a correct solution. 5 extra points for a solution containing ANSWER For each value of I, either 0 or 1 should be passed onto the output variables A and B according to the truth table of the 1-bit decoder and in such a way that both outputs are always assigned. In other words, none of the ouputs should be left flowting. The resulting circuit is shown below

7 7 Question 3: VHDL (20 points) (10 points) a) Write the Architecture body (only) for a description of the following Boolean function: f = AB + CxorD + CD. Use only component statements and assume that all required components have already been defined (i.e. you only have to do the component instantiations). Continue Question 3b on the next page.

8 8 Question 3 : VHDL (20 points) (Continued) (10 points) b) Write a complete VHDL description of a 4-bit counter circuit that counts in increments of X-Y, where X and Y are two 4-bit inputs, and wraps around to zero when the count would otherwise be greater than X. No incrementing should be done if X < Y. For example, if X=7 and Y=5 the count sequence should be {0,2,4,6,0,2 }. The circuit should have an asynchronous RESET input as well as a synchronous COUNT_ENABLE input.

9 9 Question 4 : Combinational Circuit Synthesis (15 points) You are asked to design a combinational logic circuit to be used in determining compatibility of people s blood. For this purpose, peaple s blood has been classified into 4 different types: A, B, AB and O. The rules of blood compatibility between donors and receivers are the following: 1.- Type O can donate blood to any type but receive only O. 2.- Type AB can receive blood from any type but can donate only to AB. 3.- Type A can donate to A or AB and receive from A or O. 4.- Type B can donate to B or AB and receive from B or O The circuit should work thus. For a given pair of donor-receiver, their blood types are entered into the circuit. The output of the circuit, F, assumes the value 1 if the donor blood type is compatible with the receiver blood type. F assumes the value 0 otherwise. (5 points) a) Give the truth table of the circuit and the k-map of F (5 points) b) Draw the circuit, producing F, using fewest number of 4 x 1 Multiplexers (5 points) c) Draw the circuit, producing F, using fewest number of 3-LUT s Hint: Use a binary code, (x,y), to code the four combinations of donor blood type, and, similarly, use a binary code, (w, z), to code the four combinations of receiver blood type. Thus, F is a function of the 4-variables x,y,w,z. ANSWER CODE ASSIGNMENT Donor Receiver BLOOD TYPE X Y W Z O AB A B DONOR O AB B A X Y W Z O AB B A RECEIVER k-map of function F

10 10 Question 4 : Combinational Circuit Synthesis (15 points)(continued) b) c) F = x y + w z + x y z + y w z = f1 + f2, where f1 (x, y,z) = x y + x y z f2 (w,y,z ) = w z + y w z x y z f w y z f2 a f1 f2 F X X X X

11 11 Question 5 : Testing of Combinational Circuits (15 points) Given the following circuit A B!A C B C i j k F (5 points) a) Find a test vector that detects the fault k stuck-at-0. (5 points) b) Find a test vector that detects the fault k stuck-at-1. (5 points) c) Is the circuit fully testable for all the single stuck-at fault? If not, then explain why and modify the circuit to be completely testable without changing the function.. ANSWER a) b) A B C F F k/0 F F k/ A B C F F k/1 F F k/ No vector exists to test k s-at-0 Test vectors for k s-at-1 are {000,010,100,101} c) The circuit is not fully testable because k is not testable for s-at-0 fault. The term BC is redundant. One possibility of a modified fully testable circuit is F = B(A+C) + A B. Another one is F = A B + A C.

12 12 Question 6: Sequential circuits (15 points) Given a D-type flip-flop, convert it into a JK-type flip-flop. Proceed as follows (5 points) a) Draw the corresponding Mealy-type state transition diagrams for the D-type and JK-type flip-flops. (5 points) b) Derive the input D of the D-type flip-flop in terms of the inputs J and K. (5 points) c) Draw the circuit realization, using AND, OR NOT gates, of the JK-type flipflop using the given D-type flipflop. ANSWER a) b) 1/1 0/0 A 0/0 11/1 10/1 B 1/1 Q Q + J K D X X X X /0 01/0 A 01/0 11/0 B 10/1 00/1 c) JK Q D = Q J + K Q

13 13 Question 7: Register and Counter Design (15 points) Using the programmable counter shown in the figure below, produce the circuit of a multiplesequence counter that counts in different sequences depending on the values of the control signals x, y. The counter counts according to the following table: Control signals Counting Mode x y 0 0 Reset counter 0 1 Counter modulo Counter modulo Not used (8 points) a) Draw the complete circuit using 4 x 1 multiplexers and gates as needed (7 points) b) Is your counter self-starting? If not, add whatever is needed to make it self-starting. Explain your result. Hint: A modulo-n counter is a counter that follows N different states, and not necessarily following the ascendeing or descending order of the natural sequence. a) For the counter modulo-12 and modulo-10 we use the RCO signal to activate the LOAD reseting the counter to the corresponding initial state of its counting sequence, namely, 4 in the case of modulo-12 and 6 in the case of modulo-10 counter. b) The counter is self starting because what ever the initial state, when RCO is reached, the counter will follow the selected counting mode.

14 14 Question 8: Circuit Implementation Strategies/Logic arrays (15 points) Given the function F(A,B,C,D) = m(0,2,3,7,9,10,11,14), if Φ (A,D) = A D + A D, (5 points) a) Find F1 such that F (A,B,C,D) = F1[Φ (A,D),B,C] (5 points) b) Program the given PAL schematic to produce F. (5 points) c) Draw a gate logic circuit (using NAND, EXOR, NOT gates) that will produce the function F. a) AB CD F(A,B,C,D) = B C + A B D + A C D + A C D + A B D The Shannon expansion with respect to B, C produces the following expression F(A,B,C,D) = B C [ A D + A D] + B C[ 1 ] + B C[ 0 ] + B C[ A D + A D ] F(A,B,C,D) = B C [Φ (A,D)] + B C + B C [ Φ (A,D)] F(A,B,C,D) = C Φ + B Φ, where Φ (A,D) = A D + A D. Continue Question 8 on next page..

15 15 Question 8: Circuit Implementation Strategies/Logic arrays (Continued) b) A B C D X X X X X X X X F c)

16 16 Question 9: Finite State Machine Design (15 points) Design a Mealy-type finite state machine that has one input X and one output Z. The output Z = 1 if and only if 4 consecutive 1 s have been received at input X, and Z = 0 otherwise. (5 points) a) Give the state transition diagram of this machine using a minimum number of states.(four states are sufficient) (5 points) b) Give the state transition table of the FSM. (5 points) c) Give the minimal two-level NAND-NAND implementation of the FSM using D-type edge-trigger flip-flops. ANSWER a) b) Present state Next state Output Z y1 y2 X =0 X=1 X =0 X=1 S1 = S2 = S3 = S4 = Y1 Y2 c) DY1 = Y1 = y1 y2 X + y1 y2 X ; DY2 = Y2 = y2 X ; Z = X y1 y2 Continue Question 9 on next page.

17 17 Question 9: Finite State Machine Design (Continued) X D Q Y1 >!Q Z D Q >!Q Y2

18 18 Question 10 : Design of Sequential Systems(20 points) Design a datapath/controller system that computes the following continued fraction approximation of log(1+z): x log(1 + x) = x 1+ x x Let x be the input to the system, and let y be the output of the system (which should be equal to the approximation to log(1+x)). Let the presence of a new input value be signalled by the rising edge of an external input signal START. Set a signal called DONE to high when the computation is finished. Assume that only one datapath module of each type is available (e.g. one divider, one adder, etc). Provide an asynchronous reset. a) (8 points) Draw the datapath. b) (4 points) List all of the controller inputs and outputs. c) (8 points) Draw the state transition diagram for the controller (use a Moore machine approach). Continue Question 10 on next page.

19 19 Question 10 : Design of Sequential Systems (Continued)

20 20 Question 11: Optimization of Finite State Machines (15 points) Simplify the following state table Present Next state Outputs state X = 0 X = 1 Z1 Z (8 points) a) Give the result obtained at each step of the application of the partition method to the given state table. (7 points) b) Give the minimal state table. ANSWER a) Initial sate group: ( ) 1 st partition: different outputs : ( ) (5) 2 nd partition: (1) ( )(5) 3 rd partition: (1)( ) (5) (6) 4 th partition: (1) (2,4) (3,7) (5) (6) 5 th and final partition is equal to 4 th partition, therefore the result is (1) (2,4) (3,7) (5) (6). b) Replacing (1) for A, (2,4) for B, (3,7) for C, (5) for D, and (6) for E, we obtain the following minimal state table Present Next state Outputs state X = 0 X = 1 Z1 Z2 A D C 0 0 B C A 0 0 C B C 0 0 D E B 1 0 E D B 0 0

21 21 Question 12 : Testing of Sequential Circuits (10 points) (5 points) a) Explain why testing of sequential circuits is more difficult than test of combination circuits. (5 points) b) Draw the circuit diagram of a 4-bit MISR (multi-input LFSR for signature analysis).

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final