Final Exam: Graduate Course { VLSI Testing. 1. Please read all problems before starting your answers. Problems can be answered
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1 inal xam: Graduate ourse { VLSI Testing uburn Univ., L 7250, Spring 2004 May 10, 2004 Instructions (please read before you proceed): 1. Please read all problems before starting your answers. Problems can be answered in any order. 2. ttempt all six problems and attempt all parts within each problem. 3. nswers can be written on question sheets or separate sheets or a combination. ach sheet should have a page number and problem number. On the rst sheet write your name and the total number of sheets you are submitting. 4. efore handing in your answers, please check them thoroughly. If necessary, extra 10 minutes can be allowed for checking. Problem 1: ault Modeling (16 Points) or the circuit of igure 1, determine fault equivalences among the ve faults shown. J sa1 L G sa0 sa0 H sa1 K sa1 M igure 1: ircuit for fault modeling problem. Page1of6
2 Problem 2: Testability Measures (16 Points) or the circuit of igure 2 compute SOP combinational controllability and observability measures for all lines (8 points). I D J K G H igure 2: ircuit for testability measures problem. L (i) ssuming that the testability of a stuck-at fault can be represented as the sum of appropriate controllability and observability, nd the set of most dicult to test faults (4 points). (ii) Proving a fault to be redundant is a dicult task for an TPG program. This circuit has three redundant faults, I s-a-1, J s-a-1, and s-a-1. re all of these faults in your set of most dicult to test faults? If not, explain why not (4 points). Page2of6
3 Problem 3: Logic Simulation (17 Points) The following conversation is recorded at a meeting to discuss the verication problems of the circuit shown in igure 3: K igure 3: ircuit for Problem 3. Designer: Why does our logic simulator not initialize my circuit? D ngineer: That is due to a limitation of the three-state logic simulator. Designer: Irrespective of the initial state, the ip-op should initialize to 1 state when 1 is applied at the input and the circuit is clocked. I am not going to change the circuit. You better x your simulator. D Manager (not realizing what is being promised): My engineer will nd a solution before the end of the day. You are the D engineer who must take the challenge: (i) Devise a modication of the three-state logic simulator that will correctly initialize the circuit of igure 3 containing a single ip-op (9 points). (ii) How will you extend the new procedure for circuits with many ip-ops (4 points)? Discuss any limitations (4 points). Page3of6
4 Problem 4: Podem (17 points) Use the Podem algorithm to derive a test for the fault G stuck-at-0 in the Schneider's example circuit from Roth's 1967 paper, which is shown in igure 4 (8 points). G (2,3)9 J SOP Testability Measures (0, 1) O (2,3)10 K (2,3)10 sa0 (2,3)10 (5,9)0 L H (2,3)9 M igure 4: Schneider's circuits for Podem problem. Neatly write all steps, specifying objectives, operations (backtrace, forward implications, X-path check, etc.) Give the state of the implication stack at each step. (9 points). Page4of6
5 Problem 5: Delay Test (17 points) (i) Specify a single input change (SI) test for the critical path " a ; z (shown in bold lines) in the circuit of igure 5(i). Is this a robust test? (8 points) (ii) The circuit of igure 5(i) is redesigned in igure 5(ii) to reduce the delay. Will the SI test obtained above still test the longest delay path shown in bold lines? If not, what is the minimum modication required in the test? (9 points) a b c d e f g h i (i) Original circuit. z a b c d e f g h i z (ii) Redesigned circuit. igure 5: ircuits for delay test problem. Page5of6
6 Problem 6: DT (17 Points) The circuit in igure 6 is a sequence detector. sequence in the input bitstream at locks the output to 1. The output can be unlocked by applying R =1. K R igure 6: ircuit for DT Problem 6. or scan design, only one pin is available and the only circuit element that can be used is a two-to-one multiplexer. (i) Redesign the circuit using minimum extra hardware to conform to the scan design rule, \clock must not be gated by acombinational signal." Neatly sketch the redesigned circuit (8 points). (ii) Sketch aschematic of the full-scan circuit using minimum extra overhead. Show the complete wiring of the SNIN, SN OU T and test control (T) signals (9 points). Page6of6
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