A New Design Method for Unidirectional Circuits

Transcription

1 A New Design Method for Unidirectional Circuits Saposhnikov V. V., 1) Morosov A., 2) Saposhnikov Vl. V., 1) Gössel M 2) 1) University for Railway-Engineering, Moskovski prospekt 9, SU , Sankt-Petersburg, Russia 2) Fault Tolerant Computing Group at the University of Potsdam, Insitute of Informatics, PF , D15415, Potsdam, Germany Abstract In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area overhead is less than half of the area overhead of other known methods. All single stuck-at faults are detected by the method proposed. 1. Introduction The design of self-checking circuits [1], [2], [3] is becoming more and more important as the complexity of VLSI continues to increase. In addition to permanent faults, transient faults are becoming of greater concern. Self-checking circuits have the ability to detect both transient faults and permanent faults. The combination of methods for on-line error detection or concurrent checking and testing is of great interest now [4], [5], [6]. Self-checking circuits for arbitrary prediction functions [7] and [8] for parity prediction for mutually disjoint groups of outputs of combinational circuits [9], [10] are described in the literature. These methods, however, are generally not welladapted to the specific structure of the monitored circuit and the technical fault model. Some of the single stuck-at- 0/1 faults may be mapped to erroneous output code words which can not be detected as erroneous by the checker, and the circuits are not fault-secure [11]. A method for the design of self-checking circuits adapted to the fault model of single stuck-at faults is given in [12]. In that paper, independent outputs of the monitored combinational circuit are the groups of outputs for which the parity is computed, duplicated, inverted and compared with the corresponding parities of the outputs of the original circuit. The design of circuits with a given number of groups of independent outputs is considered in [13]. In [14], a generalization of [12], a structure dependent method for the design of self-checking circuits is described. Maximal groups of independent outputs and unidirectionally independent outputs are monitored by parity bits and Berger code bits. In [15] a synthesis method for inverter-free circuits is described. The resulting circuit has inverters only at its primary inputs. Since all stuck-at faults result in unidirectional errors, these circuits can be monitored by Bergercode bits. The automatic synthesis of such circuits is given in [13]. In [16] it is shown that all single stuck-at-0/1 faults can be detected as unidirectionally multibit errors of the outputs if special encodings are used. In this paper, we propose a simple method of redesigning an arbitrary given multi-level combinational circuit to achieve a self-checking fault secure circuit. Selected gates of the circuit given as a net list are duplicated. The interconnections of gates in the modified circuit are determined in a simple way by the inverters of the original circuit, and the outputs of the transformed circuit form only one group of unidirectionally independent outputs. Therefore, these outputs can be monitored by use of a Berger code, or by the least significant bits of a Berger code. 2. Basic Notions and Notations In this paper we consider a combinational circuit f c with n binary inputs,..., x m and m binary outputs y 1 = f 1 (,...,x n ),...,y m = f m (,...,x n ), where f 1,...,f m are n-ary Boolean functions. Let x = (,..., x n ) and y = (y 1,..., y m ). The circuit f c can also be considered as a connection of 1

2 N gates g 1,..., g N described by a net list. At the output of gate g j, j = 1,..., N, the Boolean function z j = G j (x) is implemented. The set of technical faults considered is denoted by φ = { φ 0, φ 1,..., φ κ }, where φ 0 denotes the absence of a fault. If a fault φ i φ is present, the output y i under input x is denoted by y i,j = f i (φ j, x). Thus, in the absence of a fault, we have the correct output y i,0 = f i ( φ 0, x) = f i (x). The notion of unidirectionally independent outputs as a generalization of independent outputs [12], [17] is given in the following definition. Definition 1 [14]. The outputs y i and y k are called unidirectionally independent with respect to the fault φ i φ if we have, for x X, either 1. f i (x) = f i (φ j, x) and f k (x) = f k (φ j, x) or 2. f i (x) = f i (φ j, x) and f k f k (φ j, x) or f i (x) f i (φ j, x) and f k (x) = f k ( φ j, x) or 3. f i (x) f i ( φ j, x) and f k (x) f k (φ j, x) and f i (x) = f k (x). Two outputs are unidirectionally independent if, in the presence of a fault, they are both correct, if only one of them is erroneous, or if they are both unidirectionally erroneous. In the last case, both outputs are changed from 0 to 1 or from 1 to 0. Independent outputs [12], [17], [18] are a special case of unidirectionally independent outputs. The outputs y i and y k are independent with respect to the fault φ j if only conditions 1 and 2 of Definition 1 are fulfilled. In this case, the outputs y i and y k are independent if they are either both correct or if only one of them is erroneous at a time. Definition 2 [14]. The outputs y i and y k are called unidirectionally independent with respect to a set φ of faults if they are unidirectionally independent with respect to every fault φ j φ. Definition 3 [14]. The outputs form a group of unidirectionally independent outputs if every pair of these outputs is unidirectionally independent. Definition 4. The outputs y i and y k are called unidirectionally independent with respect to a gate g j if they are unidirectionally independent with respect to all faults ϕ j, ϕ j φ, of that gate. If φ is the set of all single stuck-at-0/1 faults, then φ j is the set of all single stuck-at-0/1 faults of the input and output lines of g j. Proposition 1. The outputs y i and y k are unidirectionally independent with respect to the gate g j if and only if we have Proof. dy dy i k dz dz y y = 0 i k j j The inputs of f for which a change of the output z j of g j results in a change of the output y s, s = 1,...,k, is determined by dy s dy dy ( x) = 1 i k. Thus ( x) ( x) = 1 dz j dz dz j j determines the inputs for which a change of z j results in a simultaneous change of both the outputs y i and y k. Since y ( x) y ( x) = 1 i k which we have y i (x) = y k (x), and (1) determines the inputs of f c for dy dy i k ( x) ( x) y ( x) y ( x) = 1 determines dz dz i k j j the inputs for which a change of z j simultaneously changes the outputs y i (x) and y k (x) in different directions, we can conclude (1). Definition 5. A gate g j is called unidirectional if all pairs of outputs y i, y k, 1 i<k m are unidirectionally independent with respect to g j. If an unidirectional gate is erroneous, the following situations may occur: 1. Every output of the circuit f c is correct; 2. One of the outputs of f c is erroneous; 3. Some of the outputs of f c are unidirectionally erroneous. A simple structural definition of a unidirectional gate will be very useful. 2

3 Definition 6. A gate g j, j {1,...,N} is called structurally unidirectional if its output is only connected to one of the outputs of f c or, if its output is connected to several outputs of f c, every path from the output of g j to each of the outputs of f c contains either an even or an odd number of inverters. A gate that is structurally unidirectional according to Definition 6 is obviously unidirectional according to Definition 4 and 5. x 2 Fig. 1 As an example, we consider the circuit f 1 represented in Figure 1. f 1 consists of 5 elements g 1,...,g 5. The functions y 1,..., y 5 are implemented at the outputs of these elements. The elements g 2, g 3, g 4 and g 5 are structurally unidirectional. The element g 1 is connected to the outputs y 1 and y 2. The number of inverters on the path from g 1 to y 1 is zero (even) and the number of inverters on the path from g 1 to y 2 is one (odd). According to Definition 6, the element g 1 is not structurally unidirectional. Now we check whether condition (1) is satisfied. The outputs y 1 and y 2 are determined by, and we have and dy dy ,, dz 1 x x x 2 = = x x = dz 1 1 and finally g 1 g 2 z 1 z 2 g 1 is not unidirectional. g z 3 3 z g 5 5 y 1 g 4 z 4 y 2 y = x x x x x = x z x y = x x = z y y = x x x dy dy , and gate dz dz y y = x x If the output z 1 of g 1 is stuck-at-1 under input 000 the output y 1 changes from 0 to 1 and the output y 2 from 1 to 0. Of special interest is the case where all the elements of y 3 a circuit are unidirectional. Definition 7. A combinational circuit f c is called unidirectional if every gate of f c is unidirectional. A unidirectional circuit f u has the following attributes: If a single gate fault occurs in f u, one of the following situations occurs: 1. None of the outputs of f u is erroneous; 2. One of the outputs of f u is erroneous; or 3. Some of the outputs of f u are unidirectionally erroneous (all changing from 0 to 1 or from 1 to 0). If a circuit f is unidirectional, 100 % of its (non-redundant) single gate faults, such as single stuck-at-0/1 faults, can be detected by the circuitry shown in Figure 2. The circuitry of Figure 2 consists of the functional circuit f c, a check bit generator C and a self-checking Berger-code checker SCC. X f c C c 1... c q Fig. 2 SCC V 1 V 2... In addition to the functional outputs y 1,..., y m of f c, the check bits c 1,..., c q are generated by the check bit generator C such that y 1,..., y m, c 1,..., c q are elements of a Berger code or a modified Berger code. The circuits f c and C are implemented separately. The additional area overhead for the implementation of C is computed in [27]. Thus, an arbitrary single gate fault can influence either the functional bits or the check bits. All possible errors of the functional bits are unidirectional and all single gate faults within f c or C are immediately detected by the Berger y 1 y 2 y m 3

4 code checker when they force an output to be erroneous for the first time. A method for the design of unidirectional circuits was described in [15]. In [13], unidirectional circuits are designed in such a way that all necessary inverters are located at the inputs of the circuit, and only algebraic operations are applicable during circuit optimization. Here we propose a method of circuit transformation based on the duplication of selected nodes of an arbitrarily given combinational circuit. For other applications, the duplication of selected gates was proposed in [25], [18], [19]. x 2 g0 1 x 2 3 g1 1 Fig. 3 In our approach, the non-unidirectional elements ( and in general very few additional elements) are duplicated. The general idea will be explained by the very simple circuit f 1 of Figure 1. g 1 is the only non unidirectional gate of circuit f 1 in Figure 1. Gate g 1 is duplicated into g 1 0 and g 1 1, respectively. g 1 0 (g 1 1 ) is connected to the outputs of f 1 such that all paths from g 1 0 (g 1 1 ) to the outputs have an even (odd) number of inverters. The resulting unidirectional circuit f 1 is represented in Figure 3. As is always the case, faults of the input lines which are equivalent to input signal modifications cannot be detected as erroneous if the inputs are not encoded. Possible input and output encodings for the design of unidirectional circuits are investigated in [16] and are not considered in this paper. In reality, circuit gates may be simultaneously connected to many different outputs by different paths with different numbers of inverters. The question arises if it is always possible to duplicate only a selected number of the gates to obtain a unidirectional circuit. The answer is yes, and it can be shown that the number of gates of the unidirectional circuit is less then twice the number of gates of the original circuit. For MCNC benchmark circuits, the average overhead of the duplicated elements is 16 %. y 1 y 2 y 3 3. Redesign of unidirectional circuits In this section, we describe how an arbitrarily given combinational circuit can be transformed into a unidirectional circuit f u with the same behavior. Contrary to [13], [15] where all the necessary inverters are directly connected to the primary inputs of the transformed circuit, inverters are allowed to be located within the circuit in the approach proposed here. Thus, the area overhead for the transformed circuit can be significantly reduced in comparison to [13]. The original circuit f is supposed to be given as a net list of gates, where G={g 1,..., g N } denotes the set of gates. The circuit f is transformed into the corresponding unidirectional circuit f u in the following manner. 1. We determine the set G u G of functional or structural non-unidirectional gates f. (Structurally non-unidirectional elements can be functionally unidirectional. Whether or not they are functionally unidirectional can be checked by condition 1). 2. For every non-unidirectional gate g i G u, we determine the transitive fanout T(g i ), i. e. the set of gates which are connected by a path from g i to one of the outputs of f. g i is considered to be an element of T(g i ). 3. The transitive fanout T(g i ) of all non-unidirectional gates is computed as T G u = T g. g G i i u 4. All the gates g of the transitive fanout, g T(G u ) are initially duplicated into g 0 and g 1 with an even (0) and odd (1) superscript. 5. The original gates of f which are elements of the transitive fanout T(G u ) are removed from f. 6. The duplicated gates will be connected according to the following rules: 6.1. If the output of the gate g T(G u ) in f is directly connected (via an inverter) to a circuit output s, then f 0 ( f 1 ) is directly connected (via an inverter) to the output s in f u If for g, h T(G u ) in f the output of the gate g is connected to an input of gate h via an even (odd) number of inverters, the gate g k ( g k+1mod2 ) is connected via the same number of inverters to the corresponding input of h k in f u, for k=0, If for g G \ T(G u ) and h T(G u ) in f the output of g is connected (via an even or odd number of inverters) to an input of h, then in f u the output of g is connected to the corresponding inputs of both the gates h 0 and h 1. 4

5 6.4. If a primary input l in f is connected to an input of a gate g, g T(G u ) then the primary input l in f u is connected to the corresponding inputs of the gates h 0 and h Gates that are not connected to the outputs of f u are deleted. Let us now illustrate the proposed method by the example shown in Figure 4, with G={1, 2,..., 14}. 2 x 5 5 With the exception of gate 9, all the gates of f are in T(G u ). All the gates g T(G u ), ( all the gates except gate 9) are duplicated into g 0 and g 1 according to rule 4. The original gates of f which are elements of T(G u ), are removed from f by rule 5. Now the gates are connected according to rule 6. Since gate 7 in f is directly connected to the output y 1, gate 7 0 is connected to y 1 in f u but not 7 1. Gate 14 is connected to output y 3 via one inverter; therefore, gate 14 1 is connected via an inverter to the output y 3 (6.1). x x 4 3 x 7 x y x x 8 x y 2 y 3 x x 4 x x y 1 Fig. 4 x y 2 For the circuit f in Figure 4, we now determine the unidirectional circuit f u ; the result is shown in Figure 5. The set G u of structural non-unidirectional gates is G u ={1,2,3,4,8}. For example, gate 4 is structurally nonunidirectional since there are two paths. ( y 1 with an odd number of inversions and 4-1-y 2 with an even number of inversions) to the different outputs y 1 and y 2 ; thus, gate 4 is an element of G u. On the other hand gate 10 is unidirectional since it is only connected to one output. The transitive fanouts of the gates g G u are T(1) = {1, 2, 3, 4, 5, 6, 7, 11}, T(2) = {2, 4, 5, 6, 7, 11}, T(3) = {3, 4, 5, 6, 7, 11} T(4) = {4, 5, 6, 7, 11} and T(8) = { 8, 10, 11, 12, 13, 14}. The transitive fanout T(G u ) of all the non-unidirectional gates is T(G u ) = T(1) T(2) T(3) T(4) T(8) = = {1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14}. x Fig. 5 Since gate 12 is connected to gate 14 via an inverter in f gate 12 0 is connected to gate 14 1 and gate 12 1 is connected to gate 14 0 in f u. Since in f gate 4 is directly connected to gate 11 in f u, gate 4 0 is connected to gate 11 0 and gate 4 1 is connected to 11 1 (6.2) The only gate g G / T(G u ) is gate 9. In f gate 9 is connected to gate 10. According to 6.3, gate 9 ( which is not duplicated) is connected both to gate 10 0 and gate The primary input x 2 of f is connected to gate 1. According to rule 6.4, x 2 is connected both to gate 1 0 and gate 1 1. Now the gates not connected to any output are deleted (7). y 3 5

6 These are the gates 7 1, 5 1, 6 0, 11 1, 14 0 and These gates are crossed out in Figure 5. The original circuit f consists of 14 gates and the unidirectional circuit consists of 20 gates. Figure 5 shows that after the circuit transformation the inverters are not moved to the primary inputs. It is easy to see that f and f u are functionally equivalent. To show this we suppose that the gates of f and f u are levelized. The level of the primary inputs is 0 and the level of a gate g is n+1 if all its immediate predecessors have a level less than n+1. The values of the corresponding primary inputs (at level 0) are equal for f and f u. Let g be a gate of level 1 of f and let g, g {g, g 0, g 1 } be the corresponding gate of f u of level 1. g and g are connected to the same primary inputs and therefore the outputs of g and g are identical. Let us assume that the outputs of all the gates g of f with level (g) i and g, g {g, g 0, g 1 } of f u with level (g) i are identical. Let h be a gate of f with level (h)=i+1 and let h be connected to its immediate predecessors h 1,..., h m with level (h j ) i, j = 1,..., m. Then h of f u with level i+1 is connected to its immediate predecessors h 1,..., h m, h {h, h 0, h 1 }, h j {h j, h j 0, h j 1 }. Since the outputs of h j of f and h j of f u are identical, the inputs of h and h and therefore their outputs are also identical. Thus, for every level, the outputs of the corresponding gates of f and f u are identical which implies that f and f u are equivalent. In Figure 4, level 0 is assigned to the inputs,..., 3, level 1 to the gates 1, 8, 9, level 2 to the gates 2, 3, 10, level 3 to the gates 4, 12, 13, level 4 to the gates 5, 6, 11, 14, level 5 to the gate 7 and the outputs y 2, y 3 and level 6 to the output y 1. At level 1, the inputs of the gates 1 0 and 1 1 of f u in Figure 5 are the same (x 2, ) as for gate 1 of f in Figure 4. Therefore, the output signals of the gates 1 0, 1 1 in f u and 1 in f are identical. The inputs of gate 2 of f are connected to the output of gate 1 and to the primary input, respectively. The inputs of gate 2 0 of f u are connected to the output of gate 1 1 and to the primary input. Since the output of gate 1 1 is identical to the output of gate 1, the output of gate 2 0 is identical to the output of gate 2. Similarly, the inputs of gate 2 1 of f u are connected to the output of gate 1 0 and to the primary input x 2. Since the output of 1 0 is identical to the output of gate 1 in f, the output of gate 2 1 is identical to the output of gate 2. Thus, the outputs of gate 2 in f and gates 2 0 and 2 1 in f u are equal. Similarly, it can be shown that all the corresponding gates g in f and g, g 0, g 1 in f u have equal output signals. Now we show that the modified circuit f u is unidirectional. Let g be a gate of f u. We distinguish the following cases: 1. g = g 0 has superscript 0. If g 0 is connected by a path p j to an output y j then the number of inverters on this path p j is even by construction of f u. Thus if g 0 is connected by different paths p j, p k,..., p 1 to different outputs y j, y k,..., y 1, the number of inverters of these paths p j, p k,..., p 1 is even. If a fault of gate g results in an error of y j, y k,..., y 1, this error has to be unidirectional. 2. g = g 1 has superscript 1. If g 1 is connected by a path p j to an output y j, the number of inverters of p j is odd by the construction of f u. By the same consideration as in the case of g 0, an error of gate g 1 is unidirectional. 3. g has no superscript. Then g is unidirectional in f. Thus, for every output y 1,..., y m, the network of gates connecting the output of g to an output y i in f u is identical to the network of gates connecting the output of g to the output y i in f. Therefore, a fault in g results in the same errors in both f and f u. Since g is unidirectional in f, it is unidirectional in f u. As an example we consider gate 1 of f in Figure 4. Gate 1 is connected to the output y 1 by two paths ( y 1 and y 1 ) with an even number of inverters and two paths ( y 1 and y 1 ) with an odd number of inverters. Gate 1 is also connected to the output y 2 by one path ( y 2 ) with an even number of inverters and one path ( y 2 ) with an odd number of inverters. In the unidirectional circuit f u of Figure 5, gate 1 0 is connected to the output y 1 by the two paths y 1 and y 1, each with an even number of inverters. Gate 1 1 of f u is connected to the output y 1 by the two paths y 1 and y 1, each with an odd number of inverters. Gate 1 0 of f u is also connected to the output y 2 by the path y 2 with an even number of inverters, and gate 1 1 is connected to y 2 by the path y 2 with an odd number of inverters. According to its superscript 0, gate 1 0 is connected to the outputs y 1 and y 2 by paths with an odd number of inverters only, and gate 1 1 is connected to the outputs y 1 and y 2 only by paths with an odd number of 6

7 inverters. Gate 9 is unidirectional in f. It is connected to the output y 3 by a Boolean network consisting of the gates 10,12,13 and 14. In f u, gate 9 is connected to the output y 3 by a Boolean network of the gates 10 0, 10 1, 12 0, 13 1 and Since the inputs and outputs of gate 10 in f and gates 10 0 and 10 1 in f u are identical, a fault in g results in the same error in both f and f u. Here, the output y 3 will be erroneous in the same way in f and f u. 4. Redundant faults and redundancy removing In this section, we describe how the transformation of a circuit f into an unidirectional circuit f u can add redundant faults. These redundant faults can be utilized to simplify the unidirectional circuit f u. To explain this, let g be a gate of f which is non-unidirectional with its output connected to at least two different outputs by paths with an odd and an even number of inverters. If a fault at the output of g occurs, both a path with an even number of inverters or an odd number of inverters can be sensitized to propagate this fault to an output of f. For details see, for example [19]. Let gate g of f be transformed into gates g 0 and g 1 of f u. The input signals and therefore the output signals of g in f and g 0 and g 1 in f u are always the same as long as no error occurs. However, the output of gate g 0 (g 1 ) is now connected to the outputs of f u by paths with an even (odd) number of inverters only. If a fault occurs at the output of g 0 ( g 1 ), a path with an even (odd) number of inverters has to be sensitized to propagate this fault to an output of f u. We assume that stuck-at-0/1 faults may occur at the output of g. Then, in the terminology of the D - algorithm [19], [20], a D or D has to be propagated along a sensitized path to the outputs of f. As examples, we discuss the following typical situations: 1. Both D and D can be generated and propagated along a sensitized path with an even number of inverters and along a sensitized path with an odd number of inverters. In the transformed unidirectional circuit, the gate g 0 is connected to the outputs of f u only by paths with an even number of inverters. Since both D and D of g in f can be generated and propagated along a sensitized path with an even number of inverters, D and D of g 0 in f u can be also propagated to the outputs of f u. Analogously, we conclude that both D and D of g 1 can be generated and propagated to the outputs of f u and hence all the stuck-at-0/1 faults at the outputs of g, g 0 and g 1 are testable in f and f u. 2. Only D can be generated and propagated along a sensitized path with an even number of inverters and along a sensitized path with an odd number of inverters. D can be only propagated along a path with an odd number of inverters. Then D and D at the output of g 1 can be propagated to the outputs of f u. On the other hand, D (but not D) at the output of g 0 can be propagated to the output of f u. In this situation, both the stuck-at-0/1 faults at the outputs of g and g 1 are testable, but at the output of g 0 only the stuck-at-1 fault is testable, and the stuck-at-0 fault at the output of g 0 is redundant. The existence of a redundant fault can be used further to simplicity the circuit f u by redundancy elimination as described in [21], for example. In reality, however, very few redundant faults are generated by transforming the circuit f into an unidirectional circuit f u. 5. Experimental results Table 1 shows the experimental results for the transformation of 20 MCNC benchmark circuits into unidirectional circuits. The name of the original circuit, the number of inputs PI, the number of outputs PO are given in columns 1-3. The area of the original circuits determined by use of the standard library of the synthesis system SIS nandnor.genlib [23]. For the transformed unidirectional circuits the area overhead in percent of the original circuit is given in column 4. The average area overhead due to the proposed circuit transformation for all considered benchmark circuits is 16% of the area of the original circuit. For more than half of the circuits the area overhead is less than 10%. Thus the area overhead for the proposed design method of unidirectional circuits is less than half of the area overhead of 38% obtained in [13] (for a subset of the benchmarks circuits used in [13] an area overhead of 22% was obtained in [26]), where all the necessary inverters of the unidirectional circuits are located at the circuit inputs. For a combinational circuit with G gates, ng non-unidirectional gates and sng structural non-unidirectional gates, the value a e where is a good estimate for the necessary additional area overhead. Thereby β is a constant. The value of β is experia = β ng β sng e G G 7

8 mentally determined as β = 103,44 from the considered benchmark circuits. The number G of gates, the number ng of non-unidirectional gates, the number sng of structurally non-unidirectional gates, the expected area overhead a e and the difference d = a a e a % of the area overhead in percent determined by the described algorithm and the expected area overhead are represented in columns 6 to 10 of Table 1. The average difference d is only 7.05 %. Table 1. Area Overhead by Redesign of Circuits Circuit name #PI #PO Area overhead (%) G ng sng a e (%) d (%) apex , ,31 9,61 pcle , ,95 apex , ,52 0,25 term , ,28 3,04 count , ,52 2,81 x , ,07 8,81 sct , ,21 4,75 x , ,21 11,69 ttt , ,31 7,01 pm , ,17 0,77 pcler , ,41 2,64 frg , ,07 13,11 alu , ,34 1,69 alu , ,55 2,39 misex , ,24 14,31 misex , ,17 11,01 cu , ,93 24,4 lal , ,45 11,43 duke , ,10 14,36 c , ,21 1,80 b , ,10 2,06 example , ,28 5,26 cht , ,93 8,13 Average for all circuits : 15,28 Average difference : 7,05 8

9 Principally, new redundant faults can be generated by the proposed circuit transformation. In general, the percentage of redundant faults is small for both the original and the redesigned unidirectional circuit. The circuit bw is the only case where a 100 % testable non-unidirectional circuit is transformed into a unidirectional circuit having redundant faults. In all other cases, 100 % testable circuits are transformed into 100 % testable unidirectional circuts. 6. Conclusions In this paper, a new method for the design of unidirectional combinational circuits is proposed. The arbitrarily given combinational circuit is transformed into an unidirectional circuit such that every single gate fault can only be propagated to the circuit outputs on paths with an even or an odd number of inverters. Selected gates of the original circuit are duplicated. By the proposed method, inverters are not moved to the primary inputs, although it is necessary in other known design methods. The average area overhead for the circuit transformation for MCNC benchmark circuits is only 16% of the original circuit, which is less than half the value achieved with other methods.theoretically, the circuit transformation can result in additional redundant faults which can be utilized further to optimize the derived unidirectional circuit. The simulation experiments, however, show that the number of newly generated redundant faults is negligible. References [1] Lala P. K., Fault Tolerant and Fault Testable Hardware Design, Prentice Hall, Englewood-Cliffs, N. J., 1985 [2] Saposhnikov V. V., Saposhnikov Vl. V., Self-Cheking Checkers for Balansed Codes, Automation and Remote Control, vol. 53, Nr. 3, part 1, pp , 1992 [3] Saposhnikov V. V., Saposhnikov Vl. V., Self-Checking Discrete Circuits, (in russ.) Energoatomizdat, St. Petersburg, 1992 [4] Sedmark R. M. Design for Self-Verifikation. An approach for Dealing with testability problems in VLSI-based Design, Proc. 1979, Int. Test Conference, pp , 1979 [5] Gupta S. K., Pradhan D. K., Can Concurrent Checkers Help BIST?, Proc International Test Conference, pp , 1992 [6] Gupta S. K., Pradhan D. K., Utilization of Concurrent Checkers During Built-in-Self-Test, IEEE Transactions on Electronic Computers, Jan [7] Fujiwara E., Muto N. and Matsuoka K., A Self-Testing Group Parity Prediction Checker and its Use for Built-in-Testing, IEEE Trans. Comp., C-33, Nr. 6, pp , 1984 [8] Rao T. R. N., Fujiwara E., Error Control Coding for Computer Systems, Prentice Hall, 1989 [9] Sogomonyan E. S., Design of Built-in Self-Cheking Monitoring Circuits for Combinational Devices, Automation and Remote Control, vol. 35, Nr. 2, part 2, pp , 1974 [10] Fujiwara E., Self-Testing Group Parity Prediction Checker and its Use for Built-in-Testing, Proc. 13th Test Symposium Fault Tolerant Computing, Milano, pp , 1983 [11] Ashajee M. J., Reddy S. M., On Totally Self-Checking Checkers for Separable Codes, IEEE Trans. Comp, C-16, Nr. 8, pp [12] Sogomonian E. S., Reliability of Self-Testing using Functional Diagnostic Tools, Automation and Remote Control, vol. 49, Nr. 10, part 2, pp , 1988 [13] De K., Natarajan C., Nair D., Banerjee P., RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits, IEEE Transactions on very large Integration (VLSI) Systems, Nr. 2, pp , 1994 [14] Morosov A., Saposhnikov V. V., Saposhnikov Vl. V., Gössel M., Self-Cheking Combinational Circuits with Unidirectionally Independent Outputs, Technical Report Max-Planck Fault Tolerant Computing Group Nr. MPI-I , 1995, to be published in Journal of VLSI. [15] Jha N. K., Wang S.-J., Design and Synthesis of Self- Checking VLSI Circuits, IEEE Transaction CAD, vol. 12, Nr. 6, pp , 1993 [16] Busaba F. Y., Lala P. K., Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors, JETTA, Nr. 5, pp , 1994 [17] Sogomonyan E. S., Gössel M. Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs, JETTA, Nr. 4, , 1993 [18] Bogliolo A., Damiani M., Synthesis of Combinational Circuits with Special Fault-Handling Capabilities, 13th IEEE Test Symposium, pp , Princeton, N. J., 1995 [19] Gössel M., Sogomonyan E. S., Self-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design, in IFIP Transactions A-42, Computer Science and Technology, VLSI-93, (T. Yanagawa, P. A. Ivey eds.) pp , North-Holland, 1994 [20] Fujiwara H., Logic Testing and Design for Testability, The MIT Press Cambridge, Massachusetts, London, England, 1985 [21] Roth J. P., Bouricius W. G., Schneider P. R., Programmed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits, IEEE Trans., vol. EC-16, Nr. 5, pp , 1967 [22] Abramovici M., Breuer M., Friedman H., Digital Systems Testing and Testable Design, Computer Science Press, New York,

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