Delay Variation Tolerance for Domino Circuits

Transcription

1 Delay Variation Tolerance for Domino Circuits Student: Kai-Chiang Wu Advisor: Shih-Chieh Chang Department of Computer Science National Tsing Hua University Hsinchu, Taiwan 300, R.O.C. June, 2004

2 Abstract Factors of delay variation such as process variation and noise effects may cause a manufactured chip to violate the pre-specified timing constraint. Traditional methods add a pessimistic timing margin to alleviate delay variation problems. In this thesis, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that slacks of nodes along critical paths is zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. The auxiliary sub-circuit can cause critical paths to become false paths or imperceptible paths [8] so as to improve the capability of delay variation tolerance. Experimental results are very encouraging. 2

3 Contents ABSTRACT...2 CONTENTS...3 LIST OF FIGURES...4 LIST OF TABLES...5 CHAPTER 1 INTRODUCTION...6 CHAPTER 2 DELAY VARIATION TOLERANCE IN DUPLEX DOMINO SYSTEMS PROPERTIES OF DUPLEX DOMINO CIRCUITS PROBLEM FORMULATION...10 CHAPTER 3 RE-SYNTHESIS FOR DELAY VARIATION TOLERANCE OUR RE-SYNTHESIS FRAMEWORK AREA REDUCTION BY WIRE REMOVAL AREA REDUCTION BY SIGNAL SHARING SLACK ANALYSIS AFTER RE-SYNTHESIS...20 CHAPTER 4 DELAY TOLERANCE ON INTERNAL SIGNALS...23 CHAPTER 5 EXPERIMENTAL RESULTS...27 CHAPTER 6 CONCLUSIONS...35 REFERENCES

4 List of Figures Figure 1: An example of delay variation tolerance in a domino circuit... 7 Figure 2: A duplex system... 9 Figure 3: An Example of d t delay tolerance Figure 4: The original circuit Figure 5: The new circuit after removing d t -side input wire w 1 in C Figure 6: Proof of Theorem Figure 7: The re-synthesized circuit after wire removal stage Figure 8: The re-synthesized circuit after signal sharing stage Figure 9: The slack of each node in the re-synthesized circuit Figure 10: The example circuit of delay tolerance on internal signals Figure 11: The re-synthesized circuit with delay tolerance on primary output F 1 in Figure Figure 12: The re-synthesized circuit with delay tolerance on internal signal w f in Figure Figure 13: The re-synthesized circuit with delay tolerance on primary output F 1 in Figure Figure 14: The pseudo code of our re-synthesis framework Figure 15: The distribution curves of Monte-Carlo samples

5 List of Tables Table 1: Comparison between the original circuit and its corresponding re-synthesized circuits...29 Table 2: Statistical results of Monte-Carlo experiments

6 Chapter 1 Introduction Domino circuits offer both smaller area and higher speed than static complementary gates; therefore, they are extensively used in today s high-performance designs. On the contrary, circuit delay in advanced technologies is difficult to estimate because of process variation and noise effects such as crosstalk and voltage drop [1][2]. These factors could make the performance of a design irregularly fluctuate with a small amount of delay variation, and cause a manufactured chip to violate the pre-specified timing constraint. As a result, delay variation tolerance in domino circuits is becoming important and necessary. Traditionally, to alleviate the effect of delay variation and increase reliability, designers often have to employ pessimistic timing margins. However, adding timing margin may unnecessarily slow down the design [5][7]. Statistics [4] shows that a fabricated ASIC may run up to 40% faster than predicted by the standard (worst-case) timing analysis. Unlike static circuits, dynamic domino circuits operate in two phases: the pre-charge phase and the evaluation phase. For avoiding racing problems, domino circuits require all signals except primary inputs to have only rising transitions during the evaluation phase. Due to the rising-transition-only property, 6

7 delay variation tolerance in domino circuits is much easier to accomplish than that in static circuits. a b c d e a b d C 1 C 2 F 1 F 2 F 1 Figure 1: An example of delay variation tolerance in a domino circuit Our basic idea of delay variation tolerance is to combine a (target) domino circuit with a redundant auxiliary sub-circuit, which is illustrated in the following example. A domino circuit C 1 in Figure 1 implements logic function F 1 = (a+b+c)d+e = ad+bd+cd+e. For delay tolerance on F 1, we construct an auxiliary circuit C 2 implementing F 2 = (a+b)d = ad+bd and generate a new output F 1 = F 1 +F 2. Because the on-set of F 1 apparently covers that of F 2 (i.e., F 1 F 2 ), the new function F 1 = F 1 +F 2 is identical to the original function F 1. We will show that appending circuit C 2 does not change the functionality of the original circuit but have the effect of delay tolerance. Consider an input pattern (a, b, c, d, e) = (1, 0, 0, 1, 0) which induces transitions along critical (highlighted) paths in both C 1 and C 2. Since both F 1 and F 2 have only rising transitions and feed into an OR gate, whichever rising signal arriving earlier will dominate the OR gate s output. In other words, the earlier arrival of either F 1 or F 2 determines the output value instead of the later one. Delay variation tolerance is consequently achieved 7

8 because late arrival signals will not influence the resultant circuit delay. Slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. The degree of delay variation tolerance is formulated by the concept of slacks [3]. In this thesis, we discuss how to achieve certain degree of variation tolerance by incorporating the auxiliary circuit C 2. The key contribution of this thesis is to derive innovative theorems which allow us to carry out a small-size C 2 while maintaining the capacity of delay variation tolerance. We have performed Monte-Carlo experiments. The results show that about 51% of samples of an original circuit can meet certain delay requirement; however, about 73% of samples of the re-synthesized circuit can satisfy the same requirement. The rest of this thesis is organized as follows. Section 2 describes delay variation tolerance in duplex systems. Our re-synthesis technique for delay variation tolerance is proposed in Section 3. Section 4 demonstrates the advantages of delay tolerance on internal signals. Finally, we present our experimental results and conclusions. 8

9 Chapter 2 Delay Variation Tolerance in Duplex Domino Systems 2.1 Properties of Duplex Domino Circuits Original circuit C 1 F 1 F 1 Duplicate block C 2 F 2 Figure 2: A duplex system Let a domino circuit C 1 be under consideration for delay variation tolerance. A duplex system is shown in Figure 2, which consists of the original circuit C 1, its duplication C 2, and an OR gate taking the outputs of C 1 and C 2 as its inputs. There are two properties for a duplex domino system. First, it performs the same function as the original circuit. Secondly, a transition travels along a path in C 1 also travels along the mirror path in C 2. Since domino circuits have only 0-to-1 transitions, the OR gate s output transits from 0 to 1 when the earlier transition arrives. A duplex domino system has the capacity of delay variation tolerance because any delay variation postponing either C 1 or C 2 will not affect the 9

10 eventual timing result. Still, there is more than 100% area overhead for a duplex system, making the duplex system impractical. In the remainder of this thesis, we will explain how to reduce C 2 while maintaining the given degree of variation tolerance. 2.2 Problem Formulation Let us first define the degree of delay variation tolerance. The degree of delay variation tolerance can be quantized with the smallest slack of gates/wires in a circuit. A circuit is defined to have d t delay tolerance if the delay of each gate/wire can increase d t without affecting the delay of the circuit; that is, the slack of each gate/wire is at least d t. For example in Figure 3 where the delay of each gate is 1, the number on each gate represents the slack of the gate. The circuit has 0 delay tolerance since the smallest slack in the circuit is 0. The slack of each gate/wire in a duplex domino system is infinite (i.e, d t = ), which is over-protective for delay variation problems. In general, delay tolerance of 10%~20% of the original circuit delay is sufficient for our considerations of process variation and noise effects. Given a delay tolerance value d t and a circuit, our objective is to re-synthesize the circuit so that every gate/wire in the new circuit can tolerate at least delay variation d t. Based on the definition of d t delay tolerance, the smallest slack in the re-synthesized circuit is d t. 10

11 Figure 3: An Example of d t delay tolerance 11

12 Chapter 3 Re-synthesis for Delay Variation Tolerance 3.1 Our Re-synthesis Framework To accomplish a given delay tolerance value d t without adding too much area overhead, a practical scheme originated from a duplex system is proposed. Our re-synthesis steps are as follows. (1) Begin with a duplex system in Figure 2. (2) Remove and modify some wires in C 2 for area reduction while maintaining the tolerance value. We now discuss how to perform wire removal and modification in C 2. Redundant wires in a duplex system can be removed to reduce the area overhead, but slacks of some nodes change simultaneously. As a result, the main principle of this thesis is to reduce the area overhead by removing redundant wires while keeping slacks of all nodes equal to or greater than d t. 3.2 Area Reduction by Wire Removal Assume the original circuit C 1 implements logic function F 1, the redundant auxiliary circuit C 2 implements F 2, and the combinative output is F 1 = F 1 +F 2. If 12

13 the on-set of F 2 is a sub-set of that of F 1 (i.e., F 2 F 1 ), we can preserve the original functionality of F 1 (= F 1 +F 2 = F 1 ). While there are many possible Boolean functions which satisfy F 2 F 1, we only consider wire removal in C 2 to reduce the on-set of F 2. Before presenting our theorems, we describe what wires in C 2 can be removed to maintain F 2 F 1 in the following lemma. Lemma 1: All direct input wires to OR gates in C 2 are redundant and can be simultaneously removed (replaced by a non-controlling value, i.e. a logic 0). Proof: Taking only OR gates into consideration is a matter of functionality. If the on-set of the original function F 1 doesn t include that of the auxiliary function F 2, there exist at least one input vector which evaluates F 1 to be 0 and F 2 to be 1, leading to inconsistence between the original circuit and the re-synthesized one. It s not difficult to perceive that input wire removal of an OR gate decreases its on-set; contrarily, input wire removal of an AND gate increases its on-set. Therefore, direct input wires to only OR gates in C 2 are removable in our re-synthesis approach. Q.E.D. Let the delay tolerance value be d t and the timing requirement of the circuit under consideration be d r. A path is called a d t -critical path if its delay is greater than d r minus d t. In other words, a path is a d t -critical path if its delay increases more than d t, the timing requirement will be violated. We say that a node is a d t -critical node if it is along a d t -critical path. One can also find that the slack of a d t -critical node is smaller than d t. For example in Figure 4 where the delay of each gate is 1. Suppose the delay tolerance d t is 1 and the timing requirement d r is 6. In this example, the timing requirement is equal to the length of the longest path. Path {s-b-d-f-g-h-i} is a d t -critical path because its delay is 6 greater than 13

14 d r -d t (6-1=5). In fact, all highlighted paths in Figure 4 are d t -critical paths. Node g is a d t -critical node because it is along a d t -critical path. Besides, all highlighted nodes {a, b, o, d, e, f, g, h, i} are d t -critical nodes. Note that slacks of these d t -critical nodes are 0 smaller than d t = 1. A node is defined to be a d t -dominator if all d t -critical paths to a primary output pass through it. A wire n 1 -> n 2 is a d t -side input if node n 1 is not a d t -critical node but node n 2 is a d t -critical node. In the same example, nodes {g, h, i} are d t -dominators because all d t -critical paths to primary output F 1 must pass through these nodes. Wire w 1 (l -> i) is a d t -side input because node l is not a d t -critical node but node i is. Similarly, wires {w 2, w 3, w 4, w 5, w 6 } are also d t -side inputs. p q s t r j a b w 5 w 6 o d w 3 w 4 e f k g l h w 1 i F 1 m n w 2 d t -critical path: All highlighted paths d t -critical node: {a, b, o, d, e, f, g, h, i} d t -dominator: {g, h, i} d t -side input: w 1 (l -> i), w 2 (n -> h), w 3 (j -> e), w 4 (r -> f), w 5 (p -> o), w 6 (q -> d) Figure 4: The original circuit 14

15 Theorem 1 [3]: A d t -side input wire w to an OR d t -dominator in C 2 can be removed without violating the requirement of d t delay tolerance. Proof: On the basis of Lemma 1, a d t -side input wire to an OR d t -dominator in C 2 can be removed without violating the functional requirement. On the other hand, the main reason for maintaining the tolerance value d t is as follows. After a d t -side input wire to an OR d t -dominator in C 2 is replaced by a non-controlling value, a transition travels along a d t -critical path in C 1 still travels along its mirror path in C 2. In other words, when a d t -critical path in C 1 propagates a (rising) transition, its mirror path in C 2 definitely transits from 0 to 1. Hence, circuits C 1 and C 2 will have equivalent output value whenever an input pattern activates d t -critical paths in both C 1 and C 2. As long as either C 1 or C 2 propagates its output in time (earlier than d r ), the pre-specified d r and d t are met. Q.E.D. Lemma 1 states that input wires to OR gates in C 2 are redundant; Theorem 1 indicates that removal of d t -side input wires to OR d t -dominators in C 2 can preserve the requirement of d t delay tolerance. Take the circuit in Figure 4 as an example. A duplex system can be constructed by two duplicates (C 1 and C 2 ) of the original circuit. According to Theorem 1, we can remove wire w 1 in C 2 by replacing it with a logic 0 since it is a d t -side input to OR d t -dominator i. The new circuit of C 2 after wire removal is shown in Figure 5. Note that those nodes which don t have any fanout such as nodes k and l can be recursively removed. 15

16 j a o e g h F 2 b d f m n Figure 5: The new circuit after removing d t -side input wire w 1 in C 2 The area overhead can be significantly reduced by Theorem 1. Unfortunately, more and more d t -critical nodes in recent circuits because of timing and low-power optimization lead to less and less d t -dominators, diminishing the effect of Theorem 1. But we observed that d t -side input wires to some other gates besides OR d t -dominators could still be removed to further reduce the area overhead. These supplementary removable wires are explained in the following theorem. 16

17 w 1X w 1Y d 1 C 1 w 2X 0 w t t w 2Y d 2 C 2 (a) w 1X w 1Y d 1 C 1 w 2X 0 w t t w 2Y d 2 C 2 (b) Figure 6: Proof of Theorem 2 We say that a node is a transitive fanin of node n if there is a path from the node to node n. Theorem 2: If a wire w is a d t -side input to an OR gate in C 2 which is a transitive fanin of an OR d t -dominator, the wire w can be removed without violating the requirement of d t delay tolerance. Proof: On the basis of Lemma 1, a d t -side input wire to an OR gate in C 2 can be removed without violating the functional requirement. Before proving that the tolerance value d t is maintained, we illustrate what will happen if a d t -side input 17

18 wire to an OR gate in C 2 which is transitive fanin of an AND d t -dominator is removed. Assume that node d 2 in Figure 6(a) is an AND d t -dominator. After d t -side input wire w t to OR gate t in C 2 which is a transitive fanin of d 2 is removed, the on-set of wire w 2Y, a direct input of d 2, decreases. When there is an input vector evaluating w 1X to be 1 via a d t -critical path but w 1Y to be 1 via a non-d t -critical path, w 2X is also 1 while w 2Y could be sensitized to be 0 by the same input vector. This logic 0 determines the output of d 2, and masks the logic 1 which activates a d t -critical path, destroying the ability of delay variation tolerance. Nevertheless, the similar adversity doesn t take place if node d 2 is an OR d t -dominator, as shown in Figure 6(b). After d t -side input wire w t in Figure 6(b) is removed, the on-set of wire w 2Y decreases. When w 1Y is evaluated to be 1 via a non-d t -critical path, w 2Y could be sensitized to be 0. This logic 0 doesn t determine the output of d 2 if w 1X and w 2X are both 1 via d t -critical paths. Therefore, a transition travels along a d t -critical path in C 1 still travels along its mirror path in C 2 after wire removal according to Theorem 2. Q.E.D. We illustrate this theorem with the same circuit in Figure 4. First, wire w 3 (j -> e) doesn t satisfy the condition in Theorem 1 because node e is not a d t -dominator. However, wire w 3 (j -> e) satisfies the condition in Theorem 2 because node e is a transitive fanin of OR d t -dominator g. Thus, wire w 3 in C 2 can be removed. In fact, wires {w 3, w 5, w 6 } all satisfy the condition in Theorem 2 so wires {w 3, w 5, w 6 } in C 2 are removable. The resultant circuit is shown in Figure 7. 18

19 j a b o d e f k l g h i m n C 1 a 2 g 2 h 2 b 2 f 2 m 2 n 2 C 2 Figure 7: The re-synthesized circuit after wire removal stage 3.3 Area Reduction by Signal Sharing We can also adopt signal sharing [3] to further reduce the area overhead. Those signals which implement equivalent function but not belong to d t -critical paths can be shared. For example in Figure 7, the output of node n in C 1 and that of node n 2 in C 2 have the same functionality. We can share the output signals of n and n 2, as demonstrated in Figure 8. After sharing, the required time of node n doesn t change but the arrival time increases owing to the additional fanout from node n to node h 2. We need to re-compute the slack of node n. If the slack of node n is equal to or greater than d t, we can indeed perform the sharing; otherwise, the sharing is not allowed. Suppose all equivalent signals are allowable to be shared without violating the requirement of d t delay tolerance. The final circuit is shown in Figure 8. 19

20 j a b o d e f k l g h i m n C 1 a 2 g 2 h 2 b 2 f 2 C 2 Figure 8: The re-synthesized circuit after signal sharing stage Note that the delay of a re-synthesized circuit can be larger or smaller than that of the original one. The delay of a re-synthesized circuit may be larger on account of the extra delay of the decision OR gate. On the other hand, because some critical paths become false paths, the delay of a re-synthesized circuit may be smaller. 3.4 Slack Analysis after Re-synthesis An imperceptible path [8] is such a path that any change only in the length of imperceptible paths (increase or decrease) can never affect the circuit delay. For every input vector, the path cannot independently determine the arrival time at the circuit output [8]. Theorem 3: After wire removal according to Theorem 1 and Theorem 2, all d t -critical paths are either false paths or imperceptible paths [8]. 20

21 Proof: On the basis of Theorem 1 and Theorem 2, a transition travels along a d t -critical path in C 1 also travels along its mirror path in C 2 after wire removal. Hence, circuits C 1 and C 2 will have equivalent output value whenever an input pattern activates d t -critical paths in both C 1 and C 2. Since domino circuits have only rising transitions, whichever rising signal arriving earlier will dominate the decision OR gate s output. In statistical timing analysis, the delay of each gate is given by a probability density function. If the delay of a d t -critical path P 1 in C 1 is greater than that of its mirror path P 2 in C 2 under certain delay assignment, the circuit delay is determined by P 2 because P 1 has become a false path. Inversely, if the delay of P 1 is smaller than that of P 2, the delay of P 2 rather than P 1 determines the circuit delay. We can thus infer that all d t -critical paths after wire removal are either false paths or imperceptible paths. Q.E.D. In Figure 8, all highlighted paths are either false paths or imperceptible paths. We now discuss slacks of nodes after re-synthesis. Consider node e in Figure 8. The longest true path passing through node e is {j-e-g-h-i} whose path length is 5. Therefore, node e has the slack of 1 (d r -5) in the re-synthesized circuit in Figure 8 while it has slack of 0 in the original circuit in Figure 4. For another example, since all paths passing through node a are false paths, the slack of node a is infinite. After re-synthesis, all d t -critical paths, whose delays are greater than 5 (d r -d t ), become either false paths or imperceptible paths; that is, the longest true path in the re-synthesized circuit has the delay of 5 (d r -d t ). As a result, the slack of each node in the re-synthesize circuit is at least 1 (d r -(d r -d t ) = d t ), which is shown in Figure 9. 21

22 C C 2 Figure 9: The slack of each node in the re-synthesized circuit 22

23 Chapter 4 Delay Tolerance on Internal Signals The re-synthesis methodology described previously is applied to primary outputs whose arrival time is susceptible to delay variation. We can also employ identical approach to protect the arrival time of internal signals from delay variation. Delay tolerance on internal signals can have advantages of area reduction. j k l w 1 a c e g h i F 1 s t b d f w f m n Figure 10: The example circuit of delay tolerance on internal signals In Figure 10, consider the circuit which is almost the same as that in Figure 4 except node g in Figure 10 is an AND gate. Bold lines in Figure 10 represent d t -critical nodes and d t -critical paths. If the re-synthesis technique is applied to 23

24 only primary output F 1, only d t -side input wire w 1 in C 2 can be removed and the resultant circuit is shown in Figure 11. In this example, the area overhead is large because there is only one removable d t -side input wire. We will show that by employing delay tolerance on internal signal w f, the area penalty can be significantly reduced. The result after performing re-synthesis on w f is shown in the gray blocks in Figure 12. According to Theorem 3, path segment {s-b-d-f} becomes either a false path (segment) or an imperceptible path (segment). Thus, path {s, b, d, f, x, g, h, i} passing through a false path (segment) {s-b-d-f} is also a false path. Similarly, all other paths passing through {t-b-d-f}, {s 2 -b 2 -f 2 }, or {t 2 -b 2 -f 2 } are either false paths or imperceptible paths. Those false paths or imperceptible paths no longer belong to d t -critical paths. Consequently, nodes {a, o, e, g, h, i} in Figure 12 become d t -dominators. When we continue to perform delay tolerance on primary output F 1, d t -side input wires to three OR d t -dominators {o 2, e 2, i 2 } in C 2 become removable. The re-synthesized circuit is shown in Figure 13. The total area overhead of the re-synthesized circuit in Figure 13 is 7 (gates), whereas that of the re-synthesized circuit in Figure 11 without delay tolerance on internal signals is 9 (gates). The pseudo code of our re-synthesis framework is in Figure

25 j a b o d e f k l g h i m n C 1 a 2 o 2 e 2 g2 h 2 b 2 d 2 f 2 C 2 Figure 11: The re-synthesized circuit with delay tolerance on primary output F 1 in Figure 10 s t s 2 t 2 j a b o d e f b 2 f 2 m k l g h i x w f n F 1 Figure 12: The re-synthesized circuit with delay tolerance on internal signal w f in Figure 10 25

26 j k l a o e g h i b d f w f b 2 f2 m n C 1 a 2 g 2 h 2 C 2 Figure 13: The re-synthesized circuit with delay tolerance on primary output F 1 in Figure 12 Re-synthesize_for_Delay_Variation_Tolerance (circuit) { system = construct_an_duplex_system (circuit); nodes = find_d t -critical_nodes_in_c 2 (system, d t ); dominators = find_d t -dominators (system, nodes); foreach d in dominators { remove_d t -side_input_wire (d); } /* d t _fanins are nodes which satisfy the condition stated in Theorem 2. */ fanins = find_d t -fanins (system, nodes, dominators) foreach f in fanins { remove_d t -side_input_wire (f); } share_equivalent_signal (system); } Figure 14: The pseudo code of our re-synthesis framework 26

27 Chapter 5 Experimental Results We have implemented the re-synthesis algorithm in SIS environment and conducted experiments on a set of MCNC benchmarks. Table 1 provides information about the area overhead while Table 2 demonstrates the advantages of delay variation tolerance for domino circuits. We first optimized a circuit with script.delay, and then used delay tolerance values of 10%, 15%, and 20% of the original circuit delay to re-synthesize a circuit. The timing requirement for all re-synthesized circuits is set to be the delay of the original circuit. In Table 1, column one lists the name of the original circuit. Then, we show the results of the original circuit in columns two to five, the results for 10% delay tolerance in columns six to nine, the results for 15% delay tolerance in columns ten to thirteen, and the results for 20% delay tolerance in columns fourteen to seventeen. For a given circuit and its re-synthesized circuits, we provide the area, delay, and slack information. For example, circuit 9symml has the area of 1,317 and the delay of The average slack is Before re-synthesis, there is no gate with infinite slack. When the delay tolerance is 2.14 (= 10%*21.36), the re-synthesized circuit has the area of 1,460 and the delay of The average slack is 2.93 and there are 2 gates with infinite slack in the re-synthesized circuit. When the delay tolerance is 3.20/4.27, the re-synthesized circuit has the area of 27

28 1,605/1,885 and the delay of 21.29/ The average slack is 4.32/5.93 and there are 10/35 gates with infinite slack. On the average, the area overhead for 10%, 15%, and 20% delay tolerance is respectively about 12%, 19%, and 28%. We have also performed Monte-Carlo experiments to demonstrate the effect of delay variation tolerance in Table 2. In the experiment, the delay of a gate is given as a probability density function similar to [6]. We obtained 1,000 samples of an original circuit and 1,000 samples of its re-synthesized circuit with 10% delay tolerance from Monte-Carlo experiments. After that, the delay of each sample is calculated. In Table 2, column one lists the name of the original circuit. Let d r be the delay of the circuit. Column two shows the number of circuit samples whose delays are smaller than {0.8*d r } for the original circuit, and column three shows the number for its re-synthesized circuit. Similarly, columns four to eleven report the numbers of samples whose delays are smaller than {0.9*d r }, {1.0*d r }, {1.1*d r }, and {1.2*d r } for both the original circuit and its re-synthesized circuit. Take circuit 9symml as an example. Let the timing requirement be 1.1*d r (1.1*21.36 = 23.50), 138 samples of the original circuit meet the timing requirement while 249 samples of the re-synthesized circuit satisfy the same requirement. In Figure 15(a), we drew the distribution curves of all Monte-Carlo samples of circuit 9symml and its re-synthesized circuit with 10% delay tolerance. The curves reveal that the timing behavior of the re-synthesized circuit is more stable than that of the original circuit. As well, the distribution curves of circuits comp, f51m, and t481 are respectively shown in Figure 15(b), (c), and (d). 28

29 Table 1: Comparison between the original circuit and its corresponding re-synthesized circuits Circuit Area Origianl circuit Delay Avg. slack #nodes with infinite slack Area 10% delay tolerance 15% delay tolerance Delay Avg. slack #nodes with infinite slack Area Delay Avg. slack #nodes with infinite slack Area 20% delay tolerance Delay Avg. slack #nodes with infinite slack 9symml C C C C C C C C alu apex apex b c cht cm85a cm150a cm151a cm162a comp cordic dalu

30 Table 1: Comparison between the original circuit and its corresponding re-synthesized circuits (cont.) Circuit Area Origianl circuit Delay Avg. slack #nodes with infinite slack Area 10% delay tolerance 15% delay tolerance Delay Avg. slack #nodes with infinite slack Area Delay Avg. slack #nodes with infinite slack Area Delay Avg. slack #nodes with infinite slack f51m frg frg i i i i i i k lal pair rot t term ttt vda x x x x z4ml Avg % delay tolerance 30

31 Table 2: Statistical results of Monte-Carlo experiments Circuit 0.8*d r 0.9*d r 1.0*d r 1.1*d r 1.2*d r O R O R O R O R O R 9symml C C C C C C C C alu apex apex b c cht cm85a cm150a cm151a cm162a comp cordic dalu O: Original Circuit R: Re-synthesized Circuit 31

32 Table 2: Statistical results of Monte-Carlo experiments (cont.) Circuit 0.8*d r 0.9*d r 1.0*d r 1.1*d r 1.2*d r O R O R O R O R O R f51m frg frg i i i i i i k lal pair rot t term ttt vda x x x x z4ml Avg O: Original Circuit R: Re-synthesized Circuit 32

33 Original Re-synthesized Number of Samples Timing Requirement Figure 15(a): The distribution curves of Monte-Carlo samples (9symml) Original Re-synthesized Number of Samples Timing Requirement Figure 15(b): The distribution curves of Monte-Carlo samples (comp) 33

34 Original Re-synthesized Number of Samples Timing Requirement Figure 15(c): The distribution curves of Monte-Carlo samples (f51m) Original Re-synthesized Number of Samples Timing Requirement Figure 15(d): The distribution curves of Monte-Carlo samples (t481) 34

35 Chapter 6 Conclusions We have proposed a framework to re-synthesize a given domino circuit for d t delay tolerance. Our method begins with a duplex system; we then adopt wire removal and signal sharing to reduce the area overhead of the delay tolerance structure. Two novel theorems for further area reduction are presented. Experimental results demonstrate the advantages of delay variation tolerance for a re-synthesized domino circuit. 35

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