A Hardware Approach to Self-Testing of Large Programmable Logic Arrays

Transcription

1 EEE TRANSACTONS ON COMPUTERS, VOL. C-30, NO. 11, NOVEMBER 1981 A Hardware Approach to Self-Testing of Large Programmable Logic Arrays 829 WLFRED DAEHN AND JOACHM MUCHA, MEMBER, EEE Abstract-A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. t allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A 8 X 16 X 8 PLA is completely tested within 52 cycles; a 16 X 48 X 8 PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLS circuits. ndex Terms-Built-in test; nonlinear feedback shift registers, pattern generation, programmable logic array (PLA).. NTRODUCTON T HE RAPD evolution of semiconductor technology towards higher device densities has made programmable logic arrays (PLA's) an increasingly important tool for automatically designing combinational circuits. While the problem of testing PLA's by externally generated test patterns may be considered to be solved [1], the built-in test of such devices gives rise to difficulties. The easiest way of generating test patterns for built-in testing is the use of a pseudorandom pattern generator [2]. Unfortunately, in contrast to most combinational circuits PLA's are not efficiently testable by pseudorandom patterns, as pointed out in [3]. t can be shown that even weighted random patterns will not solve the problem. n this paper a built-in test method for PLA's is proposed which is based on partitioning the circuit in such a way that only a small set of deterministic test patterns is required. n addition, those patterns are most easily generated by nonlinear feedback shift registers. This approach leads to a general method for designing deterministic test pattern generators. n Section the insufficiencies of random and weighted random patterns are discussed. The circuit partitioning and its effect on test patterns and fault coverage are described in Section. n Section V the general method for designing deterministic test pattern generators by means of nonlinear shift registers is presented and applied to the PLA problem. A comparison with other techniques is given in Section V, followed by a discussion of the overhead in Section V. Manuscript received December 11, 1980; revised June 1, The authors are with the Lehrstuhl fur Theoretische Elektrotechnik, University of Hannover, Hannover, West Germany.. NSUFFCENCES OF RANDOM PATTERNS The easiest way of generating test patterns on a chip is the use of pseudorandom sequences. They can be generated by linear feedback shift registers [4]. Unfortunately, there arise severe difficulties when applying such patterns to PLA's. They are mainly caused by the high fan-in of the gates in the search array. To detect a fault in a n-input gate of the search array, at least n input lines have to be adjusted. Using pseudorandom patterns the probability of generating an appropriate test vector becomes quite low, as shown in [3]. Generally, the problem cannot be solved even by assigning weights to the inputs.1 A NOR-gate that is mainly connected to the noninverting input lines demands a low weight. On the other hand, if a gate is mainly connected to inverting inputs, a high weight is required. Thus, for a circuit containing both types of gates, as in the case with most PLA's, no appropriate weight can be found that reduces the pseudorandom pattern count. This obvious fact was also verified by extensive logical simulations.. CRCUT PARTTONNG, TEST PATTERNS, AND FAULT COVERAGE The difficulties mentioned above can be overcome by partitioning the circuit and testing separately each of the two planes that are mostly realized as NOR-planes (Fig. 1). Three kinds of faults have to be considered, as follows: 1) stuck-at faults, 2) bridging faults, 3) programming faults. The detection of a stuck-at- input fault or a stuck-at-0 output fault of a NOR-gate requires a pattern completely consisting of zeros. For a stuck-at-0 input fault, the corresponding input line has to be one and all the other inputs must be zero. The stuck-at- output fault is dominated by the stuck-at-0 input faults. So all faults inside a k-input NOR-gate can be detected by the following set of k + 1 test patterns: o1. The probability of a logical one appearing on an input is called its. weight /81/ $ EEE

2 830 EEE TRANSACTONS ON COMPUTERS, VOL. C-30, NO. 11, NOVEMBER Search Read- Array Array brui dlgi ng fa ul t ) Fig. 2. Model for bridging faults. rll Bit Partitioning nverters Fig. 1. PLA partitioning for testability. This test set is also valid for any NOR-gate connected to an arbitrary subset of the k inputs. The test set for the whole NOR-plane is obtained by a simple extension to the necessary number of input lines. A knowledge of the personalization is not required. As known in NMOS-circuits, bridging faults may be described by logically ANDing the affected lines (Fig. 2). Shorts between input lines feeding the same gate are detectable by the following two vectors as well as shorts between lines feeding different gates: Both vectors are contained in the above test set for stuck-at faults. Bridging faults between otutput lines of a NOR-plane are detectable if the affected gates differ at least in one input. Without loss of generality the functions are assumed to be Y = X1 + X2 + X3 Y2 = X + X2 + X4. A short between y 1 and Y2 is observable by applying one of the following vectors to the circuit: O **- - These vectors are contained in the above test set too. Programming faults are faults concerning the proper connection of the input lines to the gates. These faults are detected by the above test set quite as well because whenever an input line that is connected to a NOR-gate becomes one, its output will be zero. So every NOR-gate can be identified by observing its output sequence. These-considerations result in a general design proposal for large PLA's, as shown in Fig. 3. A slightly modified "built-in logic block observer" (BLBO) is used for both pattern generation and test answer evaluation [2]. The test is performed in two consecutive steps. Step -Test ofthe First NOR-Plane: The test patterns are generated by BLBO 1 and the test answers are evaluated by BLBO 3. Then the signature is shifted out for inspection. Step 2-Test of the Second NOR-Plane: Now BLBO 2 generates the test patterns and BLBO 3 evaluates the test answers. Then again the signature is shifted out. The output inverters and the bit partitioning network could be tested by feeding back the primary outputs to the primary inputs and using BLBO 3 for pattern generation and BLBO Fig. 3. Architecture of a self-testing PLA. 1 for test answer evaluation. f the PLA is part of a larger system, pattern generation for the bit partitioning network can be done by another module testing the interconnection lines too. The test, set for NOR-planes yields also 100 percent fault coverage of a one bit partitioning network. One possible complete test set for a two-bit partitioning network is the following: V. 0...* TEST PATTERN GENERATON AND TEST ANSWER EVALUATON The most economic solution for deterministic pattern generation at the maximum internal speed of the PLA under test seems to be the use of a nonlinear feedback shift register. Designing a nonlinear feedback shift register which generates a set of vectors T that contains any given set To as a subset with a small amount of overhead is performed in two steps. Step 1: The vectors of To have to be ordered so that they can be generated by a shift register. The procedure is initialized by selecting an arbitrary start vector from To. Then a search for a successor is performed among the remaining vectors. f no direct successor can be found, a vector obtainable in two or more shift cycles must be chosen. t has to be linked to the one selected before by some additional intermediate vectors not contained in To. These link vectors are uniquely determined

3 DAEHN AND MUCHA: SELF-TESTNG OF LARGE PLA'S 831 Fig Test pattern generator for NOR-planes. Fig ' Test pattern generator for two-bit partitioning networks. TABLE REQURED PATTERNS FOR AN 8 X 16 X 8 PLA AND-plane 17 patterns OR-plane 17 patterns 34 patterns overall clock cycles for test and control 52 cycles pseudo random test 230 patterns exhaustive test 256 patterns by the two other vectors mentioned before. Repeating the last steps until exhaustion of the set To yields a vector sequence matching the above specifications. Step 2: A Boolean function must be specified delivering the first bit of the next state vector dependent on the last one. Difficulties arise if some vectors appear twice or more with different successors as a result of Step 1. teratively extending every vector of the generated sequence by the first bit of the following vector will remove this problem. As the last vector had to be extended by a X (DON'T CARE), it might be omitted as well. Applying this procedure to the universal test set for NORplanes results in a vector sequence that can be generated by a shift register with a feedback function being a simple NOR of all components of the state vector (Fig. 4). t should be noted that the patterns produced by this generator also form a valid test set for the feedback function. So by observing the output of the NOR-gate, the generator is tested as well. An appropriate test pattern generator for the two bit partitioning network is shown in Fig. 5. The evaluation of the test answers is done by a multiple input signature register [2]. V. A COMPARSON WTH OTHER TECHNQUES As the amount of test patterns to be generated by the above method is a linear function of the number of input lines and product terms, a considerable reduction of testing time is to be expected. Computer simulations of an 8 X 16 X 8 PLA have verified this prediction. Table shows the test effort of this method and gives a comparison with pseudorandom patterns and exhaustive test. The most important attribute of this method seems to be the fact that a short test length is achieved by patterns that do not depend on the personalization of the PLA. So there is no more need for sophisticated test pattern computations and the good machine simulation can be performed within a minimum of time.2 2 The good machine simulation for a 16 X 48 X 8 PLA can be done in less than 1 s of CPU time on a CDC Cyber 76, whereas a complete fault simulation is estimated to take several hours.

4 832 EEE TRANSACTONS ON COMPUTERS, VOL. C-30, NO. 11, NOVEMBER st NOR-Plane Ou tput 2nd NOR-Plane 2nd NOR- P 1 a ne Output - 1st N OR- P 1 an e.--l T T T T r T i k T i T - i - 1. '[ - n p u t 2nd NOR-P1 ane Output 1st N OR - P a n e Output 1st NOR-Plane 2nd NOR-Plane Fig. 6. Possible /O ports of the naked PLA. Fig. 7. Placement of the test aids. Fig. 9. Placement of the test aids. Fig. 8. Architecture of a self-testing PLA with /O registers. V. OVERHEAD The testability is increased with only a small amount of overhead. As the input and output lines of the two NOR-arrays pass completely through their planes, they are controllable from respective opposite edges of the naked PLA (Fig. 6). A proper arrangement of the test aids using the just mentioned feature is presented in Fig. 7. Obviously, the lengths of BLBO 1-3 are proportional to the number of inputs, product terms, and outputs, respectively. The depth is constant for a given technology. So the chip area TA required by the test aids is only proportional to the above lengths. The area F of the naked PLA is proportional to the number of crosspoints. Multiplying the number of inputs, product terms, and outputs by a factor of n results in n2 times larger local requirements F of the naked PLA, while the overhead TA increases only by a factor of n. This is denoted by the following relation: TA l- F. n many applications PLA's with input/output registers are used. Using these registers for implementation of BLBO 1 and BLBO 3 as depicted in Figs. 8 and 9 will reduce the overhead furthermore. V. CONCLUDNG REMARKS Programmable logic arrays are testable within a number of cycles that is proportional to the number of inputs and product terms. All crosspoint defects and bridging faults are detected as well even in the presence of redundancy with patterns that do not depend on the personalization of the PLA. The test can be implemented as built-in test using nonlinear

5 EEE TRANSACTONS ON COMPUTERS, VOL. C-30, NO. i, NOVEMBER 1981 feedback shift registers and multiple input signature analysis for test pattern generation and test answer evaluation, respectively. As the test always yields 100 percent fault coverage of the naked PLA, no extensive and costly fault simulation or test pattern computation is required. 833 Wilfried Daehn was born in Celle, West Germany, in He received the Dipl.-ng. degree in electrical engineering from the University of Hannover, Hannover, West Germany, in Currently, he is a Research Assistant at the Lehrstuhl ftir Theoretische Elektrotechnik, University of Hannover. REFERENCES [1] J. E. Smith, "Detection of faults in programmable logic arrays," EEE Trans. Comput., vol. C-28, pp , Nov [2] B. Koenemann, J. Mucha, and G. Zwiehoff, "Built-in logic block observation techniques," in Dig Test Conf., Cherry Hill, NJ, Oct. 1979; pp [3] T. W. Williams and E. B. Eichelberger, "Random patterns within a structured sequential logic design," in Proc Semiconductor Test Symp., Cherry Hill, NJ, 1977, pp [4] S. W. Golomb, Shift Register Sequences. San Francisco, CA: Holden-Day, [5] H. J. Nadig, "Testing a microprocessor product using a signature analysis," in Proc Semiconductor Test Conf., Cherry Hill, NJ, Oct./ Nov. 1978,pp Joachim Mucha (M'69) received the Dipl.-ng. and Ph.D. degrees in electrical engineering from the Technical University of Aachen, Aachen, West Germany, in 1960 and 1968, respectively. From 1960 to 1962 he was with the AEG-Telefunken Company, Konstanz, West Germany, working on logical design of digital systems. He later became a Research Assistant at the University of Aachen, and in 1977 he became a Professor. Since 1979 he has been a Professor at the University of Hannover, Hannover, West Germany. His research interests are in the field of CAD with emphasis on design for testa- bility. A Testable Design of terative Logic Arrays R. PARTHASARATHY AND SUDHAKAR M. REDDY, Abstract-Testable design of unilateral iterative logic arrays (LA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-step C-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. t is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number (<4) of columns and a row so that a faulty cell can be located by a test of length proportional to 1 g2 p, where p is the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell. A set of simpler sufficient conditions are given for the testability of two-dimensional arrays. t is shown that these conditions ensure that all possible input states can be applied to every cell in an array of MEMBER, EEE. NTRODUCTON DUE to advances in semiconductor fabrication technology, it has become possible to fabricate large-scale integrated semiconductor arrays containing hundreds or thousands of gates. An attractive realization of these arrays is in a cellular form because of its structural simplicity, ease of fabrication, ease of circuit and logic design, and simplified testing and diagnosis [1]. Practical examples of such arrays are adders, arithmetic logic units, etc. [6]. More recently, bit-sliced microprocessor systems have been shown to fall into this category [7]. By testing, we mean applying test inputs to the controllable input terminals of the array and observing the outputs at the arbitrary dimensions. accessible output terminals. These terminals are usually associated with the boundaries of the array, but some input and ndex Terms-C-testability, fault detection, fault diagnosis, flow table augmentation, iterative logic arrays, one-step C-testability, output terminals of each cell in the array may be additionally accessible. one-step testability. The problem of fault detection and location in iterative logic Manuscript received December 12,1980; revised June 5, This work arrays (LA) of combinational cells was first studied by Kautz was supported in part by the Air Force Office of Scientific Research under [1]. He assumed that all possible cell inputs must be applied Grant AFOSR The authors are with the Department of Electrical and Computer Engi- to each cell in order to test it completely and that a fault in a neering, University of owa, owa City, A cell may affect the cell outputs in any arbitrary manner. These /81/ $ EEE