(a) For e/0, two vectors, abc = {011, 111} can detect it. Thus. (b) For e/1, one vector, abc = 010 can detect it. Thus

Transcription

1 Chapter 4 Exercise Solutions 4.1 (Ranom Test Generation We woul enumerate the pseuo-exhaustive vectors or each o the three primary output. Let T1 be the exhaustive test set o 8 vectors or inputs a, b, c or output x, the other 4 primary inputs can take on ranom values. Likewise, T2 is the test set o 16 vectors or inputs c,, e, or primary output y, where the remaining 3 primary inputs take ranom values. Finally, T3 is the test set o 8 vectors or the last primary output z. The union o T1, T2, an T3 orms the pseuo-exhaustive test set. This is not the minimal pseuo-exhaustive test set, since there are some repeate vectors in T1, T2, an T (Ranom Test Generation Recall that the etection probability is T = n, where T is the set 2 o vectors that can etect ault, an n is the number o inputs in the circuit. In this circuit, we have 3 inputs, so there is a total o 8 possible vectors. (a For e/0, two vectors, abc = {011, 111} can etect it. Thus = 0.25 (b For e/1, one vector, abc = 010 can etect it. Thus = (c For c/0, two vectors, abc = {011, 101} can etect it, Thus = (Boolean Dierence ence (a The set o vectors that can etect e/0 is VLSI Test Principles an Architectures Ch. 4 Test Generation P. 1/8

2 z ( e = 1 ( z ( e = 0 z( e = 1 ( g ( g + b g g m b + g ( g + b g b e ( ac b ( a + c b = bc + abc = bc Thus, the set o vectors is {011, 111}. (b The set o vectors that can etect e/1 is z ( e = 0 ( z ( e = 0 z( e = 1 ( g ( g + b g g m b + g ( g + b g b ( ac b e ( a + c = bce + abe b = abe = abc Thus, the set o vectors is {010}. (c The set o vectors that can etect c/0 is z ( c = 1 ( z ( c = 0 z( c = 1 c = c a b = c ( ( a b + a b = abc + abc Thus, the set o vectors is {011, 101}. 4.4 (Boolean Dierence (a The set o vectors that can etect a/1 is VLSI Test Principles an Architectures Ch. 4 Test Generation P. 2/8

3 i ( a = 0 = a ( i ( a = 0 i( a = 1 = a = ab a ( 0 b Thus, the set o vectors is {01}. (b The set o vectors that can etect /1 is i ( = 0 = ( i ( = 0 i( = 1 = = ab ( 0 ab But it is impossible to set a=1 an =0 simultaneously. Thus, the set o vectors is. (c The set o vectors that can etect g/1 is i ( g = 0 = g ( i ( g = 0 i( g = 1 = g = g ab = ab ab = 0 g ( 0 ab Thus, the set o vectors is. 4.6 (Boolean Dierence Since α an β are inistinguishable, any test t that etects one must also etect the other. In other wors, ( t ( t α β or any etection vector t. On the other han, i a vector v oes not etect α, it must also not etect β. In this case, ( v ( v α β, where is the ault-ree circuit. Thus, or all vectors t, we have ( t ( t Thereore, = (D Algorithm α β α β. VLSI Test Principles an Architectures Ch. 4 Test Generation P. 3/8

4 XNOR 0 1 D D X D D X D D X D D D 1 0 X D D D 0 1 X x X X X X X 4.8 (D Algorithm Initially, we place a D on b. The D-rontier at this time inclues {, e}. Next, we pick a D-rontier to propagate the ault eect across. Suppose we pick. Then, the ecision a=0 is mae. At this time, the D-rontier becomes {x, e}. We pick the D-rontier that is closest to a PO. Thus, we pick x. The next ecision is e1=0. This ecision implies y=1 an z=d. In other wors, the ault-eect has been propagate all the way to the PO. The J-rontier consists o {e1=0, b= D }. To justiy e1=0, c=0 is suicient. Justiying b= D is likewise straightorwar, simply by setting b=0. Thus the vector abc=000 etects the target ault b/1. A similar ecision process is mae or the target ault e/0. However, in this case, one woul conclue that the ault is untestable. 4.9 (D Algorithm The vali value combinations or gate g inclue: {Dxx, Dx1, D1x, D xx, D x1, D 1x, xdx, xd1, 1Dx, x D x, x D 1, 1 D x, xxd, x1d, 1xD, xx D, x1 D, 1x D } 4.10 (PODEM VLSI Test Principles an Architectures Ch. 4 Test Generation P. 4/8

5 First, we nee to excite the ault. Since the ault is on a PI, the irst objective is b= D. Backtracing rom the objective gives us b=0 as the irst ecision. Logic simulating the current set o ecisions mae oes not change values o other gates. The D-rontier at this time inclues {, e}. Next, we pick a D-rontier to attempt to propagate the ault eect across. Suppose we pick. Then, backtracing rom the sie input gives us a=0 as the next ecision. Logic simulating a=0 together with previous ecisions gives us a new D-rontier {x, e}. We pick the D-rontier that is closest to a PO. Thus, we pick x. We again backtrace rom the sie input e1=0 through an X-path. This leas us to c=0. Logic simulating c=0 with earlier ecisions gives us e=0, e1=0, e2=0, y=1, x=d, z=d. At this time the ault has been etecte. Thus the vector abc=000 etects the target ault b/1. A similar ecision process is mae or the target ault e/0. However, in this case, one woul conclue that the ault is untestable (Static Implications Since we know that =1 implies x=1 an z=0, we can make {=1, x=1, z=0} as multiple objectives. Thus, any ecisions selecte shoul not violate any o the objectives at any time. Likewise, we can use the implications o z=0 to a to the multiple objectives (Static Implications (a The implications or g=0 inclue {a=0, b=1, c=1, =0, e=0, =1, g=0, h=0} (b The implications or $=0$ inclue {a=1, b=1, c=0, =1, e=1, =0, g=1, h=0} 4.15 (Dynamic Implications Since justiying e=1 via a=0 is not possible, it must be justiie via b=0. Thus, e=1 b=0 is a ynamically learne implication (Untestable Fault Ientiication (a The static logic implications o b=0 inclue {b=0, c=0, =0, e=1, g=0, z=0} (b The static logic implications o b=1 inclue {b=1, c=1, =1} (c The set o aults that are untestable when b=0 is {b/0, c/0, /0, e/1, g/0, z/0, a/0, a/1, /0, /1, /1, g/1, e/0, /0, VLSI Test Principles an Architectures Ch. 4 Test Generation P. 5/8

6 /1, a/0,a/1, c/1} ( The set o aults that are untestable when b=1 is {b/1, c/1, /1} (e The set o untestable aults base on the stem analysis o b is the intersection o the (c an (, which is {c/1, /1} 4.18 (PODEM (a c/0: The irst objective is c=1, which backtraces to b=1. Next, to propagate the ault, the objective is a=1. At this time the D-rontier is {g}. The next objective is =0. With simulation, the ault is etecte. So the vector is ab=110. (b c/1: The irst objective is c=0, which backtraces to b=0. Next, to propagate the ault, a=1. At this time the D-rontier is g. The next objective is =0. With ault simulation we obtain that the ault is blocke. So we backtrack to =1. This also blocks the ault. So we revert =X an backtrack to a=0. This also blocks the ault. Finally we backtrack to b=1. This cannot excite the ault. We are now at the root o the ecision tree. No more backtracks are possible. Thus the ault is untestable. (c /0: The irst objective is =1, which backtraces to b=1. With simulation we obtain the D-rontier to be {z}. The next objective is g=1. Backtracing through an X-path leas us to =0. Simulating at this time, the D-rontier is still the same. The previous objective g=1 is not yet justiie. So we backtrace rom g=1 again via an X-path. This time it takes us to a=1. With simulation the ault is etecte. So the vector is ab=110. ( /1: The irst objective is =0, which backtraces to b=0. At this time the D-rontier is empty since g=0. So we backtrack to b=1. But this cannot excite the ault. Thus we backtrack again. No backtracks are possible, thus the ault is untestable (Untestable Fault Ientiication I a ault is combinationally untestable, then there exists no input (PPI, PI that can excite it an propagate it to any o PPO or PO. This means that it is impossible in the sequential circuit that can take the circuit to a state PPI with any PI that can excite an propagate its ault eects to either primary outputs or to the next-state lip-lops. Thus, is also sequentially untestable (FAN VLSI Test Principles an Architectures Ch. 4 Test Generation P. 6/8

7 Since both x an y are healines, it suices to backtrace to only these points instea o primary inputs. Furthermore, since we know that y=1 x=0, when we backtrace to x, i the require value on x is 1, then we can immeiately backtrack in the ecision process (Sequential ATPG (a In time-rame 0, we propagate the D to output z, thus we nee the lip-lop value to be 1. In time-rame -1, the lip-lop value=1 can be obtaine by either the lip-lop value in time-rame -2 to be 1, or a=1. However, since a=0 (the target ault, we must backtrace to the lip-lop in time-rame -2. This will repeat ineinitely, resulting the ault to be untestable using the 5-value logic. (b In time-rame 0, we propagate the D to output z, thus we nee the lip-lop value to be 1/X in the 9-value logic. In time-rame -1, the lip-lop value=1/x can be obtaine via either the lip-lop in time-rame -2 or via a. In act, a=1/0 (the target ault suices our nee o a=1/x. Thus, the vector sequence (a=1, a=x is the test sequence (Sequential ATPG Yes, two aults a/0 an a/1 can be etecte by the same test sequence. Consier the test sequence v 0, v 1,..., v k, where v k 1 excites a/0 an propagates it to a state element, an v k both propagates the ault-eect rom the lip-lop to a PO as well as excites an propagates the other ault a/1 to a PO (Sequential ATPG The reachable states are {00, 01, 11}. The state iagram can be obtaine by constructing the truth table or the present-state an the PIs (Avance Simulation-Base ATPG The sequence that is able to propagate a ault-eect rom a lip-lop FF i to a primary output or ault 1 inicates that this propagation sequence oes not incientally mask the ault 1 along the way. This propagation sequence will be ineective or another ault j i the VLSI Test Principles an Architectures Ch. 4 Test Generation P. 7/8

8 ault-eect rom FF i is maske with the ault site or ault j (Path-Delay ATPG (a There are 14 paths in the circuit: agj, agj, bgj, bgj, begj, begj, cegj, cegj, chj, chj, hj, hj, ij, ij. (c Both agj an agj are unsensitizable (Path-Delay ATPG Any path that requires a=1 an b=0 as a necessary conition woul be unsensitizable (Path-Del Delay ATPG I the untestable path-elay ault is longer than the testable critical path, then inciental etection coul lea to yiel loss (Briging Faults The largest current is rawn rom V to Groun i the resistance between them is minimal. So any test that can turn on parallel transisters at a same time in both the AND an OR gates such that a conuction occurs rom V to Groun woul inuce the largest current. VLSI Test Principles an Architectures Ch. 4 Test Generation P. 8/8