Outline Automatic Test Pattern Generation
|
|
- Bertram Willis
- 5 years ago
- Views:
Transcription
1 K.T. Tim heng, 5_comb_tg, v. Outline utomatic Test Pattern Generation Test generation systems Test generation for combinational ckts -lgorithm POM oolean Satisfiability approach Test compaction Test generation for sequential ckts Time-frame expansion & xtended -lgorithm Nine-valued test generation Potential detection Issues of sequential TPG Test sequence compaction K.T. Tim heng, 5_comb_tg, v. 2
2 The TPG Problem Problem definition: Given a logical fault model, and a circuit, determine a small set of test vectors that detect all faults in the circuit. Problem complexity: Under the stuck-at fault model, the problem is NP-complete even for combinational circuits However, commercial test generators that efficiently generate tests for >M-gate ckts are in use today. K.T. Tim heng, 5_comb_tg, v. 3 asics: Path Sensitization Method tomic operations:. ctivation, fault excitation: Specify inputs so as to generate the appropriate value at fault site for fault excitation (I.e. set S to for S-stuck-at- fault) 2. rror propagation: specify additional signal values to propagate the fault effect from the fault site to the outputs/observation points 3. Line justification: Specify input values so as to produce the signal values specified in () or (2) 4. Value implication: unique determination of values at other signals due to value assignments made in (), (2), or (3) K.T. Tim heng, 5_comb_tg, v. 4 2
3 Simple xample f G a s.a. G6 f2 () Fault activation : = = = (2) Have a choice of error propagating: through G 5 or G 6 (a) Propagating through G 5 requires G 2 = == contradiction (b) Propagating through G 6 requires G 4 = =, = Test =(x) K.T. Tim heng, 5_comb_tg, v. 5 Line Justification H F G4 s-a- = G = = to propagate through G. To propagate G 4, need G 2 = G 3 = ttempt to line justify G 2 = G 3 = G 3 = possible if = F = or = H = If = F = inconsistency since = so G 2 =. Therefore, G 3 = = H = G 2 = need = or F = Tests are H, FH K.T. Tim heng, 5_comb_tg, v. 6 3
4 ompleteness of TPG lgorithms test generation algorithm is deemed complete iff it will find a test for a fault if exists or prove that there exists no test, given sufficient time. omplete algorithms can identify untestable faults Major complete algorithms for comb. ckts -algorithm (Roth, 966) POM (Goel, 98) FN (Fujiwara, 983) Socrates (Schulz, 988) oolean-st-based TPG (Larrabee, 992) K.T. Tim heng, 5_comb_tg, v. 7 Single Path Sensitization Is NOT omplete x d s.a. G 6 G d G4 f d s-a- : = = Propagate along G 3, G 6 requires =, G 2 = G 4 = G 5 =. In order for G 4 = either = or G = inconsistency =, = G 5 = inconsistency Propagate along G 4, G 6 = & G 2 = G 3 = G 5 = G 2 = =, = G 3 = inconsistency No test K.T. Tim heng, 5_comb_tg, v. 8 4
5 ut oolean ifference Method Finds Test =()!! G d s-a- / / G4 / / G6 / K.T. Tim heng, 5_comb_tg, v. 9 Multiple Path Sensitization G d s-a- / / G4 / / G6 / Two paths G 3, G 2 and G 4, G 6 are sensitized, i.e. error is propagated along both paths. K.T. Tim heng, 5_comb_tg, v. 5
6 The -lgebra Need to be able to deal with multiple errors at the inputs to a gate. represents a signal which has value in normal (fault-free, good) ckt, and value in faulty ckt. (I.e. /); Similarly, / ehaves like a oolean variable. K.T. Tim heng, 5_comb_tg, v. Primitive -cubes Specifies the minimal input conditions which must be applies to a logic element in order to produce an error signal at the output of Propagation -cubes The propagation -cubes of a logic element specify minimal input conditions which are required to propagate an error signal on an input (or inputs) to the output of that element. K.T. Tim heng, 5_comb_tg, v. 2 6
7 n xample 2 H J 8 9 G s.a. G4 5 7 G6 2 3 G s-a- : F primitive -cube primitive cubes of primitive cubes of primitive cubes of G4 primitive cubes of primitive cubes of G6 K.T. Tim heng, 5_comb_tg, v. 3 The -lgorithm ) Select a primitive -cube of the fault 2) Implication and checking for inconsistency. If inconsistency occurs, go to (). 3) -drive: selects an element in -frontier & attempts to propagate or in its inputs to its output. -frontier consists of set of all elements whose output values are unspecified but inputs have some signals with or. -drive is done by intersecting the test cube with a propagation -cube of the selected element. acktrack, i.e. select another propagation -cube, if intersection is null. 4) Implication of -drive: perform implication for the new test cube. 5) Repeat 3) & 4) until faulty signal propagated to an output. 6) Line justification: onsistency check on input conditions required. K.T. Tim heng, 5_comb_tg, v. 4 7
8 -lgorithm xample 2 H J 8 9 G s.a. G4 5 7 G F K.T. Tim heng, 5_comb_tg, v H J 8 9 G s.a. G F initial test cube ti propagation -cube of test cube after -drive through = tc' perform implication G heck implication: -cube of G does not imply any other signal. -frontier : G 3 Get propagation -cube for G 3 K.T. Tim heng, 5_comb_tg, v. 6 8
9 Now -frontier is G 5 & G 6 Select G 5 and a propagation -cube of G perform implication propagation -cube of Test cube after -drive Line justification or 8 G4 H J 9 2 G s.a. G6 3 F 3 6 K.T. 4Tim heng, 5_comb_tg, v. 7 Flowchart for -algorithm start Initialize test cube (tc) Select a primitive -cube of that as inconsistent acktrack to the last point a choice exists none exists -intersect with previous test cube tc and perform implication consistent Is there a or on any PO? no Select a gate from -frontier and a propagation -cube of the selected gate as yes Line Justification impossible done Test has been generated K.T. Tim heng, 5_comb_tg, v. 8 9
10 Line Justification egin Is there any line in tc which are not justified yes Select an unjustified line and a primitive cube to justify the line Intersect with previous test cube tc inconsistent consistent acktrack to the last Line point a choice exists justification impossible none exists no Test has been generated K.T. Tim heng, 5_comb_tg, v. 9 -lgorithm xample G s-a- 4 7 G4 G6 G7 8 9 G primitive -cube () implication (2) Select -frontier (3) implication (4) implication (5) 2 Select -frontier G8 (6) Implication Line justification (7) Implication Line justification (8) inconsistent & backtrack to (6) Select -frontier G6 (9) K.T. Tim heng, 5_comb_tg, v. 2 implication (8) implication () Test is found :
11 Potential Problems with -lgorithm Since the assignment of values is allowed to internal lines, more than one choice is available at such internal line/gate and backtracking could occur at each gate ould result in inefficiency for large ckts and some special classes of ckts. xample: n T (error-correction-&-translation) ckt H s.a. J F G K N P R Q L M K.T. Tim heng, 5_comb_tg, v. 2 The POM lgorithm (Goel 98) Only allows assignment of values to primary inputs The values assigned to primary inputs are then propagated toward internal lines by the implication. xample: First, a binary value is assigned to an unassigned PI to provide a fault effect at fault site: = etermine the implications of assigned PIs (only forward implication): = cause no implication Next, assign = = = imply H = F G H s.a. J N K L M P Q R K.T. Tim heng, 5_comb_tg, v. 22
12 POM ecision Tree for the xample Start = = H s.a. P = = J = = = F G L K N Q R F = F = M Test has been Successfully generated G = G = K.T. Tim heng, 5_comb_tg, v. 23 POM ssentially a process of finding a PI & a binary value for initial assignment. ontinue assigning PI values, checking to see if the error is being propagated to outputs (after each PI assignment, perform forward implication) If at any stage, either the fault cannot be excited or the error cannot be propagated further, backtrack to the most recent PI assignment and change it. K.T. Tim heng, 5_comb_tg, v. 24 2
13 Flowchart of POM Start ssign a binary value to an unassigned PI etermine implication of all PIs Test is found No test exists yes no Is there a or on any P? Is there an untried combination of values on assigned PIs? yes Set untried combination of values on assigned PIs no Test possible with additional no assigned PIs? maybe K.T. Tim heng, 5_comb_tg, v. 25 Steps in POM () etermine an initial objective. If the fault effect has not appeared at fault site, the initial objective is directed toward providing the fault effect on the faulty line. (2) Given the initial objective, a PI & a logic value are chosen that have a good likelihood of meeting the object. one using the backtrace procedure. K.T. Tim heng, 5_comb_tg, v. 26 3
14 Flowchart of acktrace begin Found PI initial assignment is the current objective value xit OR/NN & V= N/NOR & V= yes no (fed by gate G) urrent objective value V and type of gate driving Next obj line is the input of G which is at x and is the hardest to control Next obj value is the same as the current objective value objective line? no Is objective line fed by a PI? OR/NN & V= N/NOR & V= Next obj line is the input of G which is at x and is the easiest to control Is G a NN/NOR gate? yes Next obj value is the complement of the current objective value K.T. Tim heng, 5_comb_tg, v. 27 POM xample Initial objective: (, G 2 ) G4 acktrace to PI : 2 = G Initial objective: (, G 2 ) acktrace: 3 = Implication: G 2 = s-a- G6 G8 Z -frontier is { G 5, G 6 } G7 ttempt to propagate through G 5 Require = Implication: G =, G 4 =, G 5 = ttempt to propagate through G 8 K.T. Tim heng, 5_comb_tg, v. 28 4
15 POM xample ont d Initial objective: (, G 6 ) acktrace to set 4 = Implication: G 3 =, G 7 = & G 8 = failed in propagating error acktrack to most recent PI assignment reassign 4 = Implication: G 3 =, G 6 =, G 8 = Test is generated 2 = G G4 ecision tree 3 = 4 = test is found = = conflict & backtrack s-a- G6 G7 G8 Z K.T. Tim heng, 5_comb_tg, v. 29 ost of TPG () How long? (Time complexity) () How much RM? (Space complexity) () How many vectors generated? (Test application time) Theoretical result (Ibarra & Sahni, 975) : Generating a test for comb. ckt is NP-complete Worst-case time constant G (G = # of gates) mperical result (average-time behavior): Total TPG time constant G 2 Test length G K.T. Tim heng, 5_comb_tg, v. 3 5
16 ccelerating omb. TPG asic goals: Reduce number of backtracks Reduce processing between backtracking asic tools: Topological analysis Multiple backtrace Learning K.T. Tim heng, 5_comb_tg, v. 3 Socrates: Static Learning Preprocessing the ckt: () ssign a logic value to a certain signal of the ckt (2) Perform all implications from that assignment (3) Learn from the results of implications Using law of contraposition: ( ) (!!) Preprocessing: uring TPG: b d a f c e b a c d e ( a = f = ) ( f = a = ) b b d d a f a c e c e f Learned information f K.T. Tim heng, 5_comb_tg, v. 32 6
17 oolean Satisfiability pproach Given a fault, it consists of two steps: Step : onstruct a formula expressing the oolean ifference of a circuit with respect to the fault Step 2: pply a oolean Satisfiability (ST) solver to the resulting formula K.T. Tim heng, 5_comb_tg, v. 33 Step : xtracting the formula ach node of the ckt is tagged with the logic formula in 3-element conjunctive normal form, or 3NF The formula is true iff the values assigned are consistent with the truth for the logic element ( + ) * ( + ) * ( + + ) ( + ) * ( + ) * ( + + ) ( + ) * ( + ) K.T. Tim heng, 5_comb_tg, v. 34 7
18 Step : xtracting the formula ont d (a) onstruct the formula of the good circuit output (+) * (+) * (++) (+) * (+) * (++) (+) * (+) (b) onstruct formula of faulty circuit output for fault stuck-at- (no need to repeat the part identical to (a)) (+) * (+) * (++) ' ('+') * ('+) * ('+'+) ' (+) * (+) K.T. Tim heng, 5_comb_tg, v. 35 Step : xtracting the formula ont d (c) onstruct the formula of the oolean ifference: OR of (a) & (b) and the output of OR should be =(+ ) (+ )=V V 2 = From (a): (+) (+) (++) (+) (+) (++) (+) (+) From (b): ( + ) ( +) ( + +) From (c): (V +) (V + ) (V ++ ) (V 2 +) (V 2 + ) (V 2 ++ ) (+V ) (+V 2 ) (+V +V 2 ) (note: = =(+ ) (+ )=V V 2 ) K.T. Tim heng, 5_comb_tg, v. 36 8
19 Step 2: Satisfying the Formula - oolean Satisfiability Given a suitable representation for a oolean function f(): Find an assignment * such that f(*) = Or prove that such an assignment does not exist (i.e. f() = for all possible assignments) In the classical ST problem, f() is represented in product-ofsums (POS) or conjunctive normal form (NF) Many decision (yes/no) problems can be formulated either directly or indirectly in terms of oolean Satisfiability K.T. Tim heng, 5_comb_tg, v. 37 Public Released ST Solvers by US -ST: ombinational ircuit-based ST Solver F. Lu, Li-. Wang, K.-T heng, and R. Huang, ircuit ST solver with Signal orrelation guided learning, T, March 23. F. Lu, L.-. Wang, K.-T. heng, J. Moondanos and Z. Hanna, " Signal orrelation Guided TPG Solver and Its pplications for Solving ifficult Industrial ases,", Jun. 23. Satori & Seq-ST: Sequential ircuit-based ST Solver M. K. Iyer, G. Parthasarathy, and K.-T heng, STORI Fast Sequential ST solver for ircuits, I, Nov. 23. F. Lu, M. K. Iyer, G. Parthasarathy and K.-T. heng, "n fficient Sequential ST Solver With Improved Search Strategies," I Proc. esign, utomation & Test in urope (T), Mar. 25. K.T. Tim heng, 5_comb_tg, v. 38 9
20 Test ompaction for omb. Tests Fault simulate test patterns in reverse order of generation TPG patterns go first Randomly-generated patterns go last (because they may have less coverage) When coverage reaches %, drop remaining patterns (which are the useless random ones) ould significantly shortens test sequence reducing test application time K.T. Tim heng, 5_comb_tg, v. 39 2
EECS 579: Test Generation 4. Test Generation System
EECS 579: Test Generation 4 Other Combinational ATPG Algorithms SOCRATES Structure-Oriented Cost-Reducing Automatic TESt pattern generation [Schultz et al. 988] An ATPG system not just a test generation
More informationDepartment of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 203-204 Midterm Examination CLOSED OOK Kewal K. Saluja Date:
More informationDepartment of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2014-2015 Midterm Examination CLOSED BOOK Kewal K. Saluja
More informationCombinational Logic (mostly review!)
ombinational Logic (mostly review!)! Logic functions, truth tables, and switches " NOT, N, OR, NN, NOR, OR,... " Minimal set! xioms and theorems of oolean algebra " Proofs by re-writing " Proofs by perfect
More informationFault Equivalence, Dominance & Collapsing. Fault Equivalence
Fault Equivalence, Dominance & ollapsing Definition: If T a is the set of LL TVs which Detect Fault a, and T b is the set of LL TVs which Detect some other Fault b; the Two Faults a, and b are said to
More informationECE 1767 University of Toronto
Applications Why Two Fault Simulators Never Agree General Techniques Parallel Pattern Simulation Inactive Fault Removal Critical Path Tracing Fault Sampling Statistical Fault Analysis ECE 767 Fault grading
More informationFault Modeling. Fault Modeling Outline
Fault Modeling Outline Single Stuck-t Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of oolean Difference Copyright 1998 Elizabeth M. Rudnick
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 2 Circuit Optimization
Logic and omputer Design Fundamentals hapter 2 ombinational Logic ircuits Part 2 ircuit Optimization harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
More informationChapter 6 Testability Analysis
電機系 Chapter 6 Testability Analysis 可測度分析法 2 Outline Introduction SCOAP COP High-level Testability Testability Analysis Applications To give early warnings about the test problems Guide the selection of
More informationCombinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams
Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams Sherief Reda Ashraf Salem Computer & Systems Eng. Dept. Mentor Graphics Egypt Ain Shams University Cairo, Egypt
More informationOutline Fault Simulation
K.T. Tim Cheng, 4_fault_sim, v. Outline Fault Simulation Applications of fault simulation Fault coverage vs product quality Fault simulation scenarios Fault simulation algorithms Fault sampling K.T. Tim
More informationGeneration of High Quality Non-Robust Tests for Path Delay Faults
Generation of High Quality Non-Robust Tests for Path Delay Faults Kwang-Ting Cheng Hsi-Chuan Chen Department of ECE AT&T Bell Laboratories University of California Murray Hill, NJ 07974 Santa Barbara,
More information(a) For e/0, two vectors, abc = {011, 111} can detect it. Thus. (b) For e/1, one vector, abc = 010 can detect it. Thus
Chapter 4 Exercise Solutions 4.1 (Ranom Test Generation We woul enumerate the pseuo-exhaustive vectors or each o the three primary output. Let T1 be the exhaustive test set o 8 vectors or inputs a, b,
More informationChapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction
hapter 2 Introduction igital esign and omputer rchitecture, 2 nd Edition avid Money Harris and Sarah L. Harris logic circuit is composed of: Inputs Outputs Functional specification Timing specification
More informationENGR 303 Introduction to Logic Design Lecture 3. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College
Introduction to Logic Design Lecture 3 Dr. Chuck rown Engineering and Computer Information Science Folsom Lake College Outline for Todays Lecture Logic Circuits SOP / POS oolean Theorems DeMorgan s Theorem
More informationHW1 graded review form? HW2 released CSE 20 DISCRETE MATH. Fall
CSE 20 HW1 graded review form? HW2 released DISCRETE MATH Fall 2017 http://cseweb.ucsd.edu/classes/fa17/cse20-ab/ Today's learning goals Translate sentences from English to propositional logic using appropriate
More informationGeneral Diagnostic Engine: GDE
eneral iagnostic ngine: onsistency based diagnosis 1 Introduction 2 omputational approach: arlos lonso onzález elarmino Pulido Junquera SI. pto. Informática, Universidad de Valladolid onsistency ased iagnosis
More informationChapter 7. Synchronous Sequential Networks. Excitation for
Chapter 7 Excitation for Synchronous Sequential Networks J. C. Huang, 2004 igital Logic esign 1 Structure of a clocked synchronous sequential network Mealy model of a clocked synchronous sequential network
More informationLearning Objectives. Boolean Algebra. In this chapter you will learn about:
Ref. Page Slide /78 Learning Objectives In this chapter you will learn about: oolean algebra Fundamental concepts and basic laws of oolean algebra oolean function and minimization Logic gates Logic circuits
More informationNP-Complete problems
NP-Complete problems NP-complete problems (NPC): A subset of NP. If any NP-complete problem can be solved in polynomial time, then every problem in NP has a polynomial time solution. NP-complete languages
More informationTestability Measures controllability observability Controllability Observability
Testability Measures An attempt to quantify testability by Goldstein 79 and Grason 79 resulted in two testability measures, controllability and observability. Controllability is defined as the difficulty
More informationFOF (Functionally Observable Fault): A unified mode for testing and debugging - ATPG and application to debugging -
FOF Functionally Observable Fault: uniied mode or testing and debugging - TPG and application to debugging - Masahiro Fujita VLSI Design and Education enter VDE University o Tokyo Stuck-at ault and unctional
More informationChapter 2 Part 7 Combinational Logic Circuits
University of Wisconsin - Madison EE/omp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and u Hen Hu Spring 2002 hapter 2 Part 7 ombinational Logic ircuits Originals by: harles R. Kime and Tom Kamisnski
More informationFinal Exam: Graduate Course { VLSI Testing. 1. Please read all problems before starting your answers. Problems can be answered
inal xam: Graduate ourse { VLSI Testing uburn Univ., L 7250, Spring 2004 May 10, 2004 Instructions (please read before you proceed): 1. Please read all problems before starting your answers. Problems can
More informationProblem Set 4 Solutions
SE 26 igital omputers: Organization and Logical esign Jon Turner Problem Set 4 Solutions 1. Find a minimal logic expression for the NN/NOR circuit shown below. The circuit implements the expression ((()
More informationPossible logic functions of two variables
ombinational logic asic logic oolean algebra, proofs by re-writing, proofs by perfect induction logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set Logic realization
More informationCOMP219: Artificial Intelligence. Lecture 20: Propositional Reasoning
COMP219: Artificial Intelligence Lecture 20: Propositional Reasoning 1 Overview Last time Logic for KR in general; Propositional Logic; Natural Deduction Today Entailment, satisfiability and validity Normal
More informationELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3)
ELE 2200-002 igital Logic ircuits Fall 205 Logic Minimization (hapter 3) Vishwani. grawal James J. anaher Professor epartment of Electrical and omputer Engineering uburn University, uburn, L 36849 http://www.eng.auburn.edu/~vagrawal
More informationIntroduction to Arti Intelligence
Introduction to Arti Intelligence cial Lecture 4: Constraint satisfaction problems 1 / 48 Constraint satisfaction problems: Today Exploiting the representation of a state to accelerate search. Backtracking.
More informationRevised by Hankui Zhuo, March 21, Logical agents. Chapter 7. Chapter 7 1
Revised by Hankui Zhuo, March, 08 Logical agents Chapter 7 Chapter 7 Outline Wumpus world Logic in general models and entailment Propositional (oolean) logic Equivalence, validity, satisfiability Inference
More informationPropositional Logic: Equivalence
Propositional Logic: Equivalence Alice Gao Lecture 5 Based on work by J. Buss, L. Kari, A. Lubiw, B. Bonakdarpour, D. Maftuleac, C. Roberts, R. Trefler, and P. Van Beek 1/42 Outline Propositional Logic:
More informationELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3)
ELE 2200-002 Digital Logic ircuits Fall 204 Logic Minimization (hapter 3) Vishwani D. grawal James J. Danaher Professor Department of Electrical and omputer Engineering uburn University, uburn, L 36849
More informationCombinational Logic Design
PEN 35 - igital System esign ombinational Logic esign hapter 3 Logic and omputer esign Fundamentals, 4 rd Ed., Mano 2008 Pearson Prentice Hall esign oncepts and utomation top-down design proceeds from
More informationPropositional logic. Programming and Modal Logic
Propositional logic Programming and Modal Logic 2006-2007 4 Contents Syntax of propositional logic Semantics of propositional logic Semantic entailment Natural deduction proof system Soundness and completeness
More informationPropositional inference, propositional agents
ropositional inference, propositional agents Chapter 7.5 7.7 Chapter 7.5 7.7 1 Outline Inference rules and theorem proving forward chaining backward chaining resolution Efficient model checking algorithms
More informationLecture 3. Title goes here 1. level Networks. Boolean Algebra and Multi-level. level. level. level. level
Lecture 3 Dr Richard Reilly Dept. of Electronic & Electrical Engineering Room 53, Engineering uilding oolean lgebra and Multi- oolean algebra George oole, little formal education yet was a brilliant scholar.
More informationDigital- or Logic Circuits. Outline Logic Circuits. Logic Voltage Levels. Binary Representation
Outline Logic ircuits Introduction Logic Systems TTL MOS Logic Gates NOT, OR, N NOR, NN, XOR Implementation oolean lgebra ombinatorial ircuits Multipleer emultipleer rithmetic ircuits Simplifying Logic
More informationProcess Mining. Knut Hinkelmann. Prof. Dr. Knut Hinkelmann MSc Business Information Systems
Knut Hinkelmann Prof. r. Knut Hinkelmann MSc usiness Information Systems Learning Objective Topic: Learning Process knowledge from experience learning a process/decision model ase-ased Reasoning (R) reusing
More information12/31/2010. Overview. 05-Boolean Algebra Part 3 Text: Unit 3, 7. DeMorgan s Law. Example. Example. DeMorgan s Law
Overview 05-oolean lgebra Part 3 Text: Unit 3, 7 EEGR/ISS 201 Digital Operations and omputations Winter 2011 DeMorgan s Laws lgebraic Simplifications Exclusive-OR and Equivalence Functionally omplete NND-NOR
More informationPropositional Logic. Logic. Propositional Logic Syntax. Propositional Logic
Propositional Logic Reading: Chapter 7.1, 7.3 7.5 [ased on slides from Jerry Zhu, Louis Oliphant and ndrew Moore] Logic If the rules of the world are presented formally, then a decision maker can use logical
More informationCombinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.
Combinational logic Possible logic functions of two variables Logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,... Minimal set xioms and theorems of oolean algebra Proofs by re-writing
More informationLearning Objectives:
Learning Objectives: t the end of this topic you will be able to; draw a block diagram showing how -type flip-flops can be connected to form a synchronous counter to meet a given specification; explain
More informationLogical agents. Chapter 7. Chapter 7 1
Logical agents Chapter 7 Chapter 7 1 Outline Knowledge-based agents Logic in general models and entailment Propositional (oolean) logic Equivalence, validity, satisfiability Inference rules and theorem
More informationLecture #14: NP-Completeness (Chapter 34 Old Edition Chapter 36) Discussion here is from the old edition.
Lecture #14: 0.0.1 NP-Completeness (Chapter 34 Old Edition Chapter 36) Discussion here is from the old edition. 0.0.2 Preliminaries: Definition 1 n abstract problem Q is a binary relations on a set I of
More information3. PRINCIPLES OF COMBINATIONAL LOGIC
Principle of ombinational Logic -. PRINIPLES OF OMINTIONL LOGI Objectives. Understand the design & analysis procedure of combinational logic.. Understand the optimization of combinational logic.. efinitions
More informationNP-Completeness. f(n) \ n n sec sec sec. n sec 24.3 sec 5.2 mins. 2 n sec 17.9 mins 35.
NP-Completeness Reference: Computers and Intractability: A Guide to the Theory of NP-Completeness by Garey and Johnson, W.H. Freeman and Company, 1979. NP-Completeness 1 General Problems, Input Size and
More informationBoolean Algebra. Boolean Variables, Functions. NOT operation. AND operation. AND operation (cont). OR operation
oolean lgebra asic mathematics for the study of logic design is oolean lgebra asic laws of oolean lgebra will be implemented as switching devices called logic gates. Networks of Logic gates allow us to
More information12/31/2010. Overview. 10-Combinational Circuit Design Text: Unit 8. Limited Fan-in. Limited Fan-in. Limited Fan-in. Limited Fan-in
Overview 10-ombinational ircuit esign Text: Unit 8 Gates with elays and Timing Other Hazards GR/ISS 201 igital Operations and omputations Winter 2011 r. Louie 2 Practical logic gates are limited by the
More informationUNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY
UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational
More informationSimlification of Switching Functions
Simlification of Switching unctions ( ) = ( 789 5) Quine-Mc luskey Original nonminimized oolean function m i m i m n m i [] m m m m m 4 m 5 m 6 m 7 m 8 m 9 m m m m m 4 m 5 m m m 7 m 8 m 9 m m 5 The number
More informationCOSC3330 Computer Architecture Lecture 2. Combinational Logic
COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Today Combinational Logic oolean lgebra Mux, DeMux, Decoder
More informationSingle Stuck-At Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of Boolean Difference
Single Stuck-At Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of Boolean Difference Copyright 1998 Elizabeth M. Rudnick 1 Modeling the effects
More informationCSE 20 DISCRETE MATH. Winter
CSE 20 DISCRETE MATH Winter 2017 http://cseweb.ucsd.edu/classes/wi17/cse20-ab/ Today's learning goals Evaluate which proof technique(s) is appropriate for a given proposition Direct proof Proofs by contraposition
More informationTest Generation for Designs with Multiple Clocks
39.1 Test Generation for Designs with Multiple Clocks Xijiang Lin and Rob Thompson Mentor Graphics Corp. 8005 SW Boeckman Rd. Wilsonville, OR 97070 Abstract To improve the system performance, designs with
More informationDecision Procedures for Satisfiability and Validity in Propositional Logic
Decision Procedures for Satisfiability and Validity in Propositional Logic Meghdad Ghari Institute for Research in Fundamental Sciences (IPM) School of Mathematics-Isfahan Branch Logic Group http://math.ipm.ac.ir/isfahan/logic-group.htm
More informationProblem. Problem Given a dictionary and a word. Which page (if any) contains the given word? 3 / 26
Binary Search Introduction Problem Problem Given a dictionary and a word. Which page (if any) contains the given word? 3 / 26 Strategy 1: Random Search Randomly select a page until the page containing
More informationUMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs.
Overview Design for testability(dft) makes it possible to: Assure the detection of all faults in a circuit. Reduce the cost and time associated with test development. Reduce the execution time of performing
More informationUSING SAT FOR COMBINATIONAL IMPLEMENTATION CHECKING. Liudmila Cheremisinova, Dmitry Novikov
International Book Series "Information Science and Computing" 203 USING SAT FOR COMBINATIONAL IMPLEMENTATION CHECKING Liudmila Cheremisinova, Dmitry Novikov Abstract. The problem of checking whether a
More informationHeuristics for Efficient SAT Solving. As implemented in GRASP, Chaff and GSAT.
Heuristics for Efficient SAT Solving As implemented in GRASP, Chaff and GSAT. Formulation of famous problems as SAT: k-coloring (1/2) The K-Coloring problem: Given an undirected graph G(V,E) and a natural
More informationfor Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
More informationAn instance of SAT is defined as (X, S)
SAT: Propositional Satisfiability 22c:45 Artificial Intelligence Russell & Norvig, Ch. 7.6 Validity vs. Satisfiability Validity: A sentence is valid if it is true in every interpretation (every interpretation
More informationLecture 4: NP and computational intractability
Chapter 4 Lecture 4: NP and computational intractability Listen to: Find the longest path, Daniel Barret What do we do today: polynomial time reduction NP, co-np and NP complete problems some examples
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 OMP2611: omputer Organization ombinational Logic OMP2611 Fall 2015 asics of Logic ircuits 2 its are the basis for binary number representation in digital computers ombining bits into patterns following
More informationLecture 9: The Splitting Method for SAT
Lecture 9: The Splitting Method for SAT 1 Importance of SAT Cook-Levin Theorem: SAT is NP-complete. The reason why SAT is an important problem can be summarized as below: 1. A natural NP-Complete problem.
More informationA Sixteen-Valued Algorithm for Test Generation in Combinational Circuits
Syracuse University SURFACE Electrical Engineering and Computer Science Technical Reports College of Engineering and Computer Science 6-1991 A Sixteen-Valued Algorithm for Test Generation in Combinational
More informationVLSI System Testing. Testability Measures
ECE 538 VLSI System Testing Krish Chakrabarty Testability Measures ECE 538 Krish Chakrabarty 1 Testability Measures Origins Controllability and observability SCOAP measures Sources of correlation error
More informationIntroduction. 1854: Logical algebra was published by George Boole known today as Boolean Algebra
oolean lgebra Introduction 1854: Logical algebra was published by George oole known today as oolean lgebra It s a convenient way and systematic way of expressing and analyzing the operation of logic circuits.
More informationCS250: Discrete Math for Computer Science. L6: CNF and Natural Deduction for PropCalc
CS250: Discrete Math for Computer Science L6: CNF and Natural Deduction for PropCalc How to Simplify a PropCalc Formula: (p q) ((q r) p) How to Simplify a PropCalc Formula: 1. Get rid of s using def. of
More informationFoundations of Artificial Intelligence
Foundations of Artificial Intelligence 31. Propositional Logic: DPLL Algorithm Malte Helmert and Gabriele Röger University of Basel April 24, 2017 Propositional Logic: Overview Chapter overview: propositional
More informationLogic. Basic Logic Functions. Switches in series (AND) Truth Tables. Switches in Parallel (OR) Alternative view for OR
TOPIS: Logic Logic Expressions Logic Gates Simplifying Logic Expressions Sequential Logic (Logic with a Memory) George oole (85-864), English mathematician, oolean logic used in digital computers since
More informationInclusion of the Intuitionistic Fuzzy Sets Based on Some Weak Intuitionistic Fuzzy Implication
LGRIN DEMY OF SIENES YERNETIS ND INFORMTION TEHNOLOGIES Volume No 3 Sofia 0 Inclusion of the Intuitionistic Fuzzy Sets ased on Some Weak Intuitionistic Fuzzy Implication Piotr Dworniczak Department of
More informationLecture 1. Notes. Notes. Notes. Introduction. Introduction digital logic February Bern University of Applied Sciences
Output voltage Input voltage 3.3V Digital operation (Switch) Lecture digital logic February 26 ern University of pplied Sciences Digital vs nalog Logic =? lgebra Logic = lgebra oolean lgebra Exercise Rev.
More informationLogical Agents. Outline
ogical gents Chapter 6, Ie Chapter 7 Outline Knowledge-based agents Wumpus world ogic in general models and entailment ropositional (oolean) logic Equivalence, validity, satisfiability Inference rules
More informationProve that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).
hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove
More informationModal Logic XXI. Yanjing Wang
Modal Logic XXI Yanjing Wang Department of Philosophy, Peking University May 17th, 2017 Advanced Modal Logic (2017 Spring) 1 Completeness via Canonicity Soundness and completeness Definition (Soundness)
More informationEECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational
More informationSolvers for the Problem of Boolean Satisfiability (SAT) Will Klieber Aug 31, 2011
Solvers for the Problem of Boolean Satisfiability (SAT) Will Klieber 15-414 Aug 31, 2011 Why study SAT solvers? Many problems reduce to SAT. Formal verification CAD, VLSI Optimization AI, planning, automated
More informationDesign of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates
International Journal of omputer pplications (975 8887) Volume 66 No.9, March 23 Design of Fault Tolerant Reversible Multiplexer based Multi-oolean Function enerator using Parity Preserving ates Rakshith
More informationChapter 7 R&N ICS 271 Fall 2017 Kalev Kask
Set 6: Knowledge Representation: The Propositional Calculus Chapter 7 R&N ICS 271 Fall 2017 Kalev Kask Outline Representing knowledge using logic Agent that reason logically A knowledge based agent Representing
More informationChapter # 3: Multi-Level Combinational Logic
hapter # 3: Multi-Level ombinational Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. 3- hapter Overview Multi-Level Logic onversion to NN-NN and - Networks emorgan's
More informationECE 3060 VLSI and Advanced Digital Design. Testing
ECE 3060 VLSI and Advanced Digital Design Testing Outline Definitions Faults and Errors Fault models and definitions Fault Detection Undetectable Faults can be used in synthesis Fault Simulation Observability
More informationSAT in Formal Hardware Verification
SAT in Formal Hardware Verification Armin Biere Institute for Formal Models and Verification Johannes Kepler University Linz, Austria Invited Talk SAT 05 St. Andrews, Scotland 20. June 2005 Overview Hardware
More informationLOGIC PROPOSITIONAL REASONING
LOGIC PROPOSITIONAL REASONING WS 2017/2018 (342.208) Armin Biere Martina Seidl biere@jku.at martina.seidl@jku.at Institute for Formal Models and Verification Johannes Kepler Universität Linz Version 2018.1
More informationTAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th,
TU 2014 Contest Pessimism Removal of Timing nalysis v1.6 ecember 11 th, 2013 https://sites.google.com/site/taucontest2014 1 Introduction This document outlines the concepts and implementation details necessary
More informationPropositional Logic: Evaluating the Formulas
Institute for Formal Models and Verification Johannes Kepler University Linz VL Logik (LVA-Nr. 342208) Winter Semester 2015/2016 Propositional Logic: Evaluating the Formulas Version 2015.2 Armin Biere
More informationGoals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations
Introduction to Electrical Engineering, II LETURE NOTES #2 Instructor: Email: Telephone: Office: ndrew. Kahng (lecture) abk@ucsd.edu 858-822-4884 office 3802 P&M lass Website: http://vlsicad.ucsd.edu/courses/ece20b/wi04/
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer rchitecture David Money Harris and
More informationLast update: March 4, Logical agents. CMSC 421: Chapter 7. CMSC 421: Chapter 7 1
Last update: March 4, 00 Logical agents CMSC 4: Chapter 7 CMSC 4: Chapter 7 Outline Knowledge-based agents Wumpus world Logic in general models and entailment Propositional (oolean) logic Equivalence,
More informationBuilt-In Test Generation for Synchronous Sequential Circuits
Built-In Test Generation for Synchronous Sequential Circuits Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242 Abstract We consider
More informationCSE 20 DISCRETE MATH WINTER
CSE 20 DISCRETE MATH WINTER 2016 http://cseweb.ucsd.edu/classes/wi16/cse20-ab/ Today's learning goals Evaluate which proof technique(s) is appropriate for a given proposition Direct proof Proofs by contraposition
More information:3 2 D e c o de r S ubs ys te m "0 " One "1 " Ze ro "0 " "0 " One I 1 "0 " One "1 " Ze ro "1 " Ze ro "0 " "0 "
dvanced igital Logic esign EES 303 http://ziyang.eecs.northwestern.edu/eecs303/ 5:32 decoder/demultiplexer Teacher: Robert ick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 \EN 5:32
More informationCSE 20 DISCRETE MATH SPRING
CSE 20 DISCRETE MATH SPRING 2016 http://cseweb.ucsd.edu/classes/sp16/cse20-ac/ Today's learning goals Evaluate which proof technique(s) is appropriate for a given proposition Direct proof Proofs by contraposition
More informationECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions
Last (Family) Name: KIME First (Given) Name: Student I: epartment of Electrical and omputer Engineering University of Wisconsin - Madison EE/omp Sci 352 igital System Fundamentals Quiz # Solutions October
More information14:332:231 DIGITAL LOGIC DESIGN
14:332:231 IGITL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering all 2013 Lecture #17: locked Synchronous -Machine nalysis locked Synchronous Sequential ircuits lso known as
More information2.2: Logical Equivalence: The Laws of Logic
Example (2.7) For primitive statement p and q, construct a truth table for each of the following compound statements. a) p q b) p q Here we see that the corresponding truth tables for two statement p q
More informationBoole Algebra and Logic Series
S1 Teknik Telekomunikasi Fakultas Teknik Elektro oole lgebra and Logic Series 2016/2017 CLO1-Week2-asic Logic Operation and Logic Gate Outline Understand the basic theory of oolean Understand the basic
More informationGeo - CH2 Practice Test
Geo - H2 Practice Test Multiple hoice Identify the choice that best completes the statement or answers the question. 1. Find the next item in the pattern 2, 3, 5, 7, 11,... a. 13 c. 15 b. 12 d. 17 2. The
More informationPropositional Logic: Semantics
Propositional Logic: Semantics Alice Gao Lecture 4, September 19, 2017 Semantics 1/56 Announcements Semantics 2/56 The roadmap of propositional logic Semantics 3/56 FCC spectrum auction an application
More informationComp487/587 - Boolean Formulas
Comp487/587 - Boolean Formulas 1 Logic and SAT 1.1 What is a Boolean Formula Logic is a way through which we can analyze and reason about simple or complicated events. In particular, we are interested
More informationAlgorithms for ATPG under Leakage Constraints
Algorithms for ATPG under Leakage Constraints Görschwin Fey fey@informatik.uni-bremen.de Institute of Computer Science, University of Bremen, 28359 Bremen, Germany Abstract Measuring the steady state leakage
More information