FOF (Functionally Observable Fault): A unified mode for testing and debugging - ATPG and application to debugging -

Transcription

1 FOF Functionally Observable Fault: uniied mode or testing and debugging - TPG and application to debugging - Masahiro Fujita VLSI Design and Education enter VDE University o Tokyo

2 Stuck-at ault and unctional ault For an 2-input EOR gate: Only 6 dierent unctions with stuck-at aults =5 dierent unctions with unctional aults y y y y y y s-a-0: stuck at 0 s-a-: stuck at y y s-a- s-a-0 s-a- s-a-0 y y s-a- y y Non-aulty y y s-a-0 0 y y

3 FOF: Functionally Observable Fault ny aults/errors which eist only inside sub-circuits They cannot reer to signals outside o the sub-circuits Many simultaneous multiple aults/errors are targeted Not allowed Erroneous/aulty Erroneous/aulty 2 Entire circuit Erroneous/aulty n Faulty/erroneous sub-circuits are replacing suspicious portions o the buggy entire circuit Under aults/errors this can become any logic unction FOF can be a good model or logical debugging as well as test Is there eicient procedures say based on ST available? ES! Need Incremental ST instead o ST 3

4 Problem ormulation Look up Table can represent all logic unctions with the set o inputs Introducing programmable variables see net slide Then the problem becomes QF Quantiied oolean Formula ProgVar. Input. ProgVar Input = TargetNewSPEInput Given appropriate programming o the circuit is equivalent to the spec 4 Input ProgVar ProgVar ProgVar TargetSPEInput Erroneous portion

5 Representation o with ProgVar Each row o truth table is assigned a program variable 2-inut needs 4 variables 4-input needs 6 variables and so on an represent all possible logic unctions Determining values o ProgVar is to decide the logic unction ssign appropriate values to -4 so that the outputs o the circuit becomes correct in in2 out in in2 2-input out Truth table or

6 Debugging problem 6 Given counter eamples test cases that do not produce correct outputs Locate suspicious portions o HW/SW ome up with possible correction on them Make sure the corrected HW/SW is OK start veriication process again. I not repeat the debugging process alled counter eample Input HW SW Wrong output Locate suspicious portions HW SW v Generate possible corrections HW SW v Veriication eorts may have to be repeated many times!

7 buggy design or a -bit ull adder 7 iication buggy implementation Erroneous portion

8 trace o correction or a -bit ull adder 8. iication Replace an EOR with Truth table or D input Erroneous portion

9 Simple eample: Step. 000 Outputs must be equal when inputs are 000 and These are necessary conditions EQ check EQ check an be solved as simple ST problem I unsat there is no way to rectiy Truth table or D urrent solution Synthesis rom sample values necessary conditions 9

10 Simple eample: Step ased on current solution check i it is actually a real solution Outputs can never become non-equal Non-EQ check Typical ST ormulation I unsat current solution candidate is real solution = 00 is a counter eample

11 Simple eample: Step3 dd the counter eample to the constraints Outputs must be equal when inputs are 000 and Generate solution candidates or ny counter eample with the current solution? dd counter eample to constraints Inputs Truth table or D Inputs Truth table or D There is no counter eample and so inished

12 This two-level QF can be eiciently solved by incremental ST solvers asically we are solving the ollowing incremental ST problems until becoming UNST.. SPE n n => ST solution is y n n => ST solution is y 3 3 => ST solution is y 2 2 => ST solution is y n n n n => UNST Then 2 n are complete test vectors! Word-level designs can be similarly TPGed with SMT 2

13 Observation 3 With slight modiication we can generate sets o test vectors by which 00% and so ormal analysis correctness o portions o circuits can be checked hecking i there is any other solution candidate which behaves dierently rom the current solution This is a ST problem Test vectors realize complete veriication assuming that all the other portions o circuits are correct ied nd we can model simultaneous multiple aults/errors easily Numbers o iterations are the numbers o test vectors needed Normally tens or hundreds or ISS85 and OpenRIS

14 Larger eample ISS85 circuit c2670: 2-bit LU and controller inputs; 40 outputs; 93 gates I we do not know internal structure below we need to simulate or complete analysis In other words i we like to analyze entire circuits we have to do so implicit/eplicit ut i we only like to analyze their portions any dierence?

15 5 Larger eample 2 I we like only to check the grey areas are correct or not do we need vectors or complete analysis? No we need only 00 primary input vectors or 00% analysis There is an assumption that non grey areas are correct ied

16 TPG results or ISS85 circuits ll error/aulty sub-circuits are two-input gates 6 Number o test vectors grows with #aulty sub-circuits 0.7

17 Results by incremental ST solvers 7 Incremental ST solvers are 0-40 aster

18 Overview o application to debugging Introducing programmability or ormulation o debugging Implementationbuggy iication orrected design

19 Overview o application to debugging 2 Implementationbuggy iication uggy design and speciication are given orrected design

20 Overview o application to debugging 3 Implementationbuggy iication Replace buggy gates with Look-Up Tables s as ormulation

21 Overview o application to debugging 4 Program truth table to make implementation equivalent to its speciication Implementationbuggy a b z a b z iication

22 Overview o application to debugging 5 Modiy implementation based on the correction Implementationbuggy a b z a b z iication

23 Problem encountered when applied to industrial designs Missing wire errors cannot be corrected by only replacing gates with s Need methods to add more inputs iication iication does not have input Implementation Implementation No way to correct!

24 Proposed method dd more variables to inputs o s with MUs Here and one o D E F G are possible inputs to the Original Inputs lut_out dditional Inputs D E F G MU

25 Eperimental Results Real designs in industry RM processor rom Openore round 50% o bugs additional inputs are required Such eamples are shown below: Gate Input Input o MU Selected Variables Timeonvert/ST solving [sec] Industrial no MU - Timeout >5[h] RM processor / / / no MU - Timeout >5[h] / / /4585

26 Future perspectives 26 The proposed techniques can be etended in varieties o ways: For sequential circuits other than time-rame epansion For high level designs such as word-level or -based designs For automatic assertion generations or generation o complicated implications with small numbers o test vectors For general logic optimization o logic circuits For Engineering hange Order EO