Unit 9. Multiplexers, Decoders, and Programmable Logic Devices. Unit 9 1
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1 Unit 9 Multiplexers, ecoders, and Programmable Logic evices Unit 9
2 Outline Multiplexers Three state buffers ecoders Encoders Read Only Memories (ROMs) Programmable logic devices ield Programmable Gate rrays (PGs) Unit 9 2
3 Multiplexers (/5) to MUX Z ʼ ʼ 7 8 to MUX Z 2 3 Z 2 n - 2 n to MUX n control inputs Z 4 Z 8 Z 2 n Z Unit 9 3 n 2 k m k k
4 Multiplexers (2/5) Quad multiplexer to select data 2 Mux Z 2 Mux 2 Mux Z 2 Mux Z Z 2 3 X S X S X 2 S X 3 S Y S 2 Y S 2 Y 2 S 2 Y 3 S 2 EN EN EN EN EN Unit 9 4
5 Multiplexers (3/5) 4-to- MUX to realize 3-variable function Ex (,, ) ( ) to- MUX S S 2 Unit 9 5
6 Multiplexers (4/5) 8-to- MUX to realize 4-variable function = ʼʼʼ + ʼ + ʼ + ʼʼ + ʼ = ʼʼʼ(+ʼ) + ʼ (+ʼ) + (+ʼ)ʼ + (+ʼ)ʼʼ + (+ʼ)ʼ Unit to MUX
7 Unit n n n V V V V V 2 n n n V V V V V = ʼʼʼ(+ʼ) + ʼ (+ʼ) + (+ʼ)ʼ+ (+ʼ)ʼʼ+ (+ʼ)ʼ Multiplexers (5/5)
8 Three-State uffers (/4) uffers to increase the driving capability of a gate output Tri-state (three-state) uffers permits gate outputs to be connected together Unit 9 8
9 Unit 9 9 Table Truth Z Z Table Truth Z Z Truth table ata selection using three-state buffers Three-State uffers (2/4) 2-to- MUX
10 Three-State uffers (3/4) ircuits with two three-state buffers S S2 S X Z X X X X X S2 X X X X Z X Z Unit 9
11 Three State uffers (4/4) pplications. us E bit adder 4 Sum En En En En out 2. hip /O EN Output ntegrated Logic ircuit nput i-irectional nput-output Pin Unit 9
12 ecoders (/4) Generate all of the minterms of inputs a b c m m m 2 m 3 m 4 m 5 m 6 m 7 y a b c y a b c y7 abc m m m 7 a b c Y Y Y2 Y3 Y4 Y5 Y6 Y7 Unit 9 2
13 ecoders (2/4) y y y y y 2 y 3 2-to-4 decoder y y y 2 y 3 y 7 Unit 9 3
14 Unit (type #) m 9 m 8 m 7 m 6 m 5 m 4 m 3 m 2 m m input ecimal output ecoders (3/4) nputs Outputs
15 ecoders (4/4) Realization of a multiple output circuit using a decoder m m2 m4 2 m4 m7 m9 4-to- ecoder m m2 m4 m7 m9 2 Unit 9 5
16 Encoders y y y2 y3 y4 y5 y6 y7 a b c d X X X X X X X X X X X X X X X X X X X X X X X X X X X X Unit 9 6
17 nputs n LS circuit to realize multiple output oolean function(s) ROM 8 words 4 bits 2 3 Outputs Read Only Memories (/5) 2 3 Unit 9 7 mmm5m7 m2m3m4 m5m7 m m m m m m m 3m6m Stored in ROM (2 3 words of 4 bits each)
18 General orm n inputs Read Only Memories (2/5) ROM 2 n words m bits m outputs n inputs m outputs m 2 n words Unit 9 8
19 Read Only Memories (3/5) w w w 2 w 3 w w w 2 w 3 n inputs decoder 2 n words Memory array 2 n words m bits asic ROM structure m outputs Unit 9 9
20 Read Only Memories (4/5) ROM as logic devices (use decoder and diodes) to-8 decoder m m m 2 m 3 m 4 m 5 m 6 m 7 word line m m m 4 m 6 m m m 4 m 6 m m m 4 m OR-Plane Unit 9 2
21 Read Only Memories (5/5) m(,,4,6) m(2,3,4,6,7) 2 m(,,2,6) 3 m(2,3,5,6,7) Expressed with dots 3-to-8 decoder m m m 2 m 3 m 4 m 5 m 6 m 7 v v v v v v v v v v v v v v v v 2 3 () Use mask to program ROM (2) EPROM (Erasable Programmable) UV light (3) EEPROM (Electrically Erasable) Unit 9 2
22 n Various kinds PL, PL PLs n m realizes m functions with n inputs 2-level N rray (plane) not 2 n OR rray (plane) m ROM directly implements truth table Programmable Logic evices (/7) SOP implementation Unit 9 22 V+ N plane Z= f any of, is not activiated, GN or = GN i.e., or Z= V+
23 Programmable Logic evices (2/7) 2 3 OR plane X Y X Y nput V+ V+ V+ V+ V+ 2 3 Output Unit 9 23
24 Programmable Logic evices (3/7) Equivalent N - OR rray OR array N array 2 3 Unit 9 24
25 Example Programmable Logic evices (4/7) m 2,3,5,7,8,9,,,3,5 2 m 2,3,5,6,7,,,4,5 3 m 6,7,8,9,3,4,5 Minimized multiple output expressions (using K-Map) abd abd abc bc 2 c abd 3 bc abc abd PL table Unit 9 25 a b c d 2 3
26 a b c d 2 3 a b c d Programmable Logic evices (5/7) Mask programmable PL ield programmable PL nputs a b c 2 3 Outputs Unit 9 26 d PL structure Word line row,5,6 selected, (st) (5th) (6th) 2 3 no rows selected, 23 row 3 selected, 23
27 PLs n m realizes m functions with n inputs special case of PL Programmable Logic evices (6/7) N array programmable OR array NOT programmable programmed 8 Unprogrammed Unit 9 27
28 Programmable Logic evices (7/7) PL Summary N rray OR rray PL Programmable Programmable PL Programmable ixed ROM ixed Programmable Not Programmable ixed ixed Unit 9 28
29 ield Programmable Gate rrays (/4) n that contains an array of identical logic cells with programmable interconnections onfigurable Logic lock /O lock nterconnect rea Layout of a typical PG Unit 9 29
30 ield Programmable Gate rrays (2/4) L configurable logic block G 4 G 3 G 2 G LUT G H * * K E SR Q YQ Y H LUT * * K E SR Q XQ X * = Programmable MUX Unit 9 3
31 ield Programmable Gate rrays (3/4) ecomposition of switching functions Shannon s expansion theorem (x, x 2, x i-, x i, x i+, ) = x iʼ +x i ab cd cd ab a= a= Unit 9 3
32 ield Programmable Gate rrays (4/4) Realization of 5- and 6-variable functions with 4-variable function generators (G) b c d e b c d e G G a c d ef c d ef c d ef G G G G G G b G a G c d ef G G b G (a) 5-variable function (b) 6-variable function Unit 9 32
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