Chapter # 4: Programmable and Steering Logic

Transcription

1 hapter Overview PLs and PLs hapter # : Programmable and teering Logic Non-Gate Logic witch Logic Multiplexers/electers and ecoders Tri-tate Gates/Open ollector Gates ROM ombinational Logic esign Problems even egment isplay ecoder Process Line ontroller Logical unction Unit arrel hifter - - PLs and PLs Pre-fabricated building block of many N/OR gates (or NOR, NN) "Personalized" by making or breaking connections among the gates Programmable rray lock iagram for um of Products orm PLs and PLs Key to uccess: hared Product Terms Example: Equations = + ' ' = ' + = ' ' + = ' + Inputs ense array of N gates Product terms ense array of OR gates Outputs Product t erm Personality Matrix Inputs Outputs Reuse of t erms Input ide: = asserted in term = negated in term - = does not participate Output ide: = term connected to output = no connection to output - -

2 PLs and PLs Example ontinued ll possible connections are available before programming PLs and PLs Example ontinued Unwanted connections are "blown" / / // Note: some array structures work by making connections rather than breaking them - - PLs and PLs lternative representation for high fan-in structures PLs and PLs esign Example Multiple functions of,, hort-hand notation so we don't have to draw all the wires! = = + + = // / / Notation for implementing = + ' ' = ' + ' = + + = xor xor = xor xor +// /+/ -7-8

3 PLs and PLs What is difference between Programmable rray Logic (PL) and Programmable Logic rray (PL)? PL concept : implemented by Monolithic Memories (substrate is active materialsuch as semiconductor silicon) programmable N array but constrained topology of the OR rray connections between product terms are hardwired the higher the OR gate fanins, the fewer the functional outputs from PL given column of the OR array has access to only a subset of the possible product terms PLs and PLs esign Example: to Gray ode onverter Truth Table K-maps W Y K-map for W K-map for PL concept : generalized topologies in N and OR planes take advantage of shared product terms slower Minimized unctions: W = + + = ' Y = + = ''' + + ' + ' ' K-map for Y K-map for -9 - PLs and PLs Programmed PL: PLs and PLs ode onverter iscrete Gate Implementation product terms per each OR gate W Y / / / \ \ \ W Y \ \ I Packages vs PL/PL Package! \ \ \ \ : 7 hex inverters,: 7 quad -input NN : 7 t ri -input NN : 7 dual -input NN - -

4 PLs and PLs nother Example: Magnitude omparator = < > K-map for EQ K-map for NE Non-Gate Logic Introduction N-OR-Invert PL/PL Kinds of "Non-gate logic": Generalized uilding locks eyond imple Gates switching circuits built from MO transmission gates multiplexer/selecter functions decoders tri-state and open collector gates read-only memories K-map for L T K-map for GT EQ NE LT GT - - teering Logic: witches Voltage ontrolled witches teering Logic Voltage ontrolled witches ource Gate Oxide ilicon ulk rain hannel Region n-type i p-type i ource Gate nmo Transistor rain Logic on gate, ource and rain connected "n-hannel MO" Metal Gate, Oxide, ilicon andwich iffusion regions: negatively charged ions driven into i surface ource Gate pmo Transistor rain Logic on gate, ource and rain connected i ulk: positively charged ions y "pulling" electrons to the surface, a conducting channel is formed - -

5 teering Logic Logic Gates from witches teering Logic Inverter Operation +V +V +V +V +V + "" "" "" "" Inverter NN Gate NOR Gate Pull-up network constructed from pmo transistors Input is Pull-up does not conduct Pull-down conducts Output connected to GN Input is Pull-up conducts Pull-down does not conduct Output connected to V Pull-down network constructed from nmo transistors -7-8 teering Logic teering Logic NN Gate Operation NOR Gate Operation +V "" "" +V "" "" +V "" "" +V "" "" "" "" "" "" =, = Pull-up network does not conduct Pull-down network conducts Output node connected to GN =, = Pull-up network has path to V Pull-down network path broken Output node connected to V =, = Pull-up network conducts Pull-down network broken Output node at V =, = Pull-up network broken Pull-down network conducts Output node at GN -9 -

6 teering Logic MO Transmission Gate teering Logic election unction/emultiplexer unction with Transmission Gates nmo transistors good at passing 's but bad at passing 's produce weak pmo transistors good at passing 's but bad at passing 's produce weak elector: hoose I if = hoose I if = I perfect "transmission" gate places these in parallel: I ontrol ontrol ontrol In ontrol Out In ontrol Out In ontrol witches Transistors Transmission or "utterfly" Gate Out emultiplexer: I to if = I to if = I - - teering Logic Use of Multiplexer/emultiplexer in igital ystems Y teering Logic Well-formed witching Networks Problem with the emux implementation: multiple outputs, but only one connected to the input! emultiplexers Multiplexers emultiplexers Multiplexers Y I "" "" o far, we've only seen point-to-point connections among gates Mux/emux used to implement multiple source/multiple destination interconnect The fix: additional logic to drive every output to a known value Never allow outputs to "float" - -

7 teering Logic omplex teering Logic Example N Input Tally ircuit: count # of 's in the inputs teering Logic omplex teering Logic Example Operation of the Input Tally ircuit "" I ero I "" traight Through I "" "" "" "" I ero "" iagonal ero "" "" ero "" ero "" "" ero onventional Logic for Input Tally unction "" "" witch Logic Implementation of Tally unction Input is, straight through switches enabled - - teering Logic omplex teering Logic Example Operation of input Tally ircuit teering Logic omplex teering Logic Example Extension to the -input case "" "" "" I I ero T wo I I ero "" "" ero "" "" ero T wo onventional logic implementation "" Input =, diagonal switches enabled -7-8

8 teering Logic omplex teering Logic Example witch Logic Implementation: -input Tally ircuit teering Logic omplex teering Logic Example Operation of -input implementation I I "" "" I "" Two I "" "" "" "" ero "" Two ero "" "" "" "" "" ero "" "" "" "" "" "" "" "" "" ero "" "" "" "" "" "" "" ascade the -input implementation! "" "" "" "" "" "" "" "" "" "" "" ero ero "" ero "" "" ero "" "" "" "" "" "" "" -9 - Multiplexers/electors Use of Multiplexers/electors Multi-point connections Multiple input sources Multiplexers/electors General oncept n data inputs, n control inputs, output n used to connect points to a single point control signal pattern form binary index of input connected to output a MU MU b s um EMU Multiple output destinations = ' I + I unctional form Logical form I I I I - Two alternative forms for a : Mux Truth Table -

9 Multiplexers/electors I I : mux = ' I + I Multiplexers/electors lternative Implementations I I I I : mux = ' ' I + ' I + ' I + I I I I I I I I I I I I I I I I 7 8: mux = ' ' ' I + ' ' I + ' ' I + ' I + ' ' I + ' I + ' I + I7 n - In general, = Σ m I k= k k in minterm shorthand form for a n : Mux Gate Level Implementation of : Mux thirty six transistors I Transmission Gate Implementation of : Mux twenty transistors - - Multiplexer/elector Large multiplexers can be implemented by cascaded smaller ones I I I I I I I I 7 : mux : mux 8: mux : mux lternative 8: Mux Implementation ontrol signals and simultaneously choose one of I-I and I-I7 ontrol signal chooses which of the upper or lower MU's output to gate to I I I I I I I I 7 Multiplexer/elector Multiplexers/selectors as a general purpose logic block n- : multiplexer can implement any function of n variables n- control variables; remaining variable is a data input to the mux Example: (,,) = m + m + m + m7 = ' ' ' + ' ' + ' + 8: MU 7 "Lookup Table" = ' ' (') + ' (') + ' () + () : MU - -

10 Multiplexer/elector Generalization n- Mux control variables single Mux data variable I I I n I n I n our possible configurations of the truth table rows an be expressed as a function of In,, Multiplexer/elector TTL quad : multiplexers with enable Example: G(,,,) can be implemented by an 8: MU: K-map hoose,, as control variables Multiplexer Implementation TTL package efficient May be gate inefficient 7 8: mux G -7-8 ecoders/emultiplexers ecoder: single data input, n control inputs, n outputs ecoders/emultiplexers lternative Implementations control inputs (called select ) represent inary index of output to which the input is connected G elect /G Output elect Output data input usually called "enable" (G) Output Output : ecoder: O = G ; O = G : ecoder: O = G O = G O = G O = G :8 ecoder: O = G O = G O = G O = G O = G O = G O = G O7 = G : ecoder, ctive High Enable : ecoder, ctive Low Enable G /G Output Output Output Output Output Output Output Output elect elect elect elect : ecoder, ctive High Enable : ecoder, ctive Low Enable -9 -

11 ecoders/emultiplexers witch Logic Implementations ecoders/emultiplexers witch Implementation of : ecoder G elect elect elect elect Output Output Naive, Incorrect Implementation ll outputs not driven at all times G "" "" elect elect elect elect elect elect elect Output Output elect elect G Output "" "" G Output "" "" G Output "" Operation of : ecoder =, = one straight thru path three diagonal paths elect "" orrect : ecoder Implementation G Output "" "" - - ecoder/emultiplexer ecoder as a Logic uilding lock Enb :8 dec 7 Example unction: = ' ' + ' ' + = ' ' + = (' + ' + ' + ') ecoder Generates ppropriate Minterm based on ontrol ignals ecoder/emultiplexer ecoder as a Logic uilding lock Enb : dec If active low enable, then use NN gates! - -

12 ecoder/emultiplexer TTL decoder components Multiplexers/ecoders lternative Implementations of : Mux EN I 7 EN I 7 Y EN W I 7 Y EN W 9 I7 7 Y I W I 9 I Y I W I 9 I I E Multiplexer Only G Y 7 Y 9 G O (,,,, E) G Y 7 7 9Y EN Y I 7 Y 7 ENI GY 9 I I Y Y 7 I Y 7 EN Y 9 W I I I 7I I I Y 7 I EN 9 W I I I7 7I I Y I I I E 9 W I I I I I Y I E 9 W I I I E E Multiplexer + ecoder (,,,, E) - - Multiplexers/ecoders : ecoder \EN \Y : ecoder ubsystem \Y \EN G Y 9 Y Y Y G Y Y Y Y G G G 8 G G G Y7 Y Y Y Y Y Y Y Y7 Y Y Y 8 Y Y Y Y G Y7 G Y G Y 8 Y Y Y Y Y \Y \Y \Y9 \Y8 \Y7 \Y \Y \Y \Y \Y \Y \Y \Y9 \Y8 \Y7 \Y \Y \Y \Y \Y \Y \Y \Y9 \Y8 Tri-tate and Open-ollector The Third tate Logic tates: "", "" on't are/on't Know tate: "" (must be some value in real circuit!) Third tate: "" high impedance infinite resistance, no connection Tri-state gates: output values are "", "", and "" additional input: output enable () When is high, this gate is a non-inverting "buffer" When is low, it is as though the gate was disconnected from the output! This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time G Y7 G Y G Y 8 Y Y Y Y Y \Y7 \Y \Y \Y \Y \Y \Y \Y -7 Non-inverting buffer's timing waveform "" "" -8

13 Tri-state and Open ollector Using tri-state gates to implement an economical multiplexer: Input Tri-state and Open ollector lternative Tri-state ragment Input ctive low tri-state enables plus inverting tri-state buffers Input When electinput is asserted high Input is connected to Input When electinput is driven low Input is connected to This is essentially a : Mux electinput electinput I witch Level Implementation of tri-state gate -9 - Tri-tate and Open ollector : Multiplexer, Revisited \EN G Y Y 9 Y Y G Y Y Y Y 7 9 ecoder + tri-state Gates V Tri-tate and Open ollector Open ollector another way to connect multiple gates to the same output wire Open-collector NN gate gate only has the ability to pull its output low; it cannot actively drive the wire high this is done by pulling the wire up to a logic voltage through a resistor Pull-up resistor +V + V O NN gates Wired N: If and are "", output is actively pulled low if and are "", output is actively pulled low if one gate is low, the other high, then low wins if both gates are "", the output floats, pulled high by resistor Hence, the two NN functions are N'd together! - -

14 Tri-tate and Open ollector : Multiplexer Tri-tate and Open ollector TTL tri-state buffers \EN G Y 9 Y Y Y 7 \I OR +V \I OR \I OR \I OR ecoder + Open ollector Gates - - Read-Only Memories ROM: Two dimensional array of 's and 's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize ddress is input, selected word is output ec n - i j +V +V +V +V Word Line Word Line Read-Only Memories Example: ombination Logic Implementation = ' ' + ' ' + ' = ' ' + ' ' + = ' ' ' + ' ' + ' ' = ' + ' ' + ' ROM 8 w ords? by bits ddress W ord ontents n- ddress it Lines Internal Organization address outputs - -

15 Read-Only Memories Read-Only Memories Not unlike a PL structure with a fully decoded N array! n address lines ecoder n word lines ROM vs PL: ROM approach advantageous when () design time is short (no need to minimize output functions) () most input combinations are needed (eg, code converters) () little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PL approach advantangeous when () design tool like espresso is available () there are relatively few unique minterm combinations () many minterms are shared among the output functions PL problem: constrained fan-ins on OR planes Memory array n words by m bits m output lines 7 EPROM 8K x 8 7 VPP PGM O7 9 O 8 O 7 O O O O O K x ubsystem / : :8 7: 7 VPP + PGM + O7 9 8 O O 7 O O O O O U + 7 VPP PGM O7 9 O 8 O 7 O O O O O U + 7 VPP PGM O7 9 O 8 O 7 O O O O O U 7 VPP PGM 9 O7 8 O 7 O O O O O O U -7-8 ombinational Logic Word Problems General esign Procedure Understand the Problem what is the circuit supposed to do? write down inputs (data, control) and outputs draw block diagram or other picture ormulate the Problem in terms of a truth table or other suitable design representation truth table or waveform diagram hoose Implementation Target ROM, PL, PL, Mux, ecoder + OR, iscrete Gates ollow Implementation Procedure K-maps, espresso, misii ombinational Logic Word Problems Process Line ontrol Problem tatement of the Problem Rods of varying length (+/-%) travel on conveyor belt Mechanical arm pushes rods within spec (+/-%) to one side econd arm pushes rods too long to other side Rods too short stay on belt light barriers (light source + photocell) as sensors esign combinational logic to activate the arms Understanding the Problem Inputs are three sensors, outputs are two arm control signals ssume sensor reads "" when tripped, "" otherwise all sensors,, raw a picture! -9 -

16 ombinational Logic Word Problems Process ontrol Problem +% ombinational Logic Word Problems Process ontrol Problem + % + % RO Too Long pec RO Within pec pec - % RO Too hort pec - % - % Too Long Within pec Too hort pectification - % pecification + % to distance place apart at specification - % Where to place the light sensors,, and to distinguish among the three cases? to distance placed apart at specification +% ssume that detects the leading edge of the rod on the conveyor - - ombinational Logic Word Problems Process ontrol Problem ombinational Logic Word Problems to 7 egment isplay ontroller unction too short in spec too long Truth table and logic implementation now straightforward "too long" = (all three sensors tripped) "in spec" = ' (first two sensors tripped) Understanding the problem: input is a bit bcd digit output is the control signals for the display inputs,,, 7 outputs ~ 7-egment display -to-7-segment control signal decoder - lock iagram -

17 ombinational Logic Word Problems to 7 egment isplay ontroller ombinational Logic Word Problems to 7 egment isplay ontroller ormulate the problem in terms of a truth table hoose implementation target: if ROM, we are done don't cares imply PL/PL may be attractive ollow implementation procedure: K-map for K-map for K-map for hand reduced K-maps vs espresso K-map for K-map for K-map for K-map for - = ' ' = + ' ' + + ' = + + ' + Unique Product Terms = ' ' + ' + ' + ' = ' ' + = + ' ' + ' + ' = + ' + ' + ' - ombinational Logic Word Problems Increment to 7 egment isplay ontroller irst fuse numbers ombinational Logic Word Problems to 7 egment isplay ontroller Increment irst fuse numbers 8 8 H8PL an Implement the function H8PL annot Implement the function Note: use number = first fuse number + increment Note: use number = first fuse number + increment -7-8

18 ombinational Logic Word Problems to 7 egment isplay ontroller PL programming map ombinational Logic Word Problems to7 egment isplay ontroller i o 7 ilb a b c d ob c c c c c c c p e espresso input i o 7 ilb a b c d ob c c c c c c c p e espresso output = ' + + ' ' + ' + = ' + ' ' + + ' ' = ' + ' + ' ' + + ' = ' + ' + ' ' + ' = ' ' + ' = ' + ' ' + + ' = ' + ' + ' + 9 Unique Product Terms! Literals, Gates -9-7 ombinational Logic Word Problems to 7 egment isplay ontroller PL Implementation ombinational Logic Word Problems to7 egment isplay ontroller Multilevel Implementation = ' + ' Y = ' ' = + ' ' + Y = Y + ' ' + ' ' = + ' ' + ' = + + ' ' ' literals gates Ineffective use of don't cares = ' Y + ' ' = ' + Y + ' = + + ' + ' ' -7-7

19 ombinational Logic Word Problems Logical unction Unit tatement of the Problem: control inputs:,, data inputs:, output: ombinational Logic Word Problems Logical unction Unit ormulate as a truth table hoose implementation technology -variable K-map espresso multiplexor implementation TTL packages: x -input NN x -input NOR x -input OR 8: MU + V E N Q O ombinational Logic Word Problems Logical unction Unit ombinational Logic Word Problems 8-Input arrel hifter ollow implementation procedure = = = ' ' ' + ' ' + ' ' + ' gates, inverters lso four packages: x -input NN x -input NN lternative: x -bit ROM single package pecification: Inputs: 7,, ~ Outputs: O7, O, ~ O ontrol:,, Understand the problem: 7 O7 O O O O O O O,, = 7 shift input the specified number of positions to the right O7 O O O O O O O,, = 7 O7 O O O O O O O,, = -7-7

20 ombinational Logic Word Problems 8-Input arrel hifter ombinational Logic Word Problems 8-Input arrel hifter unction Table oolean equations O7 7 O 7 O 7 O 7 O 7 O 7 O 7 O 7 O7 = ' ' ' 7 + ' ' + + O = ' ' ' + ' ' O = ' ' ' + ' ' + + O = ' ' ' + ' ' + + O = ' ' ' + ' ' + + O = ' ' ' + ' ' traightforward gate logic implementation OR 8 by 8: multiplexer (wiring mess!) OR witch logic O7 O O O O O O O 7 O7 O O O O O O O O = ' ' ' + ' ' + + O = ' ' ' + ' ' rosspoint switches ully Wired crosspoint switch -78 hapter Review Non-imple Gate Logic uilding locks: PLs/PLs Multiplexers/electers ecoders ROMs Tri-state, Open ollector ombinational Word Problems: Understand the Problem ormulate in terms of a Truth Table hoose implementation technology Implement by following the design procedure -79