2. BOOLEAN SWITCHING ALGEBRA

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1 Boolean witching Algebra 2-2. BOOLEAN WITCHIN ALEBRA Objectives. Understand Boolean algebra. 2. tudy the basic rules governing logic analysis and design. eorge Boole, 85~864 John Venn, 834~ Logic Functions & witches () Boolean Algebra A mathematical foundation of digital systems. Axioms of Boolean Algebra Algebraic structure consisting of: set of elements containing at least two elements, a, b, such that binary operations { + }, { } unary operation {'} such that the following axioms hold: a ¹ b Closure: For every a, b in, a. a + b is in b. a b is in Associative laws: For every a, b, c in a. (a+b)+c=a+(b+c)=a+b+c b. (a b) c=a (b c)=a b c istributive laws: For every a, b, c in a. a+(b c)=(a+b) (a+c) b. a (b+c)=(a b)+(a c) Commutative Laws: For every a,b in, a. a + b = b + a b. a b = b a Identities: a. $ an identity element w.r.to { + }: a+=a for " a in b. $ an identity element w.r.to { }: a =a for " a in Complement: For each a in, $ a ( or a) a. a + a = b. a a = in s.t. Logic esign ong-eog Han

2 Boolean witching Algebra 2-2 Ex. The set = {,} B and the logical operations OR, AN, and NOT satisfy all the axioms of a Boolean algebra. Logic and in Boolean logic Logic Logic False True Off On Low High No es Open switch Closed switch Representation of Boolean Operations. ates, 2. Truth Table, 3. witches, 4. Venn diagram Function : NOT = = Logic symbol Logic function Truth Table t t t2 t3 t4 time witches Venn diagram Timing diagram Function : AN = = Logic symbol Logic function Truth Table t tt 2 t3 t4 t5 t6 t7 t8 witches Venn diagram Timing diagram time Logic esign ong-eog Han

3 Boolean witching Algebra 2-3 Function : OR = + Logic symbol Logic function Truth Table t tt 2 t3 t4 t5 t6 7 witches Venn diagram Timing diagram t t8 time Reference: Buffer = IEEE/ANI standard symbols Name or Function ymbol Variables Variables ' ' eneral IEEE logic symbol NOT gate & ³ AN gate OR gate Logic esign ong-eog Han

4 Boolean witching Algebra 2-4 Multiple inputs gates W W V W = ( ) = ( )( ) V = W = W Additional Logic ates Function ates Truth Table NAN NOR = ( ) = ( + ) OR NOR = Å = + = ( Å ) Consider multiple input OR/NOR gates IEEE/ANI standard symbol & ³ = = NAN gate NOR gate OR gate NOR gate Logic esign ong-eog Han

5 Boolean witching Algebra ate Logic Laws and Theorems of Boolean Algebra Operation with and :. + = 2. + = Idempotent theorem:. = 2. = 3. + = 3. = Theorem of complementarity: 4. ( ) = Theorem of complementarity: 5. + = 5. = Commutative law: 6. + = + 6. = Associative law: 7. ( + ) + = + ( + ) = ( ) ( ) istributive law: = = 8. ( + ) = ( ) = ( + ) ( + ) implification theorems: 9. + = 9. ( ) ( ). + =. ( + ) =. ( + ) =. ( ) emorgan s theorem + + = + = + 2. ( ) = ( ) { f (,,...,,,, +, 2 n )} 3. = f (,,...,,,,, + ) uality 2 n 4. ( ) = ( )... = = Logic esign ong-eog Han

6 Boolean witching Algebra 2-6 { } f (,,...,,,, +, 2 n ) 5. = f (,,...,,,,, + ) 2 Theorem for multiplying and factoring: n 6. ( + ) ( + ) = = ( + ) ( + ) Ex. implify the following Boolean functions to a minimum number of literals and implement with gates. a. ( )( ) ( ) + = + = + + = + = + b. ( ) ( ) ( ) + + = = = = + Equivalent ate NAN NOR AN OR Ex. enerate AN, OR, NOT gates with NAN or NOR. Ex. NOT, OR, AN gates implementation with NAN gates Ex. NOT, OR, AN gates implementation with NOR gates Ex. enerate NOT gate with EOR. Ex. Implement following Boolean logic with NAN gates. a. = f ( A, B, C, ) = AB + C b. = f ( A, B, C ) = ( A + B + C )( A + B + C ) Logic esign ong-eog Han

7 Boolean witching Algebra Logic Circuits IC: ECL, TTL, MO, CMO Basic logic gates elements IC name Function IC name Function Quad 2-input NAN Hex INVERTER Quad 2-input AN Triple 3-input NAN ual 4-input NAN Quad 2-input OR Quad 2-input NOR Hex INVERTER with open collector outputs Triple 3-input AN Triple 3-input NOR Quad 2-input OR emiconductor l R = r, r : resistivity [ W m] A emiconductors materials silicon (i), germanium (e) and gallium arsenide (aas) electrical properties somewhere in the middle, between those of a "conductor" and an "insulator". Logic esign ong-eog Han

8 Boolean witching Algebra 2-8 oping : the process of adding impurity atoms to semiconductor atoms (the order of impurity atom per million (or more) atoms of the semiconductor). ilicon Four valence electrons in its outer most shell which it shares with its adjacent atoms in forming covalent bonds. ilicon atoms are arranged in a definite symmetrical pattern making them a crystalline solid structure. A crystal of pure silicon (silicon dioxide or glass) is generally said to be an intrinsic crystal (it has no impurities). N-type semiconductor Introduce an impurity atom such as Arsenic, Antimony or Phosphorus into the crystalline structure making it extrinsic (impurities are added). Logic esign ong-eog Han

9 Boolean witching Algebra 2-9 P-type semiconductor Introduce a "Trivalent" (3-electron) impurity into the crystal structure, such as Aluminium, Boron or Indium, only three valence electrons are available in the outermost covalent bond meaning that the fourth bond cannot be formed. MO FET ource() Metal ate() rain() Contacts io 2 io 2 io 2 n n p ubstrate V R V I io 2 io 2 io 2 n Induced n-type Channel n p ubstrate Logic esign ong-eog Han

10 Boolean witching Algebra 2- ate ate rain ource rain ource nmo FET pmo FET nmo FET Inverter V R Logic Level 5% V IN Q V OUT Logic Level PHL t PLH t 5% CMO eneral NOT ate V Logic V pmo (implement ) Q Q 2 2 N nmo (implement ) Logic Q Q 2 ON OFF V V OFF ON CMO NOR ate Logic esign ong-eog Han

11 Boolean witching Algebra 2- V = + Q Q 2 Q Q3 4 Q Q Q Q ON ON OFF OFF V V ON OFF OFF ON V OFF ON ON OFF V V OFF OFF ON ON NAN ate V Q Q 2 Q 3 Q 4 = Q Q Q Q ON ON OFF OFF V V OFF ON OFF ON V V ON OFF ON OFF V V V OFF OFF ON ON Internal circuit of basic TTL ICs 4KW.6KW 3W KW Vcc N Vcc 4KW.6KW 3W 4W KW N 74 NAN 742 NOR Logic esign ong-eog Han

12 Boolean witching Algebra 2-2 4KW.6KW 3W Vcc Vcc 4KW 2KW.6KW 3W KW 8W N 744 INVERTER 748 AN KW N 4KW 4kW 2.5kW.6kW Vcc 3W kw kw N Voltage level of ICs 7432 OR Voltage for logic ( V ) Voltage for logic ( V ) IC type upply voltage Range Typical Range Typical TTL V = 5 CC 2.4 ~ ~.4.2 ECL V = -5.2 EE -.95 ~ ~ CMO V = 3 ~ V V ~ Quad 2-input AN gate IC N VCC Logic esign ong-eog Han

13 Boolean witching Algebra 2-3 Timing diagram of 744 chematic diagram for = f ( A, B, C, ) = ( A B + C ) Variable Name A B C Port Pin Number Part Number UA 74 UB IC Number U2A 742 Port Representation of an IC A B C Pin No A B C EMP 2 IC Name 7 Port Name Internal circuit Logic symbol Logic esign ong-eog Han

14 Boolean witching Algebra 2-4 Logic esign ong-eog Han EMP A B C N Vcc NC NC = no connection A B C Pin placement Truth table