Chapter # 4: Programmable and Steering Logic

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1 hapter # : Programmable and teering Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. - PLs and PLs Pre-fabricated building block of many N/OR gates (or NOR, NN) "Personalized" by making or breaking connections among the gates Programmable rray lock iagram for um of Products Form Inputs ense array of N gates Product terms ense array of OR gates Outputs No. -

2 Key to uccess: hared Product Terms Example: F = + ' ' F = ' + F = ' ' + F3 = ' + Personality Matrix Product t erm Inputs Outputs F F F F 3 Reuse of t erms Input ide: = asserted in term = negated in term - = does not participate Output ide: = term connected to output = no connection to output No. -3 Example ontinued ll possible connections are available before programming No. -

3 Example ontinued Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them No. - lternative representation for high fan-in structures hort-hand notation so we don't have to draw all the wires! Notation for implementing F = + ' F = ' + ' No. -6

4 esign Example Multiple functions of,, F = F = + + F3 = F = + + F = xor xor F6 = xnor xnor F F F3 F F F6 No. -7 What is difference between Programmable rray Logic (PL) and Programmable Logic rray (PL)? PL concept implemented by Monolithic Memories constrained topology of the OR rray given column of the OR array has access to only a subset of the possible product terms PL concept generalized topologies in N and OR planes No. -8

5 esign Example: to Gray ode onverter W Y K-map for W K-map for W = + + = Y = + K-map for Y K-map for = ''' + + ' + ' ' No. -9 Programmed PL: product terms per each OR gate No. -

6 ode onverter iscrete Gate Implementation \ \ 3 W \ \ \ 3 \ \ 3 \ \ Y : 7 hex inverters,: 7 quad -input NN 3: 7 t ri 3-input NN : 7 dual -input NN I Packages vs. PL/PL Package! No. - nother Example: Magnitude omparator K-map for EQ K-map for NE K-map for L T K-map for GT EQ NE LT GT No. -

7 Non-Gate Logic Introduction N-OR-Invert PL/PL Generalized uilding locks eyond imple Gates Kinds of "Non-gate logic": switching circuits built from MO transmission gates multiplexer/selecter functions decoders tri-state and open collector gates read-only memories No. -3 election Function/emultiplexer Function with Transmission Gates elector: hoose I if = hoose I if = I I emultiplexer: I to if = I to if = I No. -

8 Well-formed witching Networks Problem with the emux implementation: multiple outputs, but only one connected to the input! I "" "" The fix: additional logic to drive every output to a known value Never allow outputs to "float" No. - Multiplexers/electors Multi-point connections Multiple input sources a MU MU b um s EMU Multiple output destinations No. -6

General oncept n data inputs, n control inputs, output n used to connect points to a single point control signal pattern form binary index of input connected to output = ' I + I Functional form

9 General oncept n data inputs, n control inputs, output n used to connect points to a single point control signal pattern form binary index of input connected to output = ' I + I Functional form Logical form I I I I Two alternative forms for a : Mux Truth Table No. -7 I I : mux = ' I + I I I I I 3 : mux = ' ' I + ' I + ' I + I3 I I I I 3 I I I 6 I 7 8: mux = ' ' ' I + ' ' I + ' ' I + ' I3 + ' ' I + ' I + ' I6 + I7 n - In general, = m I k= k k n in minterm shorthand form for a : Mux No. -8

10 lternative Implementations I I I I3 Gate Level Implementation of of : : Mux thirty six transistors Transmission Gate Implementation of of : : Mux twenty transistors No. -9 I I I I 3 I I I 6 I 7 Large multiplexers can be implemented by cascaded smaller ones : mux 3 : mux 3 8: mux : mux lternative 8: Mux Implementation ontrol signals and simultaneously choose one of I-I3 and I-I7 ontrol signal chooses which of the upper or lower MU's output to gate to I I I I 3 I I 3 I 6 I 7 No. -

11 Multiplexers/selectors as a general purpose logic block n- : multiplexer can implement any function of n variables n- control variables; remaining variable is a data input to the mux Example: F(,,) = m + m + m6 + m7 = ' ' ' + ' ' + ' + = ' ' (') + ' (') + ' () + () 3 8: MU 6 7 F "Lookup Table" F 3 : MU No. - F Generalization n- Mux control variables I I I n F I n I n single Mux data variable Four possible configurations of the truth table rows an be expressed as a function of In,, No. -

12 Example: G(,,,) can be implemented by an 8: MU: K-map hoose,, as control variables : mux G Multiplexer Implementation TTL package efficient May be be gate inefficient No. -3 ecoders/emultiplexers ecoder: single data input, n control inputs, outputs - control inputs (called select ) represent inary index of output to which the input is connected - data input usually called "enable" (G) n : ecoder: O = G ; O = G : ecoder: O = G O = G O = G O3 = G 3:8 ecoder: O = G O = G O = G O3 = G O = G O = G O6 = G O7 = G No. -

13 lternative Implementations G elect Output /G elect Output Output Output : ecoder, ctive High Enable : ecoder, ctive Low Enable G Output /G Output Output Output Output Output Output3 Output3 elect elect elect elect : ecoder, ctive High Enable : ecoder, ctive Low Enable No. - witch Logic Implementations elect G elect elect elect elect Output Output Naive, Incorrect Implementation ll outputs not driven at all times G "" "" elect elect elect elect elect elect Output Output elect orrect : ecoder Implementation No. -6

14 witch Implementation of : ecoder elect elect G Output "" "" G Output "" "" Operation of : ecoder =, = one straight thru path three diagonal paths G Output "" "" G Output 3 "" "" No. -7 ecoder as a Logic uilding lock Enb 3:8 dec ecoder Generates ppropriate Minterm based on ontrol ignals Example Function: F = ' ' + ' ' + F = ' ' + F3 = (' + ' + ' + ') No. -8

15 ecoder/emultiplexer ecoder as a Logic uilding lock Enb :6 dec F 3 F F If active low enable, then use NN gates! No. -9 Multiplexers/ecoders lternative Implementations of 3: Mux EN I3 7 EN 6 I3 7 Y 3 6 EN W 6 I Y EN 6 W I7 7 Y 3 I6 6 W 6 I 9 I 3 Y I3 3 W 6 I 9 I I E Multiplexer Only G Y Y 9 G O F(,,,, E) G Y Y 6 EN 3 Y I3 7 3 Y 7 6 ENI GY3 9 I3 I 3 Y Y 7 I3 3 Y EN Y 9 W 6 I I I 7I I 3Y I 7 I3 3 EN 6 9 W 6 I I I 3 I7 7I Y I I6 6I3 3 E 9 W 6 I I I I I 3 Y I3 3 E 9 W 6 I I I E E Multiplexer + ecoder F(,,,, E) No. -3

16 Multiplexers/ecoders :3 ecoder \EN 3 G Y3 39 Y Y Y G Y3 Y Y Y G G G 38 Y7 Y6 Y Y Y3 Y Y Y \Y3 \Y3 \Y9 \Y8 \Y7 \Y6 \Y \Y \EN \Y3 :3 ecoder ubsystem... G G G Y7 Y6 Y Y 38 Y3 Y Y Y \Y3 \Y \Y \Y \Y9 \Y8 \Y7 \Y6 \Y 3 G Y7 G Y6 G Y 38 Y Y3 Y Y Y \Y \Y \Y3 \Y \Y \Y \Y9 \Y8 G Y7 G Y6 G Y 38 Y Y3 Y Y Y \Y7 \Y6 \Y \Y \Y3 \Y \Y \Y No. -3 Tri-tate and Open-ollector The Third tate Logic tates: "", "" on't are/on't Know tate: "" (must be some value in real circuit!) Third tate: "" high impedance infinite resistance, no connection Tri-state gates: output values are "", "", and "" additional input: output enable (OE) OE F When OE is high, this gate is a non-inverting "buffer" When OE is low, it is as though the gate was disconnected from the output! This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time Non-inverting buffer's timing waveform OE F "" "" No. -3

17 Tri-state and Open ollector Using tri-state gates to implement an economical multiplexer: Input F Input OE OE When electinput is asserted high Input is connected to F When electinput is driven low Input is connected to F This is essentially a : Mux electinput No. -33 Tri-state and Open ollector lternative Tri-state Fragment Input OE F ctive low tri-state enables plus inverting tri-state buffers Input OE electinput I F OE witch Level Implementation of tri-state gate No. -3

18 Tri-tate and Open ollector : Multiplexer, Revisited \EN G Y3 39 Y Y 3 Y G Y3 3 Y Y Y ecoder + tri-state Gates No. -3 Tri-tate and Open ollector Open ollector another way to connect multiple gates to the same output wire gate only has the ability to pull its output low; it cannot actively drive the wire high this is done by pulling the wire up to a logic voltage through a resistor Open-collector NN gate V Pull-up resistor + V F O NN gates Wired N: If and are "", output is actively pulled low if and are "", output is actively pulled low if one gate is low, the other high, then low wins if both gates are "", the output floats, pulled high by resistor Hence, the two NN functions are N'd together! No. -36

19 Tri-tate and Open ollector : Multiplexer \EN G Y3 39 Y 3 Y Y 7 6 \I3 OR +V F \I OR \I OR \I OR ecoder + Open ollector Gates No. -37 Read-Only Memories ROM: Two dimensional array of 's and 's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize ddress is input, selected word is output +V +V +V +V n - ec i j Word Line Word Line n- ddress it Lines Internal Organization No. -38

20 Read-Only Memories Example: ombination Logic Implementation F = ' ' + ' ' + ' F = ' ' + ' ' + F = ' ' ' + ' ' + ' ' F3 = ' + ' ' + ' ddress ROM 8 w ords by bits F F F F 3 W ord ontents F F F F 3 address outputs No. -39 Read-Only Memories Not Not unlike a PL PL structure with with a fully fully decoded N N array! array! ecoder n word lines Memory array n words by m bits n address lines m output lines ROM vs. PL: ROM approach advantageous when () design time is short (no need to minimize output functions) () most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PL approach advantangeous when () design tool like espresso is available () there are relatively few unique minterm combinations (3) many minterms are shared among the output functions PL problem: constrained fan-ins on OR planes No. -

21 Read-Only Memories 76 EPROM 8K x 8 76 VPP PGM O7 9 O6 8 O 7 O 6 O3 O O 3 O OE 6K x 6 ubsystem 3 /OE : :8 7: 76 VPP + PGM + O7 9 8 O6 O 7 O 6 O3 O O 3 O U3 OE + 76 VPP PGM O7 9 O6 8 O 7 O 6 O3 O O 3 O U OE + 76 VPP PGM O7 9 O6 8 O 7 O 6 O3 O O 3 O U OE 76 VPP PGM 9 O7 8 O6 7 O 6 O O3 O 3 O O U OE No. - ombinational Logic Word Problems General esign Procedure. Understand the Problem what is the circuit supposed to do? write down inputs (data, control) and outputs draw block diagram or other picture. Formulate the Problem in terms of a truth table or other suitable design representation truth table or waveform diagram 3. hoose Implementation Target ROM, PL, PL, Mux, ecoder + OR, iscrete Gates. Follow Implementation Procedure K-maps, espresso, misii No. -

22 ombinational Logic Word Problems Process Line ontrol Problem tatement of the Problem Rods of varying length (+/-%) travel on conveyor belt Mechanical arm pushes rods within spec (+/-%) to one side econd arm pushes rods too long to other side Rods too short stay on belt 3 light barriers (light source + photocell) as sensors esign combinational logic to activate the arms Understanding the Problem Inputs are three sensors, outputs are two arm control signals ssume sensor reads "" when tripped, "" otherwise all sensors,, raw a picture! No. -3 ombinational Logic Word Problems Process ontrol Problem +% RO Too Long + % pec RO Within pec + % pec - % RO Too hort pec - % - % Where to place the light sensors,, and to distinguish among the three cases? ssume that detects the leading edge of the rod on the conveyor No. -

23 ombinational Logic Word Problems Process ontrol Problem Too Long Within pec Too hort pectification - % pecification + % to distance place apart at specification - % to distance placed apart at specification +% No. - ombinational Logic Word Problems Process ontrol Problem Function too short in spec too long Truth table and logic implementation now straightforward "too long" = (all three sensors tripped) "in spec" = ' (first two sensors tripped) No. -6

24 ombinational Logic Word Problems to 7 egment isplay ontroller Understanding the problem: input is a bit bcd digit output is the control signals for the display inputs,,, 7 outputs 6 7-egment display to-7-segment control signal decoder 3 6 lock iagram No. -7 ombinational Logic Word Problems to 7 egment isplay ontroller Formulate the problem in terms of a truth table hoose implementation target: if ROM, we are done don't cares imply PL/PL may be attractive Follow implementation procedure: hand reduced K-maps vs. espresso No. -8

25 ombinational Logic Word Problems to 7 egment isplay ontroller K-map for K-map for K-map for K-map for 3 = ' ' = + ' ' + + ' = + + ' + Unique Product Terms K-map for K-map for 3 = ' ' + ' + ' + ' = ' ' + = + ' ' + ' + ' 6 = + ' + ' + ' K-map for 6 No. -9 ombinational Logic Word Problems Increment to 7 egment isplay ontroller First 3 fuse numbers H8PL an Implement the function Note: Fuse number = first fuse number + increment No. -

26 ombinational Logic Word Problems to 7 egment isplay ontroller Increment First fuse numbers H8PL annot Implement the function Note: Fuse number = first fuse number + increment No. - ombinational Logic Word Problems to 7 egment isplay ontroller PL Implementation No. -

27 ombinational Logic Word Problems to7 egment isplay ontroller Multilevel Implementation = ' + ' Y = ' ' = 3 + ' ' + Y = Y + ' ' + ' ' 6 = + ' ' + ' 3 = + + ' ' ' literals 33 gates Ineffective use of don't cares = ' Y + ' ' = ' + Y + ' 6 = + + ' + ' ' No. -3 ombinational Logic Word Problems Logical Function Unit tatement of the Problem: 3 control inputs:,, data inputs:, output: F No. -

28 ombinational Logic Word Problems Logical Function Unit Formulate as a truth table hoose implementation technology -variable K-map espresso multiplexor implementation TTL packages: x -input NN x -input NOR x -input OR 8: MU + V E N 3 Q O F 6 7 No. - ombinational Logic Word Problems Logical Function Unit Follow implementation procedure = = F = ' ' ' + ' ' + ' ' + ' gates, inverters lso four packages: x 3-input NN x -input NN lternative: 3 x -bit ROM single package No. -6

29 evice - st evice - nd evice - 3rd evice - th evice evice R O R O evice R O Priority Multiplexer R O evice OUTPUT The Priority Mux connects a device output (O, O, O, O) to the output line (OUTPUT) based on priorities. Each device has a request line (R, R, R, R) that is asserted when the system output line is requested by that device. The Mux must return a signal (,,, ) to each device indicating whether the request was accepted. These signals should be asserted only if a request has been received from the device and the device output has been connected to the system output. No Level Priority Encoder Enable 7 Inactive 6 Inputs 7-LPE 3 M L The output of this Priority Encoder represent the binary code of the highest asserted input at any point in time. The Inactive output indicates when no input is asserted. No. -8

30 hapter Review Non-imple Gate Logic uilding locks: PLs/PLs Multiplexers/electers ecoders ROMs Tri-state, Open ollector ombinational Word Problems: Understand the Problem Formulate in terms of a Truth Table hoose implementation technology Implement by following the design procedure No. -9

Chapter # 4: Programmable and Steering Logic

Chapter # 4: Programmable and Steering Logic hapter Overview PLs and PLs hapter # : Programmable and teering Logic Non-Gate Logic witch Logic Multiplexers/electers and ecoders Tri-tate Gates/Open ollector Gates ROM ombinational Logic esign Problems