Ch 4. Combinational Logic Technologies. IV - Combinational Logic Technologies Contemporary Logic Design 1

Transcription

1 h 4. ombinational Logic Technologies Technologies ontemporary Logic Design 1

2 History - From Switches to Integrated ircuits The underlying implementation technologies for digital systems Technologies ontemporary Logic Design 2

3 Packaged Logic, onfigurability, and Programmable Logic Standard parts Integrated circuits that contain small number of simple logic gates widely used ROM and PL/PL ROM fixed array of ones and zeros Programmable logic array (PL), Programmable array logic (PL) n array of fixed logic gates, arranged in a standard two-level form such as ND/OR pplication-specific Integrated ircuit (SI) Gate array / Standard cells Field-Programmable Gate rray (FPG) Technologies ontemporary Logic Design 3

4 Packaged Logic, onfigurability, and Programmable Logic (cont'd) Historical development of components Technologies ontemporary Logic Design 4

5 Technology Metrics Gate delay The time delay from an input change to an output change t(5% output final value) - t(5% of input final value) Degree of integration The chip area and number of chip packages required to implement a given function in a technology Power dissipation Power consumed as gates perform their logic functions Noise margin The maximum voltage that can be added to or subtracted from the logic voltages carried on wires and still have the circuit interpret the voltage as the correct logic value omponent cost Technologies ontemporary Logic Design 5

6 Technology Metrics (cont d) Fan-out The number of gate inputs to which a given gate output can be connected without exceeding electrical limitations Driving capability The speed of communications between packaged components onfigurability Technologies ontemporary Logic Design 6

7 asic Logic omponents - Fixed Logic ell-based design Designers pick and choose gates in a given standard cell library for logic functions they want to implement. NND, NOR, XOR, DDER, MUX, SSI and MSI (Small and Medium Scale Integrated ircuit) TTL: a family of packaged logic components Example: TTL 74 Standard cell library for modern SI provides the same kinds of logic functions as those TTL standard catalog contains. Technologies ontemporary Logic Design 7

8 Fixed Logic (cont d) ombinational logic implementation Pick logic packages and wire them Make Package/ell ounts minimal out 744 Technologies ontemporary Logic Design 8

9 asic Logic omponents (cont d) -Look-Up Tables Look-up table approach Storing the output value of a function for each input combination in a table Using the current input value as an index to look-up what the output should be To change the function, simply change the values stored in the table, not change any wiring Less sensitive to the complexity of the function Example If the input =, =1, and =, the corresponding index (address) of the table = 1 and the value of the entry = 1. Thus, the output F=, F1=1, F2=, F3= Index Output FF1F2F Storing the outputs at each entry Technologies in a table device ontemporary Logic Design 9

10 Look-Up Tables (cont d) ROM (Read-Only Memory) an array of values intended to be read many times but only written once We can program the output of a truth table directly into a ROM ddress: index of the array ROM Inputs are used to index a row of the array n-1 Dm-1 The value of the corresponding row are read out as the values of the outputs Each additional input bit doubles the size of the memory array Good to implement a complicated function that is difficult to simplify using the standard methods or change often the function. Variants Programmable ROM (PROM) Erasable PROM (EPROM) Electrically erasable PROM (EEPROM) D (2^n words with m-bit width) Technologies ontemporary Logic Design 1

11 Look-Up Tables (cont d) Internal organization of a ROM Each row of the array is called a word and is selected by the control inputs, which are called the address. The number of columns in the array is called the bit-width or word size. Similar to a PL structure but with a fully decoded ND array completely flexible OR array (unlike PL) n address lines inputs decoder 2 n word lines Memory array (2 n words by m bits) outputs m data lines Technologies ontemporary Logic Design 11

12 Look-Up Tables (cont d) Two dimensional array of 1s and s entry (row) is called a "word" width of row = word-size index is called an "address" address is input selected word is output n word lines (only one is active decoder is just right for this) decoder i j word[i] = 11 word[j] = 11 internal organization n-1 ddress bit lines (normally pulled to 1 through resistor selectively connected to by word line controlled switches) Technologies ontemporary Logic Design 12

13 Look-Up Tables (cont d) ombinational logic implementation (two-level canonical form) using a ROM F = ' ' + ' ' + ' F1 = ' ' + ' ' + F2 = ' ' ' + ' ' + ' ' F3 = ' + ' ' + ' F F1 F2 F truth table ROM 8 words x 4 bits/word address FF1F2F3 outputs block diagram Technologies ontemporary Logic Design 13

14 asic Logic omponents (cont d) - Multiplexer/Selector Multiplexer/Selector (MUX) Sets its single output to the same value as one of its inputs under the direction of its control inputs. 2 n data inputs, n control inputs (called "selects"), 1 output used to connect 2 n input points to a single output point control signal pattern forms binary index of input connected to output Functional description I I1 I2 I3 S1 S Z Input : Output : Function : I S Z Z j i = {,1} where j =,1,..., 2 = {,1} where i =,1,..., n -1 = {,1} = I where j = S j n 1 = i= S i 2 i n -1 Technologies ontemporary Logic Design 14

15 Multiplexer/Selector (cont d) Truth table of MUX 2:1 MUX Z = ' I + I 1 functional form logical form Z I 1 I 1 two alternative forms for a 2:1 Mux truth table I 1 I Z Technologies ontemporary Logic Design 15

16 Multiplexer/Selector (cont d) oolean equation of MUX 2:1 mux: Z = 'I + I1 4:1 mux: Z = ''I + 'I1 + 'I2 + I3 8:1 mux: Z = '''I + ''I1 + ''I2 + 'I3 + ''I4 + 'I5 + 'I6 + I7 I I1 In general: 2:1 mux Z = Z n 2 1 k = m k I k in minterm shorthand form for a 2 n :1 Mux I I1 I2 I3 4:1 mux Z I I1 I2 I3 I4 I5 I6 I7 8:1 mux Z Technologies ontemporary Logic Design 16

17 Multiplexer/Selector (cont d) Gate Level Implementation of MUX 2:1 mux 4:1 mux Technologies ontemporary Logic Design 17

18 Multiplexer/Selector (cont d) - Mux and Demux Switch implementation of multiplexers and demultiplexers can be composed to make arbitrary size switching networks used to implement multiple-source/multiple-destination interconnections Y Y Z Z Demux Mux Demux Mux Technologies ontemporary Logic Design 18

19 Mux and Demux (cont d) Uses of multiplexers/demultiplexers in multi-point connections 1 1 Sa MUX MUX Sb multiple input sources Sum Ss DEMUX multiple output destinations S S1 Technologies ontemporary Logic Design 19

20 Multiplexer/Selector (cont d) - ascading Multiplexers Large multiplexers can be made by cascading smaller ones I I1 I2 I3 I4 I5 I6 I7 4:1 mux 4:1 mux 2:1 mux control signals and simultaneously choose one of I, I1, I2, I3 and one of I4, I5, I6, I7 control signal chooses which of the upper or lower mux's output to gate to Z 8:1 mux Z 2:1 mux 2:1 mux 2:1 mux 2:1 mux alternative implementation Technologies ontemporary Logic Design 2 I I1 I2 I3 I4 I5 I6 I7 4:1 mux 8:1 mux Z

21 Multiplexer/Selector (cont d) - Multiplexers as a Logic uilding lock 2 n :1 multiplexer can implement any function of n variables with the variables used as control inputs and the data inputs tied to or 1 in essence, a lookup table Example: F(,,) = m + m2 + m6 + m7 = ''' + '' + ' + = '''(1) + ''() + ''(1) + '() + ''() + '() + '(1) + (1) :1 MUX S2 S1 S F F = '''I + ''I 1 + ''I 2 + 'I 3 + ''I 4 + 'I 5 + 'I 6 + I 7 Technologies ontemporary Logic Design 21

22 Multiplexers as a Logic uilding lock (cont d) 2 n-1 :1 multiplexer can implement any function of n variables with n-1 variables used as control inputs and the data inputs tied to the last variable or its complement Example: F(,,) = m + m2 + m6 + m7 = ''' + '' + ' + = ''(') + '(') + '() + (1) :1 MUX S2 S1 S F F ' ' ' ' :1 MUX S1 S 1 F Technologies ontemporary Logic Design 22

23 Multiplexers as a Logic uilding lock (cont d) Generalization n-1 mux control variables single mux data variable Example: G(,,,D) can be realized by an 8:1 MUX choose,, as control variables I I 1... I n-1 I n F D G I n I n ' :1 MUX S2 S1 S four possible configurations of truth table rows can be expressed as a function of I n D Technologies ontemporary Logic Design 23 1 D 1 D' D D 1 D 1 D D D D

24 asic Logic omponents (cont'd) - Demultiplexer/Decoder Decoders/demultiplexers single data input, n control inputs, 2 n outputs control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable (G) Functional description O Input : G = {,1} G Decoder /Demux Output : S O i j = {,1} = {,1} where i =,1,..., n -1 where j =,1,..., 2 n -1 S1 S O2 n-1 Function : O j = 1 where j = S otherwise = n 1 i= S i 2 i Technologies ontemporary Logic Design 24

25 Demultiplexer/Decoder (cont d) oolean equation of Decoder/Demux i= n General form for n-selects: = = m j refers to minterm = = 1 G where j S S O j G m j i= otherwise n = 1 n = 2 n = 3 1:2 Decoder: O = G S O1 = G S 3:8 Decoder: O = G S2 S1 S O1 = G S2 S1 S O2 = G S2 S1 S O3 = G S2 S1 S O4 = G S2 S1 S O5 = G S2 S1 S O6 = G S2 S1 S O7 = G S2 S1 S 2:4 Decoder: O = G S1 S O1 = G S1 S O2 = G S1 S O3 = G S1 S Technologies ontemporary Logic Design 25 i 2 i

26 Demultiplexer/Decoder (cont d) Gate level implementation of Demux 1:2 decoders active-high enable G O S 2:4 decoders O1 active-low enable G S O O1 G O G O active-high enable O1 active-low enable O1 O2 O2 O3 O3 S1 Technologies S S1 S ontemporary Logic Design 26

27 Demultiplexer/Decoder (cont d) Demux as a general-purpose building block n:2 n decoder can implement any function of n variables with the variables used as control inputs the enable inputs tied to 1 and the appropriate minterms summed to form the function :8 DE S2 S1 S ''' '' '' ' '' ' ' demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) Technologies ontemporary Logic Design 27

28 Demultiplexer/Decoder (cont d) Demux as a general-purpose building block F1 = ''D + ''D + D F2 = 'D' + F3 = (' + ' + ' + D') Enable 4:16 DE '''D' 1 '''D 2 ''D' 3 ''D 4 ''D' 5 ''D 6 'D' 7 'D 8 ''D' 9 ''D 1 'D' 11 'D 12 'D' 13 'D 14 D' 15 D F3 F1 F2 D Technologies ontemporary Logic Design 28

29 Demultiplexer/Decoder (cont d) ascading decoders 5:32 decoder 1x2:4 decoder 4x3:8 decoders F 2:4 DE S1 S '''D'E' 1 2 3:8 DE S2 S1 S 1 2 3:8 DE DE S2 S1 S 1 2 ''DE' 3:8 DE S2 S1 S ''D'E' 1 2 3:8 DE 'DE S2 S1 S D E D E Technologies ontemporary Logic Design 29

30 asic Logic omponents (cont'd) - Programmable Logic rray Pre-fabricated building block of many ND/OR gates actually NOR or NND "personalized" by making/breaking connections among the gates programmable array block diagram for sum of products form inputs ND array product terms OR array outputs (SOP) Technologies ontemporary Logic Design 3

31 Programmable Logic rray (cont d) - Enabling oncept Shared product terms among outputs example: F = + ' ' F1 = ' + F2 = ' ' + F3 = ' + personality matrix product inputs outputs term F F1 F2 F ' 1 1 ' 1 1 '' input side: 1 = uncomplemented in term = complemented in term = does not participate output side: 1 = term connected to output = no connection to output reuse of terms Technologies ontemporary Logic Design 31

32 Programmable Logic rray (cont d) - efore Programming ll possible connections are available before "programming" in reality, all ND and OR gates are NNDs Technologies ontemporary Logic Design 32

33 Programmable Logic rray (cont d) - fter Programming Unwanted connections are "blown" fuse (normally connected, break unwanted ones) anti-fuse (normally disconnected, make wanted connections) memory cell or 1 can be stored indicating whether there is to be a connection or not. ' ' '' F1 F2 F3 Technologies ontemporary Logic Design 33 F

34 Programmable Logic rray (cont d) - lternate Representation for High Fan-in Structures Short-hand notation so we don't have to draw all the wires signifies a connection is present and perpendicular signal is an input to gate D notation for implementing F = + ' ' F1 = D' + ' D '' D' 'D +'' D'+'D Technologies ontemporary Logic Design 34

35 Programmable Logic rray (cont d) - Example Multiple functions of,, F1 = F2 = + + F3 = ' ' ' F4 = ' + ' + ' F5 = xor xor F6 = xnor xnor F1F2F3F4F5F ''' '' '' Technologies ontemporary Logic Design 35 full decoder as for memory address bits stored in memory F1 F2 F3 F4 F5 F6 ' '' ' '

36 asic Logic omponents (cont'd) -PLsand PLs Programmable logic array (PL) what we've seen so far unconstrained fully-general ND and OR arrays Programmable array logic (PL) constrained topology of the OR array innovation by Monolithic Memories faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms Technologies ontemporary Logic Design 36

37 PLs and PLs (cont'd) - PLs and PLs: Design Example D to Gray code converter D W X Y Z minimized functions: W = + D + X = ' Y = + Z = '''D + D + D' + 'D' D X X 1 1 X X 1 X X K-map for W D X X 1 1 X X 1 1 X X K-map for Y Technologies ontemporary Logic Design 37 D D D X X X X X X K-map for X D X X 1 X X 1 X X K-map for Z D D

38 PLs and PLs: Design Example (cont d) ode converter: programmed PL D D ' minimized functions: W = + D + X = ' Y = + Z = '''D + D + D' + 'D' not a particularly good candidate for PL implementation since no terms are shared among outputs '''D D D' D' however, much more compact and regular implementation when compared with discrete ND and OR gates W X Y Z Technologies ontemporary Logic Design 38

39 PLs and PLs: Design Example (cont d) ode converter: programmed PL 4 product terms per each OR gate D D ' '''D D D' 'D' W X Y Z Technologies ontemporary Logic Design 39

40 PLs and PLs: Design Example (cont d) ode converter: NND gate implementation loss or regularity, harder to understand harder to make changes D W X D D D D Z Y Technologies ontemporary Logic Design 4

41 PLs and PLs (cont'd) - PLs and PLs: nother Design Example Magnitude comparator Input: Output:, D where,,, D = {,1} EQ, NE, LT, GT = {,1} 1 when = D Function: EQ = otherwise 1 when D NE = otherwise 1 when < D LT = otherwise 1 when > D GT = otherwise D EQ NE LT GT Technologies ontemporary Logic Design 41

42 PLs and PLs: nother Design Example (cont d) D D minimized functions: K-map for EQ D K-map for NE D EQ = D + D + D + D NE = + + D + D LT = + D + D GT = + + D D D D D K-map for L T K-map for GT Technologies ontemporary Logic Design 42

43 PLs and PLs: nother Design Example (cont d) D '''D' ''D D 'D' ' ' 'D D' ''D 'D 'D' EQ NE LT GT Technologies ontemporary Logic Design 43

44 asic Logic omponents (cont'd) - Multiplexer-ased FPG ctel logic module S O S S 1 D D 1 D 2 D 3 Example using a logic module S O ND Y=(S +S 1 ) (S O D +S O D 1 ) +(S +S 1 )(S O D 2 +S O D 3 ) Y=(+) ( +) +(+)(S O D 2 +S O D 3 ) Y= D 2 D 3 S O Technologies ontemporary Logic Design 44

45 asic Logic omponents (cont'd) - Look-Up Table ased FPG Simplified basic building block of FPG Xilinx onfigurable Logic lock (L) Ref.: IEEE TRNSTIONS ON INSTRUMENTTION ND MESUREMENT, VOL. 52, NO. 5, OTOER 23 Technologies ontemporary Logic Design 45

46 Two-Level and Multilevel Logic - Regular Logic Structures for Two-Level Logic ROM full ND plane, general OR plane cheap (high-volume component) can implement any function of n inputs medium speed PL programmable ND plane, fixed OR plane intermediate cost can implement functions limited by number of terms high speed (only one programmable plane that is much smaller than ROM's decoder) PL programmable ND and OR planes most expensive (most complex in design, need more sophisticated tools) can implement any function up to a product term limit slow (two programmable planes) Technologies ontemporary Logic Design 46

47 Regular Logic Structures for Two-Level Logic (cont d) -ROM vs. PL ROM approach advantageous when design time is short (no need to minimize output functions) most input combinations are needed (e.g., code converters) little sharing of product terms among output functions ROM problems size doubles for each additional input can't exploit don't cares PL approach advantageous when design tools are available for multi-output minimization there are relatively few unique minterm combinations many minterms are shared among the output functions PL problems constrained fan-ins on OR plane Technologies ontemporary Logic Design 47

48 Two-Level and Multilevel Logic (cont d) - Regular Logic Structures for Multilevel Logic Difficult to devise a regular structure for arbitrary connections between a large set of different types of gates efficiency/speed concerns for such a structure FPG: just such programmable multi-level structures programmable multiplexers for wiring lookup tables for logic functions (programming fills in the table) multi-purpose cells (utilization is the big issue) Technologies ontemporary Logic Design 48

49 Regular Logic Structures for Multilevel Logic (cont d) Using multiple levels of PLs/PLs/ROMs output intermediate result make it an input to be used in further logic Example: Full dder oolean equations Sum = in + in + in + in out = + in + in oolean equations for feedback PL implementation X = +, Y= Sum = X in + X in out = X in + Y PL Technologies ontemporary Logic Design 49 Sum out X Y

50 Two-level and Multilevel Logic (cont'd) - 7-Segment Display Decoder Understanding the problem: input is a 4 bit D digit output is the control signals for the display 4 inputs,,, D 7 outputs ~ 6 7-Segment display D-to-7-segment control signal decoder segment display D lock Diagram Technologies ontemporary Logic Design 5

51 7-Segment Display Decoder (cont d) Truth table Formulate the problem in terms of a truth table D hoose implementation target: if ROM, we are done x 11xx x x x x x x x x x x x x x x don't cares imply PL/PL may be attractive Follow implementation procedure: hand reduced K-maps espresso Technologies ontemporary Logic Design 51

52 7-Segment Display Decoder (cont d) D X 1 D X 1 D X X X X 1 1 X X D X X X 1 X X D X X X 1 X X D K-map for K-map for 1 K-map for 2 D D D D X 1 1 X X 1 1 X X 1 X X 1 1 X X D X X X 1 1 X X D X 1 X X 1 X X D X 1 1 X X 1 1 X X D K-map for 3 K-map for 4 K-map for 5 K-map for 6 = + D + + ' D' 1 = ' D' + D + ' 2 = + ' + D 14 Unique Product Terms 3 = ' D' + D' + ' D + ' 4 = ' D' + D' 5 = + ' D' + D' + ' 6 = + D' + ' + ' Technologies ontemporary Logic Design 52

53 7-Segment Display Decoder (cont d) 16H8PL (1 external inputs, 6 feedback inputs 8 outputs) 1 First fuse numbers Increment an Implement the function Technologies Note: Fuse number = first fuse number + increment ontemporary Logic Design 53 12

54 7-Segment Display Decoder (cont d) Increment H8PL (14 inputs, 8 outputs, but only two 4-input product terms can be computed.) First fuse numbers annot Implement the function Note: Fuse number = first fuse number + increment Technologies ontemporary Logic Design 54

55 7-Segment Display Decoder (cont d) D (espresso) input.i 4.o 7.ilb a b c d.ob c c1 c2 c3 c4 c5 c6.p e D (espresso) output.i 4.o 7.ilb a b c d.ob c c1 c2 c3 c4 c5 c6.p e = ' D + D + ' D' + D' + 1 = ' D + ' D' + D + ' D' 2 = ' D + ' D + ' D' + D + D' 3 = ' D + ' D + ' D' + D' 4 = ' D' + D' 5 = ' D + ' D' + + D' 6 = ' + ' + D' + 63 Literals, 2 Gates 9 Unique Product Terms! The results are more complex than those of manual method. However, #unique product terms has been reduced 15->9 Technologies ontemporary Logic Design 55

56 7-Segment Display Decoder (cont d) - PL Implementation Technologies ontemporary Logic Design 56

57 7-Segment Display Decoder (cont d) - Multilevel Implementation X = ' + D' Y = ' ' = 3 + ' X' + D Y 1 = Y + ' 5' + ' D' 6 2 = 5 + ' ' D + ' D 3 = 4 + D 5 + ' ' X' 52 literals 33 gates Ineffective use of don't cares 4 = D' Y + ' D' 5 = ' 4 + Y + ' X 6 = ' 5 + ' ' Technologies ontemporary Logic Design 57

58 Non-Gate Logic - Tri-State Outputs The Third State Logic States: "", "1" Don't are/don't Know State: "X" (must be some value in real circuit!) Third State: "Z : high impedance: infinite resistance, no connection Tri-state gates: output values are "", "1", and "Z F additional input: output enable (OE) When OE is high, this gate is a non-inverting "buffer" OE When OE is low, it is as though the gate was disconnected from the output! This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time Technologies ontemporary Logic Design 58

59 Tri-State Outputs (cont d) Tri-state gates (cont d) Truth table X 1 OE 1 1 F Z 1 Non-inverting buffer's timing waveform OE F 1 OE F "Z" "Z" Technologies ontemporary Logic Design 59

60 Tri-State Outputs (cont d) Using tri-state gates to implement an economical multiplexer: When SelectInput is asserted high, Input1 is connected to F When SelectInput is driven low, Input is connected to F This is essentially a 2:1 Mux Input Input 1 OE F OE SelectInput Technologies ontemporary Logic Design 6

61 Tri-State Outputs (cont d) lternative Tri-state Fragment Switch Level Implementation of tri-state gate Input F 1 OE Input 1 OE OE I F SelectInput ctive low tri-state enables plus inverting tri-state buffers Technologies ontemporary Logic Design 61

62 Tri-State Outputs (cont d) 4:1 Multiplexer, Revisited \EN S1 S G 1 1 2G 2 2 1Y3 1Y1 1Y2 1Y 2Y3 2Y1 2Y2 2Y D3 D2 D1 D Decoder + 4 tri-state Gates Technologies ontemporary Logic Design 62

63 Tri-State Outputs (cont d) - Output Enable Signal of ROM 2764 EPROM 8K x VPP PGM O7 9 O6 8 O5 7 O4 6 O3 5 O2 4 O1 3 O 2 1 S OE 16K x 16 Subsystem 13 /OE 12: D15:D8 D7:D 2764 VPP + PGM S OE 2764 VPP PGM S OE O7 O6 O5 O4 O3 O2 O1 O U3 O7 O6 O5 O4 O3 O2 O1 O U VPP PGM S OE 2764 VPP PGM S OE O7 O6 O5 O4 O3 O2 O1 O U2 O7 O6 O5 O4 O3 O2 O1 O U Technologies ontemporary Logic Design 63

64 Non-Gate Logic (cont'd) - Open-ollector Logic Open ollector another way to connect multiple gates to the same output wire The gate only has the ability to pull its output low; it cannot actively drive the wire high this is done by pulling the wire up to a logic 1 voltage through a resistor Switch representation of an O NND +5 V When =1 and =1, equivalent circuit of O-NND: Open-collector NND gate Pull-up resistor V F VFRrRrlim (=+ (Ra+Rb) Rr +5 V V Technologies ontemporary Logic Design 64

65 Open-ollector Logic (cont d) Example: O-NNDs in wired-nd configuration D + F If and are "1", output is actively pulled low if and D are "1", output is actively pulled low if one gate is low, the other high, then low wins if both gates are "1", the output floats, pulled high by resistor Hence, the two NND functions are ND'd together! Technologies ontemporary Logic Design 65

66 Open-ollector Logic (cont d) 4:1 Multiplexer \EN 1 G 139 S1 3 S 2 Y3 Y2 Y1 Y \I3 OR +5V F \I2 OR \I1 OR \I OR Decoder + 4 Open ollector Gates Technologies ontemporary Logic Design 66

67 Summary Theme: How to construct digital systems with more complex logic building blocks than discrete gates Overview of the different classes of basic components: Fixed logic Look-up table based logic (ROM) Steering logic (Mux, Demux) PL, PL FPG Non-gate logic Enables efficient multiplexing of large numbers of signals Tristate Open-collector Technologies ontemporary Logic Design 67