Programmable Logic Devices

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1 Programmable Logic Devices Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College

2 PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches Main types of PLDs PLA PAL ROM CPLD FPGA Custom chips: standard cells, sea of gates

3 ROM, PAL and PLA Configurations Mohd Anvar Inputs Fixed AND array (decoder) Programmable Connections Programmable OR array Outputs (a) Programmable read-only memory (PROM) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable array logic (PAL) device Inputs Programmable Connections Programmable AND array Programmable Connections Programmable OR array Outputs (c) Programmable logic array (PLA) device

4 Programmable Logic Array (PLA) Use to implement circuits in SOP form x x 2 x n The connections in the AND plane are programmable Input buffers and inverters x x x n x n The connections in the OR plane are programmable AND plane P P k OR plane f f m

5 Gate Level Version of PLA x x 2 x 3 f = x x 2 +x x 3 '+x 'x 2 'x 3 P Programmable connections OR plane f 2 = x x 2 +x 'x 2 'x 3 +x x 3 P 2 P 3 P 4 AND plane f f 2

6 Customary Schematic of a PLA x x 2 x 3 f = x x 2 +x x 3 '+x 'x 2 'x 3 f 2 = x x 2 +x 'x 2 'x 3 +x x 3 P OR plane P 2 P 3 P 4 x marks the connections left in place after programming AND plane f f 2

7 PLA Logic Implementation Key to Success: Shared Product Terms Example: Equations F = A + B C F = A C + A B F2 = B C + A B F3 = B C + A Product t erm A B B C A C B C A Personality Matrix Inputs A - - B - - C - - F Outputs F F 2 F 3 Reuse of t erms Input Side: = asserted in term = negated in term - = does not participate Output Side: = term connected to output = no connection to output

8 PLA Logic Implementation Example Continued - Unprogrammed device A B C All possible connections are available before programming F F F2 F3

9 PLA Logic Implementation Example Continued - Programmed part A B C Unwanted connections are "blown" AB BC AC BC A Note: some array structures work by making connections rather than breaking them F F F2 F3

10 PLA Logic Implementation Alternative representation for high fan-in structures Unprogrammed device Short-hand notation so we don't have to draw all the wires! X at junction indicates a connection Notation for implementing F = A B + A B F = C D + C D A B C D Programmed device AB AB CD CD AB+AB CD+CD

11 PLA Logic Implementation Design Example A B C Multiple functions of A, B, C F = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A B C F6 = A B C ABC A B C A B C ABC ABC ABC ABC ABC ABC ABC F F2 F3 F4 F5 F6

12 Programmable Array Logic (PAL) Also used to implement circuits in SOP form x x 2 x n The connections in the AND plane are programmable Input buffers and inverters x x x n x n fixed connections The connections in the OR plane are NOT programmable AND plane P P k OR plane f f m

13 Example Schematic of a PAL x x 2 x 3 f = x x 2 x 3 '+x 'x 2 x 3 f 2 = x 'x 2 '+x x 2 x 3 P P 2 f P 3 P 4 f 2 AND plane

14 PAL Logic Implementation Design Example: BCD to Gray Code Converter A B Truth Table C D W X X X X X X Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D X X X X X X X Y X X X X X X Z X X X X X X AB A CD X C X X X X X B K-map for W AB A CD X C X X X X X B K-map for Y K-maps D D AB A CD X C X X X X X B K-map for X AB A CD X C X X X X X B K-map for Z D D

15 PAL Logic Implementation Programmed PAL: A B C D Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D 4 product terms per each OR gate A BD BC BC B C A B C D BCD AD BCD W X Y Z

16 PAL Logic Implementation Code Converter Discrete Gate Implementation 4 SSI Packages vs. PLA/PAL Package! : 744 hex inverters 2,5: 74 quad 2-input NAND 3: 74 t ri 3-input NAND 4: 742 dual 4-input NAND B C C A D D W X Y B B B B C C A D 2 2 Z D A C B C B D D A B Mohd Anvar

17 PLA Logic Implementation Another Example: Magnitude Comparator A B C D A AB CD AB A CD ABCD ABCD C B K-map for EQ AB A CD D C B K-map for NE AB A CD D ABCD ABCD AC AC BD BD ABD BCD C D C D ABC BCD B K-map for L T B K-map for GT EQ NE LT GT

18 Comparing PALs and PLAs PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs PALs are simpler to manufacture, cheaper, and faster (better performance) PALs also often have extra circuitry connected to the output of each OR gate The OR gate plus this circuitry is called a macrocell

19 OR gate from PAL Macrocell Select Enable f D Q Clock Flip-flop back to AND plane

20 Combinational and Sequential PLDS 6L4 PAL Combinational Logic Up to 6 inputs 32 bit & bit-bar lines Up to 4 outputs Up to 7 product terms per output product term/output for tri-state control Input, Output, Bi-driectional bus (on per output basis) Note fuse numbers (early technology)

21

22

23 6R4 PAL Sequential Logic 6 inputs (counting feedback into array from DFFs) Again 32 bit & bit-bar lines 4 outputs (Q outputs from 8 DFFs) Up to 64 product terms The flip-flops are all controlled by a common clock which is tied directly to pin on the device. pin, which is used as a dedicated input for the output enable of the flip-flops.

24

25 Simple PLDS PLD 22V Combinational/Sequential Logic PAL devices are most commonly used SPLD Eg: PAL 22v II input pins that feed the AND plane and an additional input that can serve as Clock input The OR gates are of variable size, ranges from 8 to 6 inputs From 8 to 6 product terms per output Each out put pin has tristate buffer,which allows the pin to optionally be used as input pin Introduction of Macro cell-the circuitry between OR gate and an out put in PAL Combinational and/or sequential logic in PLD

26 Complex Programmable Logic Devices (CPLD) SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms Combined number of inputs + outputs < 32 or so CPLDs contain multiple circuit blocks on a single chip Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an interconnection network that is programmable Each block is connected to an I/O block as well

27 Structure of a CPLD I/O block PAL-like block PAL-like block I/O block Interconnection wires I/O block PAL-like block PAL-like block I/O block

28 Internal Structure of a PAL-like Block Includes macrocells Usually about 6 each Fixed OR planes OR gates have fan-in between 5-2 PAL-like block PAL-like block XOR gates provide negation ability XOR has a control input D Q D Q D Q

29 More on PAL-like Blocks CPLD pins are provided to control XOR, MUX, and tri-state gates When tri-state gate is disabled, the corresponding output pin can be used as an input pin The associated PAL-like block is then useless The AND plane and interconnection network are programmable Commercial CPLDs have between 2- PAL-like blocks

30 Example CPLD Use a CPLD to implement the function f = x x 3 x 6 ' + x x 4 x 5 x 6 ' + x 2 x 3 x 7 + x 2 x 4 x 5 x 7 (from interconnection wires) x x 2 x 3 x 4 x 5 x 6 x 7 unused PAL-like block f D Q

31 The Xilinx 95-series CPLD The internal PLDs are called Configurable Functional Blocks (FBs or CFBs) Each FB has 36 inputs and 8 Macrocells (effectively a 36V8 ) Each CLPD is packaged in a plastic-leaded chip carrier (PLCC) The number of I/O pins are much less than the total number of Macrocells in family of devices

32 Xinlinx CPLDs

33 Architecture of Xilinx 95-family CPLD 36 Signal pins 8 outputs Global Clock Global set/reset Global 3 state control 8 Output enable signals

34 XC95 I/O Block

35

36

37 FPGA SPLDs and CPLDs are relatively small and useful for simple logic devices Up to about 2 gates Field Programmable Gate Arrays (FPGA) can handle larger circuits No AND/OR planes Provide logic blocks, I/O blocks, and interconnection wires and switches Logic blocks provide functionality Interconnection switches allow logic blocks to be connected to each other and to the I/O pins

38 FPGA Structure Input/Output Block IOB IOB IOB IOB Configurable Logic Block IOB IOB IOB IOB CLB CLB CLB CLB SM SM SM CLB CLB CLB CLB SM SM SM CLB CLB CLB CLB SM SM SM CLB CLB CLB CLB IOB IOB IOB IOB Switch Matrix IOB IOB IOB IOB

39 FPGA CLB Structure

40 LUTs Logic blocks are implemented using a lookup table (LUT) Small number of inputs, one output Contains storage cells that can be loaded with the desired values A 2 input LUT uses 3 MUXes to implement any desired function of 2 variables Shannon's expansion at work! x x 2 / / / / f

41 Example 2 Input LUT x x 2 f f = x 'x 2 ' + x x 2, or using Shannon's expansion: f = x '(x 2 ') + x (x 2 ) = x '(x 2 '() + x 2 ()) + x (x 2 '() + x 2 ()) x f x 2

42 3 Input LUT 7 2x MUXes and 8 storage cells are required Commercial LUTs have 4-5 inputs, and 6-32 storage cells x x 2 x 3 / / / / / / / / f

43 Programming an FPGA LUTs contain volatile storage cells None of the other PLD technologies are volatile FPGA storage cells are loaded via a PROM when power is first applied The UP2 Education Board by Altera contains a JTAG port, a MAX 7 CPLD, and a FLEX K FPGA The MAX 7 CPLD chip is EPM728SLC84-7 EPM7 MAX 7 family; 28 macrocells; LC84 84 pin PLCC package; 7 speed grade

44 Example FPGA Use an FPGA with 2 input LUTS to implement the function f = x x 2 + x 2 'x x 3 3 f f = x x 2 x f 2 = x 2 'x 3 x f = f + f x 2 2 x 2 x 2 f f x 2 3 f f 2 f

45 Another Example FPGA Use an FPGA with 2 input LUTS to implement the function f = x x 3 x 6 ' + x x 4 x 5 x 6 ' + x 2 x 3 x 7 + x 2 x 4 x 5 x 7 Fan-in of expression is too large for FPGA (this was simple to do in a CPLD) Factor f to get sub-expressions with max fan-in = 2 f = x x 6 '(x 3 + x 4 x 5 ) + x 2 x 7 (x 3 + x 4 x 5 ) = (x x 6 ' + x 2 x 7 )(x 3 + x 4 x 5 ) Could use Shannon's expansion instead Goal is to build expressions out of 2-input LUTs

46 FPGA Implementation f = (x x 6 ' + x 2 x 7 )(x 3 + x 4 x 5 ) x 4 x 5 x 3 f x x 6 x x 6 A x 4 x 5 C x 3 C E x 2 x 7 x 2 x 7 B A B D D E f

47 ALTERA FLEX K

48 FLEX K Logic array block

49 FLEX K Embedded Array block

50 Xilinx XC4-CLB

51 XC4 -IOB

52 Wish you all the best.. Thank you

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