Chapter 7: Digital Components. Oregon State University School of Electrical Engineering and Computer Science. Review basic digital design concepts:

Transcription

1 hapter 7: igital omponents Prof. en Lee Oregon tate University chool of Electrical Engineering and omputer cience hapter Goals Review basic digital design concepts: esigning basic digital components using logic gates and memory elements: ecoders/encoders, multiplexers, counters, registers, memories, and rithmetic and Logic Units (LUs). Understand that these digital components represent fundamental building blocks for any digital system, especially processor (microarchitecture) design: Modular design. hapter 7: igital omponents 2

2 ontents 7. Introduction 7.2 Multiplexers 7.3 ecoders 7.4 Elements 7.5 Registers 7.6 Register File asic LU (see hapter 9) hapter 7: igital omponents 3 7. Introduction hapter 7: igital omponents 4 2

3 asic igital omponents Multiplexors ecoders/encoders Registers Memories later we will see rithmetic and Logic Units (LUs) Fetch Execute MUXH R MUX Opcode VR Microarchitecture 6 Rd Rr 5 5 Register ddr. Logic 7 7 w w r r in Register File in out out Program IR P ddr Inst/ata Out lignment Unit 7 7 K MUXJ zf R, R+, -R, or R+q q 6 se k 7 or 2 MR P++ se k, k, or Z P+ k NP + MUXK P+ P+ or k MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents Multiplexer hapter 7: igital omponents 6 3

4 Multiplexors Use to choose among multiple input sources. Fetch MUXJ P P++ se k, k, or Z P+ ddr Program Inst/ata Out R, R+, -R, or R+q k + MUXK P+ IR MR NP Execute MUXH Opcode lignment Unit Rd Rr K q k 7 or 2 P+ or k R MUX Register ddr. Logic w w r r in Register File in out out zf se MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents 7 Multiplexors 2 n data inputs, n control inputs, one output. ontrol signal pattern forms binary index of input connected to output. I I MUX I I O O I I O I I O = ' I + I hapter 7: igital omponents O 4

5 Multiplexors (cont.) 2: MUX: O = I + I 4: MUX: O = I + I + I 2 + I 3 : MUX: O = 2 I + 2 I + 2 I I I I I I 7 I I I I 2 I 3 4: mux O I I 2 O I 3 hapter 7: igital omponents 9 ascading Multiplexors Large multiplexers implemented by cascading smaller ones. lternative Implementation I I I 2 I 3 I 4 I 5 I 6 I 7 4: MUX 4: MUX 2: MUX : MUX O I I I 2 I 3 I 4 I 5 I 6 I 7 2: MUX 2: MUX 2: MUX 2: MUX : MUX 4: MUX O 2 2 hapter 7: igital omponents 5

6 7.3 ecoder hapter 7: igital omponents ecoders ingle data input, k control inputs, 2 k outputs. Used to select one of 2 k components: RM cells in memory Registers in register file 2 3-to- 3 4 ecoder ''' '' '' ' '' ' ' hapter 7: igital omponents 2 6

7 2-to-4 ecoder Implementing a 2-to-4 decoder Truth Table E O 3 O 2 O O E O O O 2 O 3 O = E O = E O 2 = E O 3 = E We can also implement active low enable hapter 7: igital omponents Elements hapter 7: igital omponents 4 7

8 Elements i-stable elements used in Program and ata memories Registers Register File Fetch Execute MUXH Opcode 6 Rd Rr 5 5 Program IR P ddr Inst/ata Out lignment Unit K MUXJ R, R+, -R, or R+q q 6 k 7 or 2 MR P++ se k, k, or Z P+ k NP + MUXK P+ P+ or k R MUX Register ddr. Logic w w r r in Register File in out out zf se MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents 5 Element: -R Latch R R hold not allowed R R not allowed hold hapter 7: igital omponents

9 -R Latch Operation =, R= (hold), initially = R =, R= (reset), initially = R!!!! =, R= (set), initially = =, R= (not allowed), initially = R!! R!!!! hapter 7: igital omponents 7 -R Latch with Enable R ircuit Function Table R X X No hange No hange Not allowed Logic ymbol R hapter 7: igital omponents 9

10 Latch ircuit Function Table LK X No hange Logic ymbol hapter 7: igital omponents 9 Negative Edge-Triggered -FF LK ircuit Function Table LK No hange No hange Logic ymbol LK hapter 7: igital omponents 2

11 Negative Edge-Triggered -FF Operation X ( or ) X ( or ) (t-) X ( or ) Master lave LK t t+ hapter 7: igital omponents 2 Positive Edge-Triggered -FF ircuit Function Table LK No hange No hange LK Logic ymbol LK hapter 7: igital omponents 22

12 Edge-Triggered -FF /w Enable ircuit Logic ymbol E E hapter 7: igital omponents Registers hapter 7: igital omponents 24 2

13 Registers Used to temporary hold and separate information Fetch among various parts of the datapath. Program MUXJ P ddr P++ se k, k, or Z P+ + Inst/ata Out R, R+, -R, or R+q k MUXK P+ IR MR NP Execute MUXH Opcode lignment Unit Rd Rr K q k 7 or 2 P+ or k R MUX Register ddr. Logic w w r r in Register File in out out zf se MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents 25 n-bit Register /w Load Enable E set of commonly clocked flip-flops LK ymbol E hapter 7: igital omponents 26 3

14 hift Registers er_in = er_out LK LK = er_out er_in 3 hift Left (down) hift Right (up) hapter 7: igital omponents 27 i-irectional hift Register /w Parallel Load LK L_IN Right (top) ontrol Next Input tate Function 3 2 Hold 3 2 hift right R _IN 3 2 hift left 2 L_IN Load Left (bottom) R_IN hapter 7: igital omponents 2 4

15 7.5 hapter 7: igital omponents 29 Program and ata memories Fetch MUXJ P P++ se k, k, or Z P+ ddr Program Inst/ata Out R, R+, -R, or R+q k + MUXK P+ IR MR NP Execute MUXH Opcode lignment Unit Rd Rr K q k 7 or 2 P+ or k R MUX Register ddr. Logic w w r r in Register File in out out zf se MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents 3 5

16 ell tatic RM (RM) Fast Practically a -FF. Used in Registers and Instruction and ata aches. ynamic RM (RM) Need to be refreshed periodically. Used in Main in out in out RM ell hapter 7: igital omponents 3 RM tructure ata In in(b-) in(b-2) in() ecoder front-end to select one word Not clocked! n- n-to-2 n ecoder In In Out Out In In Out Out In In Out Out 2 n- In Out In Out In Out Write Enable (Write) hip ect WE Output Enable (Read) OE out(b-) out(b-2) out() ata Out hapter 7: igital omponents 32

17 RM Operation: Read in(b-) in(b-2) in() Row ect In X b- X b-2 X Out In Out In Out WE OE X b- X b-2 X out(b-) out(b-2) out() hapter 7: igital omponents 33 RM Operation: Write in(b-) in(b-2) in() Row ect X b- X b-2 X In X b- X b-2 X Out In Out In Out WE OE out(b-) out(b-2) out() hapter 7: igital omponents 34 7

18 uilding Larger Read Write K X RM ddress IN OUT 7 2-to-4 ecoder 2 3 WE OE 64K X RM ddress 256K x RM Using four 64K x RMs IN OUT WE OE 64K X RM ddress IN OUT WE OE 64K X RM ddress IN OUT WE OE hapter 7: igital omponents 35 uilding Wider 256K x RM Using two 256K x RMs K X RM ddress 256K X RM ddress IN OUT IN OUT Write Read WE OE WE OE hapter 7: igital omponents 36

19 7.6 Register File hapter 7: igital omponents 37 Register File torage buffer between LU and Fetch MUXJ P P++ se k, k, or Z P+ ddr Program Inst/ata Out R, R+, -R, or R+q k + MUXK P+ IR MR NP Execute MUXH Opcode lignment Unit Rd Rr K q k 7 or 2 P+ or k R MUX Register ddr. Logic w w r r in Register File in out out zf se MUX ata In ddr MUXF R MUXG MUX LU LU ata ata Out ddress dder R, R+,-R, or R+q P++se k, k, or Z hapter 7: igital omponents 3 9

20 Register File Register Identifiers Read Write ata In in in LK r r w w Read-port, 2 Write-port X-, Y-, & Z-registers R R R 27 E E E ecoder 27 ecoder 27 RF_w RF_w Write signals 27 MUX 27 MUX out out ata Out hapter 7: igital omponents 39 asic LU hapter 7: igital omponents 4 2

21 Full dder x i y i x i y i c i + F c i c i+ c i s i x i y i c i s i c i+ x i y i c i x i y i c i s i c i+ s i s i = x i y i c i c i+ = x i y i + ( x i y i )c i or c i+ = x i y i + ( x i + y i )c i hapter 7: igital omponents 4 n-bit Ripple arry dder x n- y n- x n- y n- x y c n F F F c arry-out available after 2 gds c n s n- s n-2 s x n- y n- x Å y already available c n- ssuming x and y are available at the same time. ased on c i+ =x i y i +(x i +y i )c i Valid result available after 2n gds! s n- um available after 2 gds arry-in available after 2(n-) gds hapter 7: igital omponents 42 2

22 dder/ubtractor With R and a complementor, we can perform a variety of operations: x+y x+y x+y + +y y y + x n- y n- y n- y n-2 y c n F F F c x n- y n- x y c y c result = y c + yc s n- s n-2 s hapter 7: igital omponents 43 ondition odes in REG x n- y n- x n- y n- x y c n F F F c ign-bit () N V orrect Incorrect! orrect Incorrect! s n- s n-2 s Rule for Overflow (V) arry-in, carry-out V N Z No carry-in, no carry out Otherwise, overflow! arry-out it n- arry-in arry-out it n- arry-in hapter 7: igital omponents 44 22

23 uestions? hapter 7: igital omponents 45 23