CHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5.

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1 CHPTER Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F * = S + S = S + S S S S0 C in C 0 dder G 0 C S S S0 dder G C * (Errata: Delete after problem number) = S + S = (S + S ) = (S + ) =S + S, = (S + ) S F C i G S C C in t t S t F C i + G 00: G = 0: G = + 0: G = + : G = S C in Cascade four such stages, connecting the carries. 2

2 9-6.* Two bits : The R, NR, NR and ND are all bitwise operations. The design for one stage remains the same as any other Stages. a) R = 00, NND = 0, NR = 0 NR = ut = S + S + S + S + S b) The above is a simplest expression Logic table S2 S S0 peration Sr 0 v 0 S l ^ i S C i Ri (to stage to right) i i C L Carry to the left C R Carry to the right C Ri (from stage to left) C Rn 0 C Li (from stage to right) C L0 F C out 0 Mux Mux S S 2 0 Mux S 2 F i C Li (to stage to left) 9-8.* 9-9. (a) 00 (b) 0 (c) 00 (d) 000 D M FS MD RW (a) (b) (c) (d) (e) (f) (g) (h) * (a) R5 R4 R5 R5 = (d) R5 R0 R5 = (b) R6 R2 + R4 + R6 = 0 (e) R4 srconstant R4 = (c) R5 R0 R5 = (f) R3 Data in R3 = R3 R3 + R, R3 = 000 R4 R4 R, R4 = 0000 R5 R5 R, R5 = 0000 R R, R = 0 R... R7 = i, D, g, t, l, a, i R R +, R = R6 R6 + R +, R6 = R7 R7 + R +, R7 = 0000 R R7, R = 0000 Unscrambled is Digital 22

3 * a) 64 x 64 = 4096 b) 32 c) 0 to d) to errata : bit 3 as the sign bit makes sense a) 8 bits b) 49 bits = 48 Instruction Register Transfer D M FS MD RW MW PL J R[ 0] R[ 7] R[ 3] x R[ ] MR4 [ [ ]] xxx x xxxx 0 0 x R[ 2] R[ 5] xxx x R[ 3] sl R[ 6] 0 xxx x if R[ 4] = 0 then PC PC + se PC xxx 00 xxx x 0000 x Instruction Register Transfer peration Code DR S S or perand R[ 0] = sr R[ 7] R[ ] MR6 [ [ ]] R[ 2] R[ 5] R[ 3] R[ 4] R[ 3] R[ 4] R[ 2] R[ ] M: 5 - Correct for table specification MD: 3 - Correct for table specification RW:4 - Correct for table specification MW: Correct for table specification PL: Correct for table specification J: 3 - Correct for table specification C: 9 - Correct for table specification FS: The logic gives 0000 for FS for PL = which selects the value on the input to the Function Unit to be evaluated for branches and blocks the value on bit 9 which is otherwise used as C for branches. For PL = 0, the normal bits for FS are passed as required from the op code. Correct. Instruction Code Registers/Memory changed DD R0, R, R SU R3, R4, R R0 = 3 SU R6, R7, R R3 = - DD R0, R0, R R6 = 4 SU R0, R0, R R0 = 2 ST R7, R R0 = -2 LD R7, R M[7] = -2 DI R0, R6, R7 = M[4] DI R3, R6, R0 = 6 R3 = 7 23

4 9-8. R[ 4] R[ 4] R[ 4] V and C are produced by the arithmetic circuit. For the R FS code, S = 0, S0 =. and Cin = 0, giving arithmetic operation dd. For arbitrary contents in R[4], the values of C and V are a function of the sign and value of the contents of R4 and are unpredicable Part pcode VCNZ IL PS D M FS MD RW MM MW (a) E xxxx E 0 0 0xxx 0xxx 0xxx (b) E xxxx INF xxxx E xxx0 INF 0 0 xxxx 0xxx xxxx x (c) E xxx INF 0 0 xxxx 0xxx xxxx x (d) E xxxx INF 0 0 0xxx 0xxx xxxx x Instruction R8 R9 Z E0 R8 RS [ ] 0 E E R9 zfp x 0 E2 E2 R8 srr E3 E3 R9 R E2 E2 R8 srr E3 E3 R9 R E2 E2 R8 srr E3 E3 R9 R E2 E2 R8 srr E3 E3 R9 R E2 E2 R8 srr E3 E3 R9 R E4 E4 RDR [ ] R INF INF Removal of the two decisions on zero operations does not affect the number of states in the state machine diagram. The reason for this is that the same states are required because the datapath of the computer only supports one register transfer per clock cycle. The transfers required by the instruction execution force the state structure. s a consequence, there can be no reduction of the number of clock cycles required to execute the instructions. The new state machine diagram is actually a worst case in terms of execution time for the instruction execution. The two decisions can only improve the execution times. So the analysis suggested is unnecessary. 24

5 9-22. Partial state machine diagram: E0 E E2 INF Problem Solutions Chapter 9 R8 RS [ ] R9 MRS [ [ ]] RDR [ ] R8 + R9, pcode VCNZ IL PS D M FS MD RW MM MW E xxxx E xxxx 0xxx E xxxx E xxx xxxx x xxxx 0 0 E xxxx INF 0 0 0xxx Partial state machine diagram: R8 R8 pcode = 0000 R8 R8 R8 pcode = 0000 E0 E pcode = 0000 RDR [ ] RS [ ] + RS [ ] Z ( pcode = 0000) V ( pcode = 0000) V ( pcode = 0000) E2 Z ( pcode = 0000) E3 pcode = 0000 INF pcode = 0000 PC PC + se D R8 R8 +, Part pcode VCNZ V RV IL PS D M FS MD RW MM MW E xxxx E xxx x 0 E 0000 xxx E xxx 0xxx 0xxx x 0 E xxx INF 0 0 0xxx 0xxx 0xxx x E xxxx INF xxxx x 0 E xxx0 E xxxx x x 0 E xxx INF xxxx x x 0 E xxxx INF 0 0 xxxx xxxx xxxx x xxxx 0 0 x 0 25

6 9-24. Partial state machine diagram: E0 R8 R8 R8 E R9 RS [ ] RS [ ] Z ( ) E3 INF Z N ( ) E2 Z N ( ) R8 R8 + RDR [ ] R8 +, pcode VCNZ IL PS D M FS MD RW MM MW E xxxx E E xxx E xxx 0xxx E xx00 E xxx 0xxx E xx0 INF xxx 0xxx E xxxx E xxxx x E xxxx INF 0 0 0xxx 000 xxxx x (Errata: dd a + and the following hint. Hint: In order to address all eight registers, it is necessary to provide eight values for S in the Instruction Register. Since the instruction register can only be loaded from memory, these instructions must be placed in memory temporarily during the instruction execution and loaded into the IR as data without using the normal instruction fetch. ) The operation code used for SMR and these instructions is 0 which is easy to generate by complementing all 0 s. The word to be stored in memory is built in a register by complementing all 0 s and NDing the result with the value of S from the original instruction. The register value generated is incremented, stored in memory and loaded into the IR after the execution of each transfer from a register to a memory location. Register Transfer pcode VCNZ IL PS D M FS MD RW MM MW R8 R[S] E0 0 xxxx E xxx xxxx R9 R9 R9 (R9 0) E 0 xxxx E R9 R9 E2 0 xxxx E xxxx x R0 sr R9 E3 0 xxxx E xxxx x R9 R0 zf S E4 0 xxxx E xxxx R zf S E5 0 xxxx E xxxx xxxx M[R0] R9 E6 0 xxxx E7 0 0 xxxx xxxx x 0 0 IR M[R0] E7 0 xxxx E8 0 xxxx 00 xxxx x xxxx x M[R8] R[S] E8 0 xxxx E9 0 0 xxxx 000 0xxx 0 xxxx 0 0 R8 R8 + E9 0 xxxx E xxxx x R9 R9 + E0 0 xxxx E xxxx x R zf S, Z : E5 E 0 xxx0 E5 0 0 xxxx 0 xxxx 00 x R zf S, Z : INF, inc PC E 0 xxx INF 0 0 xxxx 0 xxxx 00 x

7 9-26. (Errata: Solution of this problem with the architecture available is too difficult and while it can be solved, any solution is highly impractical. It will be removed in the 2nd and subsequent printings.) 27

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