Counters. Clocked sequential circuit whose state diagram contains a single cycle. Modulus number of states in the cycle. Counters with nonpower

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1 Counters S S S Clocked sequential circuit whose state diagram contains a single cycle. Sm S S Modulus number of states in the cycle. Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e Counters with nonpower of modulus has unused states

2 Ripple Counters Ripple counter. Requires fewer components than other counters. Slowest one. T T 0 T T Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

3 Synchronous Counters Synchronous counters. Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e The clock inputs of all flip-flops in the counter circuit are connected to a common clock signal. Synchronous serial counter. CNTEN EN T EN T EN T EN T 0

4 Counters Synchronous parallel counter. CNTEN EN 0 T EN T EN T EN T Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

5 MSI Counters x

6 MSI Counters x L_L () () _L () A () () A B () () B C () () C () () () () (0) Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

7 x Free Running Mode x + V R RPU 0 L A B C A B C U A B C Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e A B C COUNT Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

8 x Modulo Counters x x + V R RPU 0 L A A B B C C U x V R RPU 0 L A A B B C C U CNT CNT_L x0 U 0 CNT0_L U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

9 x Excess- Counter x + V R RPU 0 L A A B B C C U x00 0 SXX_L U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

10 x Cascading Counters x x RESET_L LOA_L CNTEN 0 0 L A B C A B C 0 0 L A B C A B C 8 U U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

11 x Modulo Counter + V R RPU 0 x L A B C A B C 0 RESET_L GO_L x00 U CNTEN x00 RELOA_L U x U L 0 A A B B C C MAXCNT U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

12 x Modulo 8 Counter With ecoder RPU + V 0 x L A A B B C C U R x8 Y0 G Y GA Y GB Y Y A Y B Y C Y 0 U S0_L S_L S_L S_L S_L S_L S_L S_L Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e _L S0_L S_L S_L S_L S_L S_L S_L S_L COUNT 0 0 Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

13 x Modulo 8 Counter With ecoder Modulo 8 counter with decoder and glitch-free outputs. RPU 0 x L A B C A B C U + V R x8 Y0 G Y GA Y GB Y Y A Y B Y C Y 0 U S0_L S_L S_L S_L S_L S_L S_L S_L OE x U RS_L RS_L RS_L RS_L RS_L RS_L RS_L RS0_L Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

14 N-bit register with the provision for shifting its stored data by a bit position each tick of the clock. SERIN Serial input specifies a new bit to shifted into the register. Serial output specifies the bits being shifted out of the register SEROUT Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

15 LOA/SHIFT SERIN N N Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e Parallel input specifies a new set of bits to be entered into the register, all at once during a single clock tick. Parallel output specifies the bits at the output of every flip-flop in the register.

16 Serial-in, parallelout shift register. SERIN N Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

17 LOA/SHIFT Parallel-in, serialout shift register. SERIN SEROUT N Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

18 MSI Shift Registers. x serial-in, parallel-out with asynchronous clear input. x parallel-in, serial-out with asynchronous clear input. x universal shift register. Inputs Next state Function S S0 A B C Hold 0 0 A B C Shift right 0 RIN A B C Shift left 0 B C LIN Load A B C

19 () _L () LIN () 0 S S0 00 () () 0 RIGHT 0 00 C () () C B () () B S (0) 0 LEFT S0 () 0 00 A () () A RIN () 0 Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

20 Shift register counter a circuit formed by a shift registers and combinational logic. The state diagram for this state machine is cyclic. This circuit does not necessarily count in ascending or descending order. Ring Counter the simplest shift register counter. This circuit uses a n- bit shift register to obtain a counter with n states.

21 + V R x RESET (load) 0 S S0 LIN C C B B A A RIN wired as a shift-left shift register 0 RESET 0 STATE S S S S S S Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

22 Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

23 A self correcting counter is designed so that all abnormal states have transitions leading to normal states V R ABC0 x 0 S S0 LIN C C B B A A RIN U wired as a shift-left shift register x U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

24 Twisted-ring, Moebius or Johnson counter is a n-bit shift register whose serial input receives the complement of serial output. This counter has n states. RESET_L + V R x 0 S S0 LIN C C B B A A RIN _L U wired as a shift-left shift register x0 U Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e 0 RESET_L 0 STATE S S S S S S S S8 S S S Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

25 igital telephony. Central offices samples analog voice 8000 times/sec (once every μs). Then the COs transmit them digitally over a kbps serial channel. kbps is much less than can be achieved by a single digital line, therefore several kbps signals are multiplexed onto a single wire.

26 x L A B 0 A B C C U x L A B 0 A B C C U RESET_L x SH/L SERIN A B C E F G H 0 H INH U x0 U BIT_L SYNC 0 parallel data + V SYNC timeslot number to destination bit number SATA R BC0 BC BC BC BC BC BC BC

27 + V x R RESET_L L 0 A A B B C C U x BC0 BC BC BC x0 U bit number (a) (.08 MHz) 88 nsec clock ticks per μsec frame L 0 A A B B C C BIT_L BC BC BC BC SYNC timeslot number SYNC SYNC SATA timeslot timeslot 0 timeslot timeslot timeslot 0 U x timeslots per frame INH SH/L SERIN A B to destination parallel data 0 C 0 E F G H H U SATA (b) bit 0 0 SYNC BIT_L 0 SATA 0 0 timeslot timeslot 0 timeslot Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e

28 + V R SYNC_L x L 0 A A B B C C U x BC0 BC BC BC x BIT0 U bit number from source SYNC x0 U 0 L A B C A B C U x0 U BC BC BC BC BIT0_L timeslot number x SATA Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e 8 SERA SERB R A B R C R R E 0 R R F R G R0 H U x G U P P P P P P P P0 parallel data

29 x + V R SYNC_L L 0 A A B B C C U x BC0 BC BC BC x BIT0 U bit number from source SYNC x0 U L 0 A A B B C C U x0 BIT0_L U BC BC BC BC timeslot number x SATA Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e 8 SERA SERB R A B R C R R E 0 R R F R G R0 H U x G U P P P P P P P P0 parallel data bit 0 0 SYNC BIT0_L SATA 0 0 byte byte 0 byte R0 R partial byte byte partial byte 0 byte 0 partial byte P0 P byte 0 byte byte 0 Copyright 000 by Prentice Hall, Inc. igital esign Principles and Practices, /e