Topics for Lecture #9. Button input processor

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1 opics for Lecture # Reminder: midterm examination # next uesday starting at :0am. Examples of small state machines simultaneous button push detector (continued) button push processor pulse stretcher General procedure for state machine design Counters: definitions, examples, applications October, 00 EE : igital esign Laboratory Lecture utton input processor Requirement: output a pulse of duration one clock period in response to each input pulse. Example of desired behavior. IN OU he dashed pulse corresponds to an ambiguity in the specifications: how should this state machine respond to consecutive short input pulses? In some applications consecutive pulses will not or should not occur, so this possibility can be ignored. October, 00 EE : igital esign Laboratory Lecture

2 utton input processor () State machines and transition/output tables. October, 00 EE : igital esign Laboratory Lecture Pulse stretcher Requirement: each input pulse produces a -clock output pulse. Example of desired behavior: IN OU hese specifications are also ambiguous: is the output retriggerable? Can output pulses be longer than clocks? October, 00 EE : igital esign Laboratory Lecture

3 Pulse stretcher () State machines and transition/output tables. he circuit can be simplified by decomposing into two state machines. IN MCL ONE GO OU CN October, 00 EE : igital esign Laboratory Lecture State machine design 0. Specify desired behavior of machine unambiguously (often hardest step).. Construct state/output table (or draw a state diagram, often preferable).. Minimize the number of states (optional).. State assignment: choose state variables and assign values to named states.. Form transition/output table from state/output table using state values.. Choose flip-flop type. nswer: flip-flops. Construct excitation table (not needed for flip-flops). erive excitation equations from excitation table. 8. erive output equations from transition/output table.. raw logic diagram of next-state logic (or provide equations to C tools). October, 00 EE : igital esign Laboratory Lecture

4 Counter uses Real time clock: cycle through a sequence of states in a known order. State encodings: binary, C = binary coded decimal, Gray. Frequency divider: output a period signal at a fraction of input frequency. Event counter: increment state each time a signal or oolean function is true (on rising edge of clock). Interval timer: count number of clock pulses between start and stop signals larm clock: activate an alarm signal at a specified time in the future. elay: activate a timeout signal after a specified number of clock cycles. October, 00 EE : igital esign Laboratory Lecture Ripple vs. synchronous counter 0 CNEN EN 0 EN EN EN Ripple counter: each bit toggles when lower order bit changes from to 0. Synchronous: a bit changes at rising clock edge when all lower bits are. October, 00 EE : igital esign Laboratory Lecture 8

5 x binary synchronous counter x Logic symbol: 0 C C Next-state logic and output logic for the x: [,C,C,] := if then [0,0,0,0] else if then [,C,,] else if * then [,C,C,] + [0,0,0,] else [,C,C,]; = * * C * * ; October, 00 EE : igital esign Laboratory Lecture x state table able 8- State table for a x -bit binary counter. Inputs Current State Next State _L _L C C 0 x x x x x x x x x x x x x C 0 x x x x x C x 0 x x x x C October, 00 EE : igital esign Laboratory Lecture 0

6 x logic diagram () _L () _L () () () CK () () CK C () () C CK () () CK () () (0) October, 00 EE : igital esign Laboratory Lecture Connections: x: free-running counter + V x RPU 0 C C U iming diagram for divide-by- counter R C C COUN October, 00 EE : igital esign Laboratory Lecture

7 Modulo- counters x State sequence:,,...,,... + V R RPU 0 C C U x0 CN CN_L U 0 x State sequence: 0,,...,0,... + V R RPU CN0_L 0 C C U x00 U 0 October, 00 EE : igital esign Laboratory Lecture Excess- decimal counter x State sequence:,,...,,,... + V R RPU 0 C C U SXX_L x00 U 0 With one -input NN gate, any period between and can be obtained. In fact, any low and high values can be specified. rawback of x: counts up only. Use x for bidirectional counting. October, 00 EE : igital esign Laboratory Lecture

8 Cascaded binary counters x x RESE_L LO_L CNEN 0 0 C C 0 0 C C 8 U Important: do not use as a clock. may (will) glitch. should be used to enable the next counter, i.e., to tell the next counter when to increment on the next active clock edge. U October, 00 EE : igital esign Laboratory Lecture elay submachine using x x GO 0 0 C C ONE ONE is asserted four clocks after GO is asserted. GO CN ONE October, 00 EE : igital esign Laboratory Lecture

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