Sequential Circuits. CS/EE 3700 : Fundamentals of Digital System Design
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1 Sequential Circuits CS/EE 37 : Fundamentals of igital System esign Chris J. Myers Lecture 7: Flip-flops, Registers, Counters Chapter 7 Combinational output depends only on the input. Sequential output depends on input and past behavior. Require use of storage elements. Contents of storage elements is called state. Circuit goes through sequence of states as a result of changes in inputs. Sensor Reset Set Memory element On Off Alarm A B Figure 7. Control of an alarm system Figure 7.2 A simple memory element Load ata G A B Output Reset Set G2 Figure 7.3 A controlled memory element Figure 7.4 A memory element with NOR gates
2 R S a b S R a b // (no change) (b) ruth table R Clk S R S Clk S R x x ( t + ) (t ) (no change) (t ) (no change) x t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t (b) ruth table R Clk S a b Figure 7.5 (c) iming diagram A latch built with NOR gates?? ime R S (c) iming diagram Figure 7.6 Gated SR latch?? ime S Clk R (d) Graphical symbol (ata) S Clk S R Clk R Clk x ( t + ) ( t ) Clk (b) ruth table (c) Graphical symbol Figure 7.7 Gated SR latch with NAN gates Figure 7.8 Gated latch (ata) S Clk R t su t h t t 2 t 3 t 4 Clk Clk (d) iming diagram ime Figure 7.8 Gated latch Figure 7.9 Setup and hold times 2
3 Master Slave m s P3 Clk Clk 2 P 5 3 P2 6 m = s 4 P4 (b) Graphical symbol (b) iming diagram (c) Graphical symbol Figure 7. Master-slave flip-flop Figure 7. A positive-edge-triggered flip-flop Preset a Clk a b b a c b Preset c c (b) iming diagram (b) Graphical symbol Figure 7.2 Comparison of level-sensitive and edge-triggered Figure 7.3 Master-slave flip-flop with and Preset Preset Preset (b) Graphical symbol Figure 7.4 Positive-edge-triggered flip-flop with and Preset Figure 7.5 Synchronous reset for a flip-flop 3
4 ( t + ) ( t ) ( t ) (b) ruth table (c) Graphical symbol J K J K ( t + ) ( t) ( t) J K (d) iming diagram (b) ruth table (c) Graphical symbol Figure 7.6 flip-flop Figure 7.7 JK flip-flop In Out Summary of erminology Basic latch cross-coupled NAN/NOR Gated latch output changes when clk =. Gated SR latch Gated latch Flip-flop output changes only on clk edge. Edge-triggered flip-flop Master-slave flip-flop t t t 2 t 3 t 4 t 5 t 6 t 7 In = Out (b) A sample sequence Figure 7.8 A simple shift register Parallel output Serial input Shift/Load Parallel input Count (b) iming diagram Figure 7.9 A simple shift register Figure 7.2 A three-bit up-counter 4
5 2 cycle changes 2 changes 2 Count (b) iming diagram Figure 7.2 A three-bit down-counter able 7. erivation of the synchronous up-counter 2 3 Enable Count (b) iming diagram Figure 7.22 A four-bit synchronous up-counter Figure 7.23 Inclusion of enable and clear capability Enable Enable Output carry Load Output carry Figure 7.24 A four-bit counter with flip-flops Figure 7.25 A counter with parallel-load capability 5
6 Enable Load 2 Count (b) iming diagram 2 Count (b) iming diagram Figure 7.26 A modulo-6 counter with synchronous reset Figure 7.27 A modulo-6 counter with asynchronous reset n Enable BC Start Load (a) An n -bit ring counter Enable 2 2 BC 2 3 y y y 2 y 3 2-to-4 decoder 3 3 w w En Load wo-bit up-counter Start Figure 7.28 A two-digit BC counter Figure 7.29 Ring counter (b) A four-bit ring counter n Reset Figure 7.3 Johnson counter Figure 7.3 hree types of storage elements in a schematic 6
7 Interconnection wires ata PAL-like block ata Latch Latch Flip- op oggle (Other macrocells not shown) Figure 7.32 Gated latch generated by CA tools Figure 7.33 Implementation of a circuit in a CPL USE ieee.std_logic_64.all ; LIBRARY altera ; USE altera.maxplus2.all ; ENIY flipflop IS POR (, : IN S_LOGIC ; Resetn, Presetn : IN S_LOGIC ; : OU S_LOGIC ) ; EN flipflop ; ARCHIECURE Structure OF flipflop IS dff_instance: dff POR MAP (,, Resetn, Presetn, ) ; EN Structure ; Figure 7.34 iming simulation of storage elements Figure 7.35 Instantiating a flip-flop from a package USE ieee.std_logic_64.all ; ENIY implied IS POR ( A, B : IN S_LOGIC ; AeqB : OU S_LOGIC ) ; EN implied ; ARCHIECURE Behavior OF implied IS PROCESS ( A, B ) IF A = B HEN AeqB <= '' ; EN IF ; EN PROCESS ; EN Behavior ; USE ieee.std_logic_64.all ; ENIY latch IS POR (, Clk : IN S_LOGIC ; : OU S_LOGIC) ; EN latch ; ARCHIECURE Behavior OF latch IS PROCESS (, Clk ) IF Clk = '' HEN <= ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.36 Implied memory Figure 7.37 Code for a gated latch 7
8 USE ieee.std_logic_64.all ; ENIY flipflop IS POR (, : IN S_LOGIC ; : OU S_LOGIC) ; EN flipflop ; ARCHIECURE Behavior OF flipflop IS PROCESS ( ) IF 'EVEN AN = '' HEN <= ; EN IF ; EN PROCESS ; EN Behavior ; LIBRARY ieee; USE ieee.std_logic_64.all; ENIY flipflop IS POR (, : IN S_LOGIC ; : OU S_LOGIC ) ; EN flipflop ; ARCHIECURE Behavior OF flipflop IS PROCESS WAI UNIL 'EVEN AN = '' ; <= ; EN PROCESS ; EN Behavior ; Figure 7.38 Code for a flip-flop Figure 7.39 Code for a flip-flop using WAI UNIL USE ieee.std_logic_64.all ; ENIY flipflop IS POR (, Resetn, : IN S_LOGIC ; : OU S_LOGIC) ; EN flipflop ; ARCHIECURE Behavior OF flipflop IS PROCESS ( Resetn, ) IF Resetn = '' HEN <= '' ; ELSIF 'EVEN AN = '' HEN <= ; EN IF ; EN PROCESS ; EN Behavior ; USE ieee.std_logic_64.all ; ENIY flipflop IS POR (, Resetn, : IN S_LOGIC ; : OU S_LOGIC) ; EN flipflop ; ARCHIECURE Behavior OF flipflop IS PROCESS WAI UNIL 'EVEN AN = '' ; IF Resetn = '' HEN <= '' ; <= ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.4 flip-flop with asynchronous reset Figure 7.4 flip-flop with synchronous reset Figure 7.42 he lpm_ff parameterized flip-flop module Figure 7.43 An adder with registered feedback 8
9 iming Constraints 2 ns from register clocked to data output. 8 ns for adder to produce sum. 4 ns for sum to propagate to register input. 3 ns for setup time. cycle time must be 7 ns. Figure 7.44 iming simulation USE ieee.std_logic_64.all ; LIBRARY lpm ; USE lpm.lpm_components.all ; ENIY shift IS POR ( : IN S_LOGIC ; Reset : IN S_LOGIC ; Shiftin, Load : IN S_LOGIC ; R : IN S_LOGIC_VECOR(3 OWNO ) ; : OU S_LOGIC_VECOR(3 OWNO ) ) ; EN shift ; ARCHIECURE Structure OF shift IS instance: lpm_shiftreg GENERIC MAP (LPM_WIH => 4, LPM_IRECION => "RIGH") POR MAP (data => R, clock =>, aclr => Reset, load => Load, shiftin => Shiftin, q => ) ; EN Structure ; USE ieee.std_logic_64.all ; ENIY reg8 IS POR ( : IN S_LOGIC_VECOR(7 OWNO ) ; Resetn, : IN S_LOGIC ; : OU S_LOGIC_VECOR(7 OWNO ) ) ; EN reg8 ; ARCHIECURE Behavior OF reg8 IS PROCESS ( Resetn, ) IF Resetn = '' HEN <= "" ; ELSIF 'EVEN AN = '' HEN <= ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.45 Instantiation of the lpm_shiftreg module Figure 7.46 Code for an eight-bit register with asynchronous clear USE ieee.std_logic_64.all ; ENIY regn IS GENERIC ( N : INEGER := 6 ) ; POR ( : IN S_LOGIC_VECOR(N- OWNO ) ; Resetn, : IN S_LOGIC ; : OU S_LOGIC_VECOR(N- OWNO ) ) ; EN regn ; ARCHIECURE Behavior OF regn IS PROCESS ( Resetn, ) IF Resetn = '' HEN <= (OHERS => '') ; ELSIF 'EVEN AN = '' HEN <= ; EN IF ; EN PROCESS ; EN Behavior ; USE ieee.std_logic_64.all ; ENIY muxdff IS POR (,, Sel, : IN S_LOGIC ; : OU S_LOGIC ) ; EN muxdff ; ARCHIECURE Behavior OF muxdff IS PROCESS WAI UNIL 'EVEN AN = '' ; IF Sel = '' HEN <= ; <= ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.47 Code for an n-bit register with asynchronous clear Figure 7.48 Code for a flip-flop with a 2-to- multiplexer on the input 9
10 USE ieee.std_logic_64.all ; ENIY shift4 IS POR ( R : IN S_LOGIC_VECOR(3 OWNO ) ; L, w, : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR(3 OWNO ) ) ; EN shift4 ; ARCHIECURE Structure OF shift4 IS COMPONEN muxdff POR (,, Sel, : IN S_LOGIC ; : OU S_LOGIC ) ; EN COMPONEN ; Stage3: muxdff POR MAP ( w, R(3), L,, (3) ) ; Stage2: muxdff POR MAP ( (3), R(2), L,, (2) ) ; Stage: muxdff POR MAP ( (2), R(), L,, () ) ; Stage: muxdff POR MAP ( (), R(), L,, () ) ; EN Structure ; Figure 7.49 Hierarchical code for a four-bit shift register USE ieee.std_logic_64.all ; ENIY shift4 IS POR ( R : IN S_LOGIC_VECOR(3 OWNO ) ; : IN S_LOGIC ; L, w : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR(3 OWNO ) ) ; EN shift4 ; ARCHIECURE Behavior OF shift4 IS PROCESS WAI UNIL'EVEN AN = '' ; IF L = '' HEN <= R ; () <= () ; () <= (2); (2) <= (3) ; (3) <= w ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.5 Alternative code for a shift register USE ieee.std_logic_64.all ; ENIY shift4 IS POR ( R : IN S_LOGIC_VECOR(3 OWNO ) ; : IN S_LOGIC ; L, w : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR(3 OWNO ) ) ; EN shift4 ; ARCHIECURE Behavior OF shift4 IS PROCESS WAI UNIL'EVEN AN = '' ; IF L = '' HEN <= R ; (3) <= w ; (2) <= (3) ; () <= (2); () <= () ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.5 Code that reverses the ordering of statements USE ieee.std_logic_64.all ; ENIY shiftn IS GENERIC ( N : INEGER := 8 ) ; POR ( R : IN S_LOGIC_VECOR(N- OWNO ) ; : IN S_LOGIC ; L, w : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR(N- OWNO ) ) ; EN shiftn ; ARCHIECURE Behavior OFshiftn IS PROCESS WAI UNIL'EVEN AN = '' ; IF L = '' HEN <= R ; Genbits: FOR i IN O N-2 LOOP (i) <= (i+) ; EN LOOP ; (N-) <= w ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.52 Code for an n-bit left-to-right shift register USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENIY upcount IS POR (, Resetn, E : IN S_LOGIC ; : OU S_LOGIC_VECOR (3 OWNO )) ; EN upcount ; ARCHIECURE Behavior OFupcountIS SIGNAL Count : S_LOGIC_VECOR (3 OWNO ) ; PROCESS (, Resetn ) IF Resetn = '' HEN Count <= "" ; ELSIF ('EVENAN = '') HEN IF E = '' HEN Count <= Count + ; Count <= Count ; EN IF ; EN IF ; EN PROCESS ; <= Count ; EN Behavior ; Figure 7.53 Code for a four-bit up-counter USE ieee.std_logic_64.all ; ENIY upcount IS POR ( R : IN INEGER RANGE O 5 ;, Resetn, L : IN S_LOGIC ; : BUFFER INEGER RANGE O 5 ) ; EN upcount ; ARCHIECURE Behavior OFupcountIS PROCESS (, Resetn ) IF Resetn = '' HEN <= ; ELSIF ('EVENAN = '') HEN IF L = '' HEN <= R ; <= + ; EN IF; EN IF; EN PROCESS; EN Behavior; Figure 7.54 A four-bit counter with parallel load, using INEGER signals
11 USE ieee.std_logic_64.all ; ENIY downcnt IS GENERIC ( modulus : INEGER := 8 ) ; POR (, L, E : IN S_LOGIC ; : OU INEGER RANGE O modulus- ) ; EN downcnt ; Extern ata Bus ARCHIECURE Behavior OFdowncnt IS SIGNAL Count : INEGER RANGE O modulus- ; PROCESS WAI UNIL ('EVENAN = '') ; IF E = '' HEN IF L = '' HEN Count <= modulus- ; Count <= Count- ; EN IF ; EN IF ; EN PROCESS; <= Count ; EN Behavior ; R R 2 Rk R in R out R 2 in R 2 out Rk in Rk out Control circuit Function Figure 7.55 Code for a down-counter Figure 7.56 A digital system with k registers Register Swapping Bus R o u t R 2 o u t Consider 3 register example (R, R2, R3) that swaps contents of R and R2 using R3. hree steps: Contents of R2 transferred to R3. R i n R 2 i n R R 2 Contents of R transferred to R2. Contents of R3 transferred to R. Figure 7.57 etails for connecting registers to a bus R 2 out, R 3 in R out, R 2 in R 3 out, R in R 2 out, R 3 in R out, R 2 in R 3 out, R in Reset w w P Reset Figure 7.58 A shift-register control circuit Figure 7.59 A modified control circuit
12 R 2 out, R 3 in R out, R 2 in R 3 out, R in Bus w R in R 2 in Rk R R 2 in Rk ata S Multiplexers S j Reset Figure 7.6 A control circuit that does not require flip-flop preset inputs Figure 7.6 Using multiplexers to implement a bus USE ieee.std_logic_64.all ; ENIY regn IS GENERIC ( N : INEGER := 8 ) ; POR ( R : IN S_LOGIC_VECOR(N- OWNO ) ; Rin, : IN S_LOGIC ; : OU S_LOGIC_VECOR(N- OWNO ) ) ; EN regn ; ARCHIECURE Behavior OF regn IS PROCESS WAI UNIL 'EVEN AN = '' ; IF Rin = '' HEN <= R ; EN IF ; EN PROCESS ; EN Behavior ; USE ieee.std_logic_64.all ; ENIY trin IS GENERIC ( N : INEGER := 8 ) ; POR ( X : IN S_LOGIC_VECOR(N- OWNO ) ; E : IN S_LOGIC ; F : OU S_LOGIC_VECOR(N- OWNO ) ) ; EN trin ; ARCHIECURE Behavior OF trin IS F <= (OHERS => 'Z') WHEN E = '' X ; EN Behavior ; Figure 7.62 Code for an n-bit register with enable Figure 7.63 Code for an n-bit tri-state buffer USE ieee.std_logic_64.all ; USE ieee.std_logic_64.all ; ENIY shiftr IS -- left-to-right shift register withasync reset GENERIC ( K : INEGER := 4 ) ; POR ( Resetn,, w : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR( O K) ) ; EN shiftr ; ARCHIECURE Behavior OFshiftr IS PROCESS ( Resetn, ) IF Resetn = '' HEN <= (OHERS => '') ; ELSIF 'EVENAN = '' HEN Genbits: FOR i IN K OWNO 2 LOOP (i) <= (i-) ; EN LOOP ; () <= w ; EN IF ; EN PROCESS ; EN Behavior ; Figure 7.64 Code for the shift-register controller PACKAGE components IS COMPONENregn -- register GENERIC ( N : INEGER := 8 ) ; POR ( R : IN S_LOGIC_VECOR(N- OWNO ) ; Rin, : IN S_LOGIC ; : OU S_LOGIC_VECOR(N- OWNO ) ) ; EN COMPONEN ; COMPONENshiftr -- left-to-right shift register withasync reset GENERIC ( K : INEGER := 4 ) ; POR ( Resetn,, w : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR( O K) ) ; EN component ; COMPONENtrin -- tri-state buffers GENERIC ( N : INEGER := 8 ) ; POR ( X : IN S_LOGIC_VECOR(N- OWNO ) ; E : IN S_LOGIC ; F : OU S_LOGIC_VECOR(N- OWNO ) ) ; EN COMPONEN ; EN components ; Figure 7.65 Package and component declarations 2
13 USE ieee.std_logic_64.all ; USE work.components.all ; ENIY swap IS POR ( ata : IN S_LOGIC_VECOR(7 OWNO ) ; Resetn, w : IN S_LOGIC ;, Extern : IN S_LOGIC ; RinExt : IN S_LOGIC_VECOR( O 3) ; BusWires : INOU S_LOGIC_VECOR(7 OWNO ) ) ; EN swap ; tri_ext: trin POR MAP ( ata, Extern,BusWires ) ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg2: regnpor MAP ( BusWires, Rin(2),, R2 ) ; reg3: regnpor MAP ( BusWires, Rin(3),, R3 ) ; tri: trin POR MAP ( R, Rout(),BusWires) ; tri2: trin POR MAP ( R2, Rout(2),BusWires) ; tri3: trin POR MAP ( R3, Rout(3),BusWires) ; EN Behavior ; ARCHIECURE Behavior OF swap IS SIGNALRin, Rout, : S_LOGIC_VECOR( O 3) ; SIGNAL R, R2, R3 : S_LOGIC_VECOR(7 OWNO ) ; control: shiftr GENERIC MAP ( K => 3 ) POR MAP ( Resetn,, w, ) ; Rin() <= RinExt() OR (3) ; Rin(2) <= RinExt(2) OR (2) ; Rin(3) <= RinExt(3) OR () ; Rout() <= (2) ; Rout(2) <= () ; Rout(3) <= (3) ; Figure 7.66 A digital system with a bus Figure 7.66 A digital system with a bus USE ieee.std_logic_64.all ; USE work.components.all ; ENIY swapmux IS POR ( ata : IN S_LOGIC_VECOR(7 OWNO ) ; Resetn, w : IN S_LOGIC ; : IN S_LOGIC ; RinExt : IN S_LOGIC_VECOR( O 3) ; BusWires : BUFFER S_LOGIC_VECOR(7 OWNO ) ) ; EN swapmux; ARCHIECURE Behavior OFswapmuxIS SIGNALRin, : S_LOGIC_VECOR( O 3) ; SIGNAL S : S_LOGIC_VECOR( OWNO ) ; SIGNAL R, R2, R3 : S_LOGIC_VECOR(7 OWNO ) ; control: shiftr GENERIC MAP ( K => 3 ) POR MAP ( Resetn,, w, ) ; con t Rin() <= RinExt() OR (3) ; Rin(2) <= RinExt(2) OR (2) ; Rin(3) <= RinExt(3) OR () ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg2: regnpor MAP ( BusWires, Rin(2),, R2 ) ; reg3: regnpor MAP ( BusWires, Rin(3),, R3 ) ; encoder: WIH SELEC S <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OHERS ; muxes: --eight 4-to- multiplexers WIH S SELEC BusWires <= ata WHEN "", R WHEN "", R2 WHEN "", R3 WHEN OHERS ; EN Behavior ; Figure 7.67a Using multiplexers to implement a bus Figure 7.67b Using multiplexers to implement a bus (con t) (ENIY declaration not shown) ARCHIECURE Behavior OFswapmuxIS SIGNALRin, : S_LOGIC_VECOR( O 3) ; SIGNAL R, R2, R3 : S_LOGIC_VECOR(7 OWNO ) ; control: shiftr GENERIC MAP ( K => 3 ) POR MAP ( Resetn,, w, ) ; Rin() <= RinExt() OR (3) ; Rin(2) <= RinExt(2) OR (2) ; Rin(3) <= RinExt(3) OR () ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg2: regnpor MAP ( BusWires, Rin(2),, R2 ) ; reg3: regnpor MAP ( BusWires, Rin(3),, R3 ) ; muxes: WIH SELEC BusWires <= ata WHEN "", R2 WHEN "", R WHEN "", R3 WHEN OHERS ; EN Behavior ; Figure 7.68 Simplified code for describing a bus Figure 7.69 iming simulation 3
14 Figure 7.7 A digital system that implements a simple processor able 7.2 Operations performed in the processor I I I 2 I 3 X X X 2 X 3 Y Y Y 2 Y 3 y y y 2 y 3 y y y 2 y 3 y y y 2 y to-4 decoder w w En 2-to-4 decoder w w En 2-to-4 decoder w w En y y y 2 y 3 2-to-4 decoder w w En Up-counter Reset FR in Function Register f f Rx Rx Ry Ry Function Figure 7.7 A part of the control circuit for the processor Figure 7.72 he function registers and decoders Processor Control Logic = w + one FR in = w Extern = I one = (I + I ) + (I 2 + I 3 ) 3 A in = (I 2 + I 3 ) G in = (I 2 + I 3 ) 2 G out = (I 2 + I 3 ) 3 AddSub = I 3 R in = (I + I ) X + (I 2 +I 3 ) 3 X R out = I Y + (I 2 + I 3 )( X + 2 Y ) able 7.3 Control signals asserted in each operation/time step 4
15 USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENIY upcount IS POR (, : IN S_LOGIC ; : BUFFER S_LOGIC_VECOR( OWNO ) ) ; EN upcount ; ARCHIECURE Behavior OF upcount IS upcount: PROCESS ( ) IF ('EVEN AN = '') HEN IF = '' HEN <= "" ; <= + '' ; EN IF ; EN IF; EN PROCESS; EN Behavior ; Figure 7.73 Code for a two-bit up-counter with asynchronous reset USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; USE work.subccts.all ; ENIY proc IS POR ( ata : IN S_LOGIC_VECOR(7 OWNO ) ; Reset, w : IN S_LOGIC ; : IN S_LOGIC ; F, Rx, Ry : IN S_LOGIC_VECOR( OWNO ) ; one : BUFFER S_LOGIC ; BusWires : INOU S_LOGIC_VECOR(7 OWNO ) ) ; EN proc ; ARCHIECURE Behavior OF proc IS SIGNALRin, Rout : S_LOGIC_VECOR( O 3) ; SIGNAL, High,AddSub : S_LOGIC ; SIGNAL Extern,Ain, Gin, Gout, FRin : S_LOGIC ; SIGNAL Count, Zero : S_LOGIC_VECOR( OWNO ) ; SIGNAL, I, X, Y : S_LOGIC_VECOR( O 3) ; SIGNAL R, R, R2, R3 : S_LOGIC_VECOR(7 OWNO ) ; SIGNAL A, Sum, G : S_LOGIC_VECOR(7 OWNO ) ; SIGNALFunc, FuncReg : S_LOGIC_VECOR( O 6) ; con t Figure 7.74a Code for the processor Zero <= "" ; High <= '' ; <= Reset OR one OR (NO w AN ()) ; counter: upcountpor MAP (,, Count ) ; dec: dec2to4 POR MAP ( Count, High, ); Func <= F & Rx & Ry ; FRin <= w AN () ; functionreg: regn GENERIC MAP ( N => 6 ) POR MAP ( Func, FRin,, FuncReg) ; deci: dec2to4 POR MAP (FuncReg( O 2), High, I ) ; decx: dec2to4 POR MAP (FuncReg(3 O 4), High, X ) ; decy: dec2to4 POR MAP (FuncReg(5 O 6), High, Y ) ; Extern <= I() AN () ; one <= ((I() OR I()) AN ()) OR ((I(2) OR I(3)) AN (3)) ; Ain <= (I(2) OR I(3)) AN () ; Gin <= (I(2) OR I(3)) AN (2) ; Gout <= (I(2) OR I(3)) AN (3) ; AddSub <= I(3) ; con t Figure 7.74b Code for the processor (con t) RegCntl: FOR k IN O 3 GENERAE Rin(k) <= ((I() OR I()) AN () AN X(k)) OR ((I(2) OR I(3)) AN (3) AN X(k)) ; Rout(k) <= (I() AN () AN Y(k)) OR ((I(2) OR I(3)) AN ((() AN X(k)) OR ((2) AN Y(k)))) ; EN GENERAERegCntl; tri_extern: trin POR MAP ( ata, Extern,BusWires ) ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg2: regnpor MAP ( BusWires, Rin(2),, R2 ) ; reg3: regnpor MAP ( BusWires, Rin(3),, R3 ) ; tri: trin POR MAP ( R, Rout(),BusWires) ; tri: trin POR MAP ( R, Rout(),BusWires) ; tri2: trin POR MAP ( R2, Rout(2),BusWires) ; tri3: trin POR MAP ( R3, Rout(3),BusWires) ; rega: regn POR MAP ( BusWires, Ain,, A ) ; alu: WIH AddSub SELEC Sum <= A + BusWires WHEN '', A - BusWires WHEN OHERS ; regg: regn POR MAP ( Sum, Gin,, G ) ; trig: trin POR MAP ( G, Gout,BusWires ) ; EN Behavior ; Figure 7.74c Code for the processor (con t) (ENIY declaration not shown) ARCHIECURE Behavior OF proc IS SIGNAL X, Y,Rin, Rout : S_LOGIC_VECOR( O 3) ; SIGNAL, High,AddSub : S_LOGIC ; SIGNAL Extern,Ain, Gin, Gout, FRin : S_LOGIC ; SIGNAL Count, Zero,, I : S_LOGIC_VECOR( OWNO ) ; SIGNAL R, R, R2, R3 : S_LOGIC_VECOR(7 OWNO ) ; SIGNAL A, Sum, G : S_LOGIC_VECOR(7 OWNO ) ; SIGNALFunc, FuncReg, Sel : S_LOGIC_VECOR( O 6) ; Zero <= "" ; High <= '' ; <= Reset OR one OR (NO w AN NO () AN NO ()) ; counter: upcountpor MAP (,, Count ) ; <= Count ; Func <= F & Rx & Ry ; FRin <= w AN NO () AN NO () ; functionreg: regn GENERIC MAP ( N => 6 ) POR MAP ( Func, FRin,, FuncReg) ; I <= FuncReg( O 2) ; decx: dec2to4 POR MAP (FuncReg(3 O 4), High, X ) ; decy: dec2to4 POR MAP (FuncReg(5 O 6), High, Y ) ; controlsignals: PROCESS (, I, X, Y ) con t Figure 7.75a Alternative code for the processor Extern <= '' ; one <= '' ;Ain <= '' ; Gin <= '' ; Gout <= '' ; AddSub <= '' ; Rin <= "" ; Rout <= "" ; CASE IS WHEN "" => -- no signals asserted in time step WHEN "" => -- define signals asserted in time step CASE I IS WHEN "" => -- Load Extern <= '' ;Rin <= X ; one <= '' ; WHEN "" => -- Move Rout <= Y ;Rin <= X ; one <= '' ; WHEN OHERS => -- Add, Sub Rout <= X ;Ain <= '' ; EN CASE ; WHEN "" => -- define signals asserted in time step 2 CASE I IS WHEN "" => -- Add Rout <= Y ; Gin <= '' ; WHEN "" => -- Sub Rout <= Y ;AddSub <= '' ; Gin <= '' ; WHEN OHERS => -- Load, Move EN CASE ; WHEN OHERS => -- define signals asserted in time step 3 CASE I IS Figure 7.75b Alternative code for the processor (con t) 5
16 WHEN "" => -- Load WHEN "" => -- Move WHEN OHERS => -- Add, Sub Gout <= '' ; Rin <= X ; one <= '' ; EN CASE ; EN CASE ; EN PROCESS ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg: regnpor MAP ( BusWires, Rin(),, R ) ; reg2: regnpor MAP ( BusWires, Rin(2),, R2 ) ; reg3: regnpor MAP ( BusWires, Rin(3),, R3 ) ; rega: regn POR MAP ( BusWires, Ain,, A ) ; alu: WIH AddSub SELEC Sum <= A + BusWires WHEN '', A - BusWires WHEN OHERS ; regg: regn POR MAP ( Sum, Gin,, G ) ; Sel <= Rout & Gout & Extern ; WIH Sel SELEC BusWires <= R WHEN "", R WHEN "", R2 WHEN "", R3 WHEN "", G WHEN "", ata WHEN OHERS ; EN Behavior ; Figure 7.75c Alternative code for the processor (con t) Figure 7.76 iming simulation of the processor V V V V R R L c 9 c c R L -bit counter V LE w a b g a b g Converter Converter w w w 2 w 3 w w w 2 w 3 (a) divider (b) LE circuit c 9 BC BC E wo-digit BC counter Reset (c) Push-button switch, LE, and 7-segment displays Figure 7.77 A reaction-timer circuit Figure 7.77 A reaction-timer circuit USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENIY BCcount IS POR ( : IN S_LOGIC ;, E : IN S_LOGIC ; BC, BC : BUFFER S_LOGIC_VECOR(3 OWNO ) ) ; EN BCcount ; ARCHIECURE Behavior OF BCcount IS PROCESS ( ) IF 'EVEN AN = '' HEN IF = '' HEN BC <= "" ; BC <= "" ; con t ELSIF E = '' HEN IF BC = "" HEN BC <= "" ; IF BC = "" HEN BC <= ""; BC <= BC + '' ; EN IF ; BC <= BC + '' ; EN IF ; EN IF ; EN IF; EN PROCESS; EN Behavior ; Figure 7.78a Code for a two-digit BC counter Figure 7.78b Code for a two-digit BC counter (con t) 6
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