Evaluating Overheads of Multi-bit Soft Error Protection Techniques at Hardware Level Sponsored by SRC and Freescale under SRC task number 2042

Transcription

1 Evaluating Overheads of Multi-bit Soft Error Protection Techniques at Hardware Level Sponsored by SR and Freescale under SR task number 2042 Lukasz G. Szafaryn, Kevin Skadron Department of omputer Science University of Virginia Brett H. Meyer Department of Electrical & omputer Engineering McGill University SR Task: 2042

2 Problem: Multi-bit Soft Errors Area covered by a 2um particle strike radius with respect to the area of two 3-bit registers at various technology nodes [1] As devices become smaller, particle strike radius affects more circuit components In addition to storage (SRAM) circuits, it is now becoming a concern for logic (combinational/sequential) components Single particle strike can cause a multi-bit soft error that affects bits in the same or adjacent component(s) 2

3 Motivation Traditional techniques for single-bit soft errors in logic do not offer adequate protection against multi-bit errors We need to evaluate more aggressive techniques as they significantly change the overhead of protection We evaluate: ED/E (SEDED) Residue odes Spatial Redundancy Temporal Redundancy Feature Upsizing ED/E and Residue odes (ALU/FPU) Spatial and Temporal Redundancy (Interleaved) Parity Single-bit Upset 1 0 Multi-bit Upset

4 Implementation Use example processor design OpenRIS 1200 core Area-proportional ALU/FPU (20%) and ache (40%) Synthesized with IBM 90nm technology Develop considered protection techniques and apply them In combinations for different types of components At granularities: pipeline-stage, FE/BE or core Evaluate protection scenarios in terms of Area Delay Average Power 90nm technology 4

5 Protection Techniques Types of ircuits Temporal Redundancy Spatial Redundancy Residue odes (ALU/FPU) (Interleaved) Parity, ED/E Feature upsizing ombinational Sequential 5

6 Protection Techniques Fine-grained ED/E and Residue odes SRAM ED/E (1 encoder/decoder per array) ALU/FPU (ombinational Logic) Residue Generator/omparator Sequential Logic ED/E (1 encoder/decoder per word) Inst MMU/ ache E Reg File E ALU/FPU R E Data MMU/ ache E Instructions E E E Fetch Decode Execute Memory E Writeback E Spatial Redundancy Inst MMU/ ache Reg File ALU/FPU Data MMU/ ache ombinational/sequential Logic Redundancy omparator Instructions Fetch Decode Execute Memory Fetch Decode Execute Memory Writeback Writeback Inst MMU/ ache Reg File ALU/FPU Data MMU/ ache 6

7 Protection Techniques oarse-grained ycle-level Spatial Redundancy Inst MMU/ ache Data MMU/ ache Front End Back End ore Instructions Front End Back End ore Inst MMU/ ache Data MMU/ ache Multi-cycle-level Spatial and Temporal Redundancy heckpoi nt Buffer ore ore R R R Buffer Load/ Store Buffer heckpoi nt Buffer ore R R Buffer Load/ Store Buffer 7

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10 Area [normalized to Original] Protection Granularity Area Original All Parity All SEDED omponent Front-end/Back-end ore ALU/FPU Residue All Spatial Redundancy Spatial Redundancy can be applied at various granularities with similar detection/correction capability However, the difference in area overhead (corresponding to different amounts of intermediate outputs compared) is small This concept does not apply to SEDE as it would result in a loss of coverage due to the smaller number of storage elements protected 10

11 Delay [normalized to Original] Average Power [normalized to Original] Protection Granularity Delay and Average Power omponent FE/BE ore Original All Parity All SEDED ALU/FPU Residue All Spatial Redundancy omponent FE/BE ore Original All Parity All SEDED ALU/FPU Residue All Spatial Redundancy Granularity does not affect the overall delay, as there is still the same amount of logic in the critical path Power overhead of Spatial Redundancy slightly decreases at higher granularity due to smaller amount of state compared 11

12 Area [normalized to Original] Protection Designs Area R/Buffers Redundancy omparator Residue ode SEDED Parity Redundant omponents Original Red Spatial Redundancy Res Residue odes Tem Red Temporal Redundancy 1000 (cycles) checking frequency Area-optimal designs would use SEDED for storage (SRAM) circuits and Spatial Redundancy for logic (combinational/sequential) circuits Area can be traded for performance by checking correctness at multi-cycle time scale (1000 cycles, for example) Performance can traded for area by performing redundant computation in time under Temporal Redundancy 12

13 Delay [normalized to Original] Average Power [normalized to Original] Protection Designs Delay and Average Power ~2x total delay ~2x energy R/Buffers Redundancy omparator Residue ode SEDED Parity Redundant omponents Original At cycle-level, designs that use residue codes for ALU (the slowest component) incur the shortest overall delay hecking correctness at a multi-cycle time scale can be done off the critical path, thus shortening the overall delay Designs that minimize the use of SEDED for logic circuits achieve the lowest power consumption 13

14 onclusions Multi-bit soft errors are becoming a concern in logic (combinational/sequential) circuits Protection against multi-bit errors in logic components requires techniques that are more aggressive than traditionally used parity Error detecting/correcting codes are preferred for storage (SRAM) circuits while Spatial Redundancy is preferred for logic (combinational/sequential) circuits Increased granularity of Spatial Redundancy only slightly reduces overhead of protection Area can be traded for performance by checking correctness at multi-cycle scale Performance can be traded for area by performing redundant computation in time under Temporal Redundancy 14

15 Future Work Use error injection in the simulator to evaluate vulnerability of components and effectiveness of protection techniques Evaluate performance and power for common benchmarks Investigate recovery overhead of protection mechanisms onsider wider range of protection techniques Evaluate benefit of multi-cycle-level Temporal Redundancy in a superscalar processor at application level 15

16 Technology Transfer Industry Interactions Freescale Internships Intel, summer Publications/presentations TEHON 2012 paper 16

17 Questions

18 References [1] Nishant J. George, arl R. Elks, Barry W. Johnson, John Lach. Bit-slice logic interleaving for spatial multi-bit soft-error tolerance.

19 OpenRIS Area D ache I ache D MMU I MMU ontrol Fetch Decode Execute Int ALU FPU Memory Writeback Arch Reg Reg File OpenRIS features: Single in-order pipeline I/D MMU I/D ache

20 OpenRIS Delay and Average Power Arch Reg ontrol Writeback Fetch Memory 0.07 Decode FPU Int ALU Execute Decode Fetch ontrol Execute Int ALU FPU Memory Writeback Arch Reg Delay Average Power FPU has the highest delay and average power

21 OpenRIS ell ount and Area 0.06 Latches Latches Other 0.44 Other 0.62 SRAM 0.32 SRAM