L07-L09 recap: Fundamental lesson(s)!
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- Aron Carpenter
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1 L7-L9 recap: Fundamental lesson(s)! Over the next 3 lectures (using the IPS ISA as context) I ll explain:! How functions are treated and processed in assembly! How system calls are enabled in assembly! How exceptions are handled in assembly! I ll also explain why it s important that register conventions be followed!!
2 L7-L9 recap: Why it s important! If you ever write a compiler or OS some day, you will need to be aware of, and code for all of the issues to be discussed over the next 3 lectures! If you understand what architectural overhead may be associated with (compiled) procedure calls, you should be able to write much more efficient HLL code! 2!
3 Lecture The IPS datapath! Suggested reading:! (HP Chapter )! 3!
4 Processor components! ulticore processors and programming! Processor comparison! vs.! Goal: describe the fundamental components required in a single core of a modern microprocessor as well as how they interact with each other, with main memory, and with external storage media." CSE 332! Writing more! efficient code! The right HW for the right application! HLL code translation! 4!
5 Fundamental lesson(s)! Today we ll discuss what hardware is required to execute an instruction, as well as how to best organize it.! 5!
6 Why it s important! If you ever design the HW for a microprocessor, etc. you'll need to be aware of these types of issues! Understanding organization and how it impacts the delay of something like a memory reference - will make you a better programmer!! It is now more and more important to design HW/SW simultaneously! 6!
7 The organization of a computer! Von Neumann odel:! Stored-program machine instructions are represented as numbers" Programs can be stored in memory to be read/written just like " numbers." Today" we ll talk" about these" things" Control" Compiler" emory" Input" Focus of lectures 5-9" Datapath" Output" Processor" 7!
8 Review: Functions of Each Component! Datapath: performs data manipulation operations! arithmetic logic unit (ALU)! floating point unit (FPU)! Control: directs operation of other components! finite state machines! micro-programming (to be discussed)! emory: stores instructions and data! random access v.s. sequential access! volatile v.s. non-volatile! RAs (SRA, DRA), ROs (PRO, EEPRO), disk! tradeoff between speed and cost/bit! Input/Output and I/O devices: interface to environment! mouse, keyboard, display, device drivers! 8!
9 Let s derive the IPS datapath:! To simplify things a bit we ll just look at a few instructions:! memory-reference: lw, sw! arithmetic-logical: add, sub, and, or, slt! branching: beq, j! Organizational overview:! fetch an instruction based on the content of PC! decode the instruction! fetch operands! (read one or two registers)! execute! (effective address calculation/arithmetic-logical operations/ comparison)! store result! (write to memory / write to register / update PC)! Very common" instructions" With Von Neumann, " RISC model do similar" things for each" instruction " A 9!
10 A Single Cycle Datapath! ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] Let s trace a few insturctions! add "$5, $6, $7" sw "($9), $" sub"$, $2, $3" lw "$, ($2)" Instruction [5 ] 6 Sign 32 extend ALU control!
11 PERFORANCE!!
12 Single-Cycle Implementation! Single-cycle, fixed-length clock:! CPI =! Clock cycle = propagation delay of the longest datapath operations among all instruction types! Easy to implement! How to determine cycle length?! Calculate cycle time assuming negligible delays except:! memory (2ns), ALU and adders (2ns), register file access (ns)! R-type:!max {mem + RF + ALU + RF, Add}!!!= 6ns! LW:!max{mem + RF + ALU + mem + RF, Add}!!= 8ns! SW:!max{mem + RF + ALU + mem, Add}!!!= 7ns! BEQ:!max{mem + RF + ALU, max{add, mem + Add}}!= 5ns! What is the CC time?! 2!
13 Before, spoke about multi-cycle datapath! Init PC= Fetch IR=I[PC] PC=PC+ Decode op= op= op= Load RF[ra]=D[d] Store D[d]=RF[ra] Add RF[ra] = RF[rb]+ RF[rc] 3!
14 The multi-cycle approach (& benefits):! Break an instruction into smaller steps! Execute each step in one cycle.! Execution sequence:! Balance amount of work to be done! Restrict each cycle to use only one major functional unit! At the end of a cycle! Store values for use in later cycles! Introduce additional internal registers! The advantages:! Cycle time much shorter! Diff. inst. take different # of cycles to complete! Functional unit used more than once per instruction! 4!
15 IPS multi-cycle datapath! Note introduction of temporary storage registers" 5!
16 5 steps an instruction could take:!. Instruction Fetch (Ifetch):! Fetch instruction at address ($PC)! Store the instruction in register IR! Increment PC! 2. Instruction Decode and Register (Decode):! Decode the instruction type and read register! Store the register contents in registers A and B! Compute new PC address and store it in ALUOut! 3. Execution, emory Address Computation, or Branch Completion (Execute):! Compute memory address (for LW and SW), or! Perform R-type operation (for R-type instruction), or! Update PC (for Branch and Jump)! Store memory address or register operation result in ALUOut! 6!
17 5 steps an instruction could take:! 4. emory Access or R-type instruction completion!!(em/regwrite/emwrite):! memory at address ALUOut and store it in DR! Write ALUOut content into register file, or! Write memory at address ALUOut with the value in B! 5. Write-back step (WrBack):! Write the memory content read into register file! Number of cycles for an instruction:! R-type: 4! lw: 5! sw: 4! Branch or Jump: 3 7!
18 Instruction execution (summary):! Action for R-type Action for memory-reference Action for Action for Step name instructions instructions branches jumps Instruction fetch IR = em[pc], PC = PC + 4 Instruction A =RF [IR[25:2]], decode/register fetch B = RF [IR[2:6]], ALUOut = PC + (sign-extend (IR[:-]) << 2) Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A =B) then PC = PC [3:28] computation, branch/ (IR[5:]) PC = ALUOut (IR[25:]<<2) jump completion emory access or R-type RF [IR[5:]] = Load: DR = em[aluout] completion ALUOut or Store: em[aluout]= B emory read completion Load: RF[IR[2:6]] = DR 8!
19 Some questions:! How many cycles will it take to execute this code?!!!!lw $t2, ($t3)!!!lw $t3, 4($t3)!!!beq $t2, $t3, Label #assume branch is not taken!!!add $t5, $t2, $t3!!!sw $t5, 8($t3) Label:!...!! =2! What is being done during the 8th cycle of execution?!!!compute memory address: 4 + content of $t3! In what cycle does the addition of $t2 and $t3 takes place?!!6!! How would performance compare if multi-cycle clock period is 2 ns and cycle cycle period is ns?!!!(2 CCs x 2 ns) vs. (5 CCs x ns):!!42 ns vs. 5 ns!! 9!
20 Foreshadowing: pipelines! Note: Some extra HW needed.! Data must be stored from one stage to the next in pipeline registers/latches.! hold temporary values between clocks and needed info. for execution.! 2!
21 Another way to look at it! Clock Number! Inst. #!! 2! 3! 4! 5! 6! 7! 8! Inst. i! IF! ID! EX! E! WB! Inst. i+! IF! ID! EX! E! WB! Inst. i+2! IF! ID! EX! E! WB! Inst. i+3! IF! ID! EX! E! WB! Program execution order (in instructions)! ALU! I! Reg! D! Reg! ALU! I! Reg! D! Reg! ALU! I! Reg! D! Reg! ALU! Time! I! Reg! D! Reg! 2!
22 (Tying computer architecture to logic design )! A SHORT DISCUSSION ABOUT CONTROL LOGIC! 22!
23 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control When we talk about control," we talk about these blocks" Instruction [5 ] 23!
24 Single cycle control: inputs & outputs! Step :! Identify inputs & outputs" Control Inputs:! Opcode (6 bits)! How about R-type instructions?! Control Outputs:! RegDst! ALUSrc! emtoreg! RegWrite! em! emwrite! Branch! Jump! ALUctr! columns! rows! Step 2:! ake a control signal" table for each cycle" 24!
25 Control Signal Table! R-type! (inputs)! Add! Sub! LW! SW! BEQ! Func (input)!!! xxxxxx! xxxxxx! xxxxxx! Op (input)!!!!!! RegDst!!!! X! X! ALUSrc!!!!!! em-to-reg!!!! X! X! Reg. Write!!!!!! em.!!!!!! em. Write!!!!!! Branch!!!!!! ALUOp! Add! Sub!!!! (outputs)! 25!
26 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control For IPS, we have to" build a ain Control Block" and an ALU Control Block" Instruction [5 ] 26!
27 ain control, ALU control! OP! 6" (opcode)! ain! Control" Func! ALUOp" 6" 2" Other control" signals" ALU! Control" ALUctr! 3" ALU" Our 2 blocks! of control logic! Use OP field to generate ALUOp (encoding)! Control signal fed to ALU control block! Use Func field and ALUOp to generate ALUctr (decoding)! Specifically sets 3 ALU control signals! B-Invert, Carry-in, operation! 27!
28 ain control, ALU control! OP! 6" ain! Control" ALUOp" 2" Func! 6" ALU! Control" ALUctr! 3" ALU" Outputs of main control,! become inputs to ALU control! R-type! lw! sw! beq! ALU Operation! R-type! add! add! subtract! ALUOp<:>!!!!! We have 8 bits" of input to our ALU control" block; we need 3 bits of" output " Or in other words! = ALU performs add! = ALU performs sub! = ALU does what function code says! 28!
29 Generating ALUctr! We want these outputs:! ALU Operation! and! or! add! sub! slt! ALUctr<2:>!!!!!! mux! ALUctr<2> = B-negate (C-in & B-invert)" ALUctr<> = Select ALU Output" ALUctr<> = Select ALU Output" Invert B and C-in must be a for subtract" and -! or -! adder -! less -! We have these inputs! func<5:>! 36 (and)!=! 37 (or)!=! 32 (add)!=! 34 (sub)!=! 42 (slt)!=! can ignore these bits! (they re the same for all )! lw/sw! beq! R-type! Inputs" Outputs" ALUOp" Funct field" ALUctr" ALUOp" ALUOp" F5" F4" F3" F2" F" F" " " X" X" X" X" X" X" (add)! " " X" X" X" X" X" X" (sub)! " X" X" X" " " " " (add)! " X" X" X" " " " " (sub)! " X" X" X" " " " " (and)! " X" X" X" " " " " (or)! " X" X" X" " " " " (slt)! 29"
30 The logic:! This table is used to generate the actual Boolean logic gates that produce ALUctr." Could generate gates by hand, often done w/sw." (func<5:>) F2 F (ALUOp) /X /X F3 /X ALUOp ALUOp lw/sw! beq! R-type! X/ / and and or F /X /X / ALUOp" Funct field" ALUctr" ALUOp" ALUOp" F5" F4" F3" F2" F" F" " " X" X" X" X" X" X" (add)! " " X" X" X" X" X" X" (sub)! " X" X" X" " " " " (add)! " X" X" X" " " " " (sub)! " X" X" X" " " " " (and)! " X" X" X" " " " " (or)! " X" X" X" " " " " (slt)! ALUctr<2> or / / or Inputs" ALUctr<> / ALUctr<> / ALUctr / Ex: ALUctr<2> (SUB/BEQ) Outputs" 3!
31 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control For IPS, we have to" build a ain Control Block" and an ALU Control Block" Instruction [5 ] 3!
32 Well, here s what we did! Single cycle IPS machine" ux We came up with the information to generate this logic which would fit here in the datapath." 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add result ALU PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] ux register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control (ALUOp) F3 ALUOp ALUOp and or ALUctr<2> Instruction [5 ] (func<5:>) F2 or ALUctr<> ALUctr F F or and ALUctr<> 32!
33 Controller FS for 6-instruction processor! Recall:! With multi-cycle, need to generate control signals at right time" Captured by FS" Each level analogous to CC" " Init PC_clr= Fetch I _rd= PC_inc= I R_ld= Decode op= op= op= op= op= op= Load D_addr=d D_rd= RF_s = R F _ s = RF_W_addr=ra RF_W_wr= Store D_addr=d D_wr= RF_s = X RF_s = X RF_Rp_addr=ra RF_Rp_rd= Add RF_Rp_addr=rb RF_Rp_rd= RF_s = RF_s = RF_Rq_add=rc RF_Rq_rd= RF_W_addr_ra RF_W_wr= alu_s = alu_s = Loadconstant RF_s= RF_s= RF_W_addr=ra RF_W_wr= Subtract RF_Rp_addr=rb RF_Rp_rd= RF_s= RF_s= RF_Rq_addr=rc RF_Rq_rd= RF_W_addr=ra RF_W_wr= alu_s= alu_s= RF_Rp_zero Jump-if-zero RF_Rp_addr=ra RF_Rp_rd= Jump-ifzero-jmp PC_ld= RF_Rp_zero' 33!
34 IPS FS diagram! 2 e m o r y a d r e s s c o m p u t a t i o n A L U S r c A = A L U S r c B = A L U O p = Cycle " S t a r t Cycle 3" I n s t r u c t i o n f e t c h e m R e a d A L U S r c A = I o r D = I R W r i t e A L U S r c B = A L U O p = P C W r t e P C S o u r c e = B r a n c h c o m p l e t i o n E x e c u t o n 6 8 A L U S r c A = A L U S r c A = A L U S r c B = A L U S r c B = A L U O p = A L U O p = P C W r t e C o n d P C S o u r c e = I n s t r u c t i o n d e t c o d e / r e g i s t e r f e tc h i 9 A L U S r c A = A L U S r c B = A L U O p = ( O p = J ') J u m p c o m p l e t o n P C W r i t e P C S o u r c e = Cycle 2" 3 ( O p = ' L W ') e m o r y a c c e s s 5 e m o r y a c c e s s 7 R - t y p e c o m p l e t o n e m R e a d I o r D = e m W r i t e I o r D = R e g D s t = R e g W r i t e e m t o R e g = Cycle 4" 4 W r t e - b a c k s t e p R e g D s t = R e g W r i t e e m t o R e g = Cycle 5" 34!
35 ight also store control signals in RO! 2 3 e m o r y a d r e s s c o m p u t a t i o n A L U S r c A = A L U S r c B = A L U O p = ( O p = ' L W ') e m o r y a c c e s s e m R e a d I o r D = 5 S t a r t e m o r y a c c e s s e m W r i t e I o r D = 7 I n s t r u c t i o n f e t c h e m R e a d A L U S r c A = I o r D = I R W r i t e A L U S r c B = A L U O p = P C W r t e P C S o u r c e = 6 E x e c u t o n A L U S r c A = A L U S r c B = A L U O p = R e g D s t = R e g W r i t e e m t o R e g = R - t y p e c o m p l e t o n B r a n c h c o m p l e t i o n 8 A L U S r c A = A L U S r c B = A L U O p = P C W r t e C o n d P C S o u r c e = I n s t r u c t i o n d e t c o d e / r e g i s t e r f e tc h i 9 A L U S r c A = A L U S r c B = A L U O p = ' ) ( O p = J J u m p c o m p l e t o n P C W r i t e P C S o u r c e = Control Logic (in RO)! Input! Output! P"C"W" r"i"t"e" P"C"W" r"i"t"e"c"o"n"d" I"o"r"D" "e"m"r"e"a"d" "e"m"w" r"i"t"e" I"R"W" r"i"t"e" "e"m" t"o"r"e"g" P"C"S"o"u"r"c"e" A"L"U"O"p" A"L"U"S" r"c"b" A"L"U"S" r"c"a" R"e"g"W" r"i"t"e" R"e"g"D"s"t" N"S"3" N"S"2" N"S"" N"S"" 4 R e g D s t = R e g W r i t e e m t o R e g = W r t e - b a c k s t e p O"p"5" O"p"4" O"p"3" O"p"2" O"p"" O"p"" Instruction Register! Opcode Field! S"3" S"2" S"" S"" S" t"a"t"e" r"e"g" " i"s"t"e"r" 35!
36 Exceptions! Exceptions: unexpected events from within the processor! arithmetic overflow! undefined instruction! switching from user program to OS! Interrupts: unexpected events from outside of the processor! I/O request! Consequence: alter the normal flow of instruction execution! Key issues:! detection! action! save the address of the offending instruction in the EPC! transfer control to OS at some specified address! Exception type indication:! status register! interrupt vector! Another reason that register naming conventions are important.! 36!
37 FS with Exception Handling! 37!
38 Datapath with Exception Handling! 38!
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