L07-L09 recap: Fundamental lesson(s)!

Size: px
Start display at page:

Download "L07-L09 recap: Fundamental lesson(s)!"

Transcription

1 L7-L9 recap: Fundamental lesson(s)! Over the next 3 lectures (using the IPS ISA as context) I ll explain:! How functions are treated and processed in assembly! How system calls are enabled in assembly! How exceptions are handled in assembly! I ll also explain why it s important that register conventions be followed!!

2 L7-L9 recap: Why it s important! If you ever write a compiler or OS some day, you will need to be aware of, and code for all of the issues to be discussed over the next 3 lectures! If you understand what architectural overhead may be associated with (compiled) procedure calls, you should be able to write much more efficient HLL code! 2!

3 Lecture The IPS datapath! Suggested reading:! (HP Chapter )! 3!

4 Processor components! ulticore processors and programming! Processor comparison! vs.! Goal: describe the fundamental components required in a single core of a modern microprocessor as well as how they interact with each other, with main memory, and with external storage media." CSE 332! Writing more! efficient code! The right HW for the right application! HLL code translation! 4!

5 Fundamental lesson(s)! Today we ll discuss what hardware is required to execute an instruction, as well as how to best organize it.! 5!

6 Why it s important! If you ever design the HW for a microprocessor, etc. you'll need to be aware of these types of issues! Understanding organization and how it impacts the delay of something like a memory reference - will make you a better programmer!! It is now more and more important to design HW/SW simultaneously! 6!

7 The organization of a computer! Von Neumann odel:! Stored-program machine instructions are represented as numbers" Programs can be stored in memory to be read/written just like " numbers." Today" we ll talk" about these" things" Control" Compiler" emory" Input" Focus of lectures 5-9" Datapath" Output" Processor" 7!

8 Review: Functions of Each Component! Datapath: performs data manipulation operations! arithmetic logic unit (ALU)! floating point unit (FPU)! Control: directs operation of other components! finite state machines! micro-programming (to be discussed)! emory: stores instructions and data! random access v.s. sequential access! volatile v.s. non-volatile! RAs (SRA, DRA), ROs (PRO, EEPRO), disk! tradeoff between speed and cost/bit! Input/Output and I/O devices: interface to environment! mouse, keyboard, display, device drivers! 8!

9 Let s derive the IPS datapath:! To simplify things a bit we ll just look at a few instructions:! memory-reference: lw, sw! arithmetic-logical: add, sub, and, or, slt! branching: beq, j! Organizational overview:! fetch an instruction based on the content of PC! decode the instruction! fetch operands! (read one or two registers)! execute! (effective address calculation/arithmetic-logical operations/ comparison)! store result! (write to memory / write to register / update PC)! Very common" instructions" With Von Neumann, " RISC model do similar" things for each" instruction " A 9!

10 A Single Cycle Datapath! ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] Let s trace a few insturctions! add "$5, $6, $7" sw "($9), $" sub"$, $2, $3" lw "$, ($2)" Instruction [5 ] 6 Sign 32 extend ALU control!

11 PERFORANCE!!

12 Single-Cycle Implementation! Single-cycle, fixed-length clock:! CPI =! Clock cycle = propagation delay of the longest datapath operations among all instruction types! Easy to implement! How to determine cycle length?! Calculate cycle time assuming negligible delays except:! memory (2ns), ALU and adders (2ns), register file access (ns)! R-type:!max {mem + RF + ALU + RF, Add}!!!= 6ns! LW:!max{mem + RF + ALU + mem + RF, Add}!!= 8ns! SW:!max{mem + RF + ALU + mem, Add}!!!= 7ns! BEQ:!max{mem + RF + ALU, max{add, mem + Add}}!= 5ns! What is the CC time?! 2!

13 Before, spoke about multi-cycle datapath! Init PC= Fetch IR=I[PC] PC=PC+ Decode op= op= op= Load RF[ra]=D[d] Store D[d]=RF[ra] Add RF[ra] = RF[rb]+ RF[rc] 3!

14 The multi-cycle approach (& benefits):! Break an instruction into smaller steps! Execute each step in one cycle.! Execution sequence:! Balance amount of work to be done! Restrict each cycle to use only one major functional unit! At the end of a cycle! Store values for use in later cycles! Introduce additional internal registers! The advantages:! Cycle time much shorter! Diff. inst. take different # of cycles to complete! Functional unit used more than once per instruction! 4!

15 IPS multi-cycle datapath! Note introduction of temporary storage registers" 5!

16 5 steps an instruction could take:!. Instruction Fetch (Ifetch):! Fetch instruction at address ($PC)! Store the instruction in register IR! Increment PC! 2. Instruction Decode and Register (Decode):! Decode the instruction type and read register! Store the register contents in registers A and B! Compute new PC address and store it in ALUOut! 3. Execution, emory Address Computation, or Branch Completion (Execute):! Compute memory address (for LW and SW), or! Perform R-type operation (for R-type instruction), or! Update PC (for Branch and Jump)! Store memory address or register operation result in ALUOut! 6!

17 5 steps an instruction could take:! 4. emory Access or R-type instruction completion!!(em/regwrite/emwrite):! memory at address ALUOut and store it in DR! Write ALUOut content into register file, or! Write memory at address ALUOut with the value in B! 5. Write-back step (WrBack):! Write the memory content read into register file! Number of cycles for an instruction:! R-type: 4! lw: 5! sw: 4! Branch or Jump: 3 7!

18 Instruction execution (summary):! Action for R-type Action for memory-reference Action for Action for Step name instructions instructions branches jumps Instruction fetch IR = em[pc], PC = PC + 4 Instruction A =RF [IR[25:2]], decode/register fetch B = RF [IR[2:6]], ALUOut = PC + (sign-extend (IR[:-]) << 2) Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A =B) then PC = PC [3:28] computation, branch/ (IR[5:]) PC = ALUOut (IR[25:]<<2) jump completion emory access or R-type RF [IR[5:]] = Load: DR = em[aluout] completion ALUOut or Store: em[aluout]= B emory read completion Load: RF[IR[2:6]] = DR 8!

19 Some questions:! How many cycles will it take to execute this code?!!!!lw $t2, ($t3)!!!lw $t3, 4($t3)!!!beq $t2, $t3, Label #assume branch is not taken!!!add $t5, $t2, $t3!!!sw $t5, 8($t3) Label:!...!! =2! What is being done during the 8th cycle of execution?!!!compute memory address: 4 + content of $t3! In what cycle does the addition of $t2 and $t3 takes place?!!6!! How would performance compare if multi-cycle clock period is 2 ns and cycle cycle period is ns?!!!(2 CCs x 2 ns) vs. (5 CCs x ns):!!42 ns vs. 5 ns!! 9!

20 Foreshadowing: pipelines! Note: Some extra HW needed.! Data must be stored from one stage to the next in pipeline registers/latches.! hold temporary values between clocks and needed info. for execution.! 2!

21 Another way to look at it! Clock Number! Inst. #!! 2! 3! 4! 5! 6! 7! 8! Inst. i! IF! ID! EX! E! WB! Inst. i+! IF! ID! EX! E! WB! Inst. i+2! IF! ID! EX! E! WB! Inst. i+3! IF! ID! EX! E! WB! Program execution order (in instructions)! ALU! I! Reg! D! Reg! ALU! I! Reg! D! Reg! ALU! I! Reg! D! Reg! ALU! Time! I! Reg! D! Reg! 2!

22 (Tying computer architecture to logic design )! A SHORT DISCUSSION ABOUT CONTROL LOGIC! 22!

23 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control When we talk about control," we talk about these blocks" Instruction [5 ] 23!

24 Single cycle control: inputs & outputs! Step :! Identify inputs & outputs" Control Inputs:! Opcode (6 bits)! How about R-type instructions?! Control Outputs:! RegDst! ALUSrc! emtoreg! RegWrite! em! emwrite! Branch! Jump! ALUctr! columns! rows! Step 2:! ake a control signal" table for each cycle" 24!

25 Control Signal Table! R-type! (inputs)! Add! Sub! LW! SW! BEQ! Func (input)!!! xxxxxx! xxxxxx! xxxxxx! Op (input)!!!!!! RegDst!!!! X! X! ALUSrc!!!!!! em-to-reg!!!! X! X! Reg. Write!!!!!! em.!!!!!! em. Write!!!!!! Branch!!!!!! ALUOp! Add! Sub!!!! (outputs)! 25!

26 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control For IPS, we have to" build a ain Control Block" and an ALU Control Block" Instruction [5 ] 26!

27 ain control, ALU control! OP! 6" (opcode)! ain! Control" Func! ALUOp" 6" 2" Other control" signals" ALU! Control" ALUctr! 3" ALU" Our 2 blocks! of control logic! Use OP field to generate ALUOp (encoding)! Control signal fed to ALU control block! Use Func field and ALUOp to generate ALUctr (decoding)! Specifically sets 3 ALU control signals! B-Invert, Carry-in, operation! 27!

28 ain control, ALU control! OP! 6" ain! Control" ALUOp" 2" Func! 6" ALU! Control" ALUctr! 3" ALU" Outputs of main control,! become inputs to ALU control! R-type! lw! sw! beq! ALU Operation! R-type! add! add! subtract! ALUOp<:>!!!!! We have 8 bits" of input to our ALU control" block; we need 3 bits of" output " Or in other words! = ALU performs add! = ALU performs sub! = ALU does what function code says! 28!

29 Generating ALUctr! We want these outputs:! ALU Operation! and! or! add! sub! slt! ALUctr<2:>!!!!!! mux! ALUctr<2> = B-negate (C-in & B-invert)" ALUctr<> = Select ALU Output" ALUctr<> = Select ALU Output" Invert B and C-in must be a for subtract" and -! or -! adder -! less -! We have these inputs! func<5:>! 36 (and)!=! 37 (or)!=! 32 (add)!=! 34 (sub)!=! 42 (slt)!=! can ignore these bits! (they re the same for all )! lw/sw! beq! R-type! Inputs" Outputs" ALUOp" Funct field" ALUctr" ALUOp" ALUOp" F5" F4" F3" F2" F" F" " " X" X" X" X" X" X" (add)! " " X" X" X" X" X" X" (sub)! " X" X" X" " " " " (add)! " X" X" X" " " " " (sub)! " X" X" X" " " " " (and)! " X" X" X" " " " " (or)! " X" X" X" " " " " (slt)! 29"

30 The logic:! This table is used to generate the actual Boolean logic gates that produce ALUctr." Could generate gates by hand, often done w/sw." (func<5:>) F2 F (ALUOp) /X /X F3 /X ALUOp ALUOp lw/sw! beq! R-type! X/ / and and or F /X /X / ALUOp" Funct field" ALUctr" ALUOp" ALUOp" F5" F4" F3" F2" F" F" " " X" X" X" X" X" X" (add)! " " X" X" X" X" X" X" (sub)! " X" X" X" " " " " (add)! " X" X" X" " " " " (sub)! " X" X" X" " " " " (and)! " X" X" X" " " " " (or)! " X" X" X" " " " " (slt)! ALUctr<2> or / / or Inputs" ALUctr<> / ALUctr<> / ALUctr / Ex: ALUctr<2> (SUB/BEQ) Outputs" 3!

31 The HW needed, plus control! Single cycle IPS machine" ux 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control For IPS, we have to" build a ain Control Block" and an ALU Control Block" Instruction [5 ] 3!

32 Well, here s what we did! Single cycle IPS machine" ux We came up with the information to generate this logic which would fit here in the datapath." 4 Add Instruction [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add result ALU PCSrc PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] ux register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x Instruction [5 ] 6 Sign 32 extend ALU control (ALUOp) F3 ALUOp ALUOp and or ALUctr<2> Instruction [5 ] (func<5:>) F2 or ALUctr<> ALUctr F F or and ALUctr<> 32!

33 Controller FS for 6-instruction processor! Recall:! With multi-cycle, need to generate control signals at right time" Captured by FS" Each level analogous to CC" " Init PC_clr= Fetch I _rd= PC_inc= I R_ld= Decode op= op= op= op= op= op= Load D_addr=d D_rd= RF_s = R F _ s = RF_W_addr=ra RF_W_wr= Store D_addr=d D_wr= RF_s = X RF_s = X RF_Rp_addr=ra RF_Rp_rd= Add RF_Rp_addr=rb RF_Rp_rd= RF_s = RF_s = RF_Rq_add=rc RF_Rq_rd= RF_W_addr_ra RF_W_wr= alu_s = alu_s = Loadconstant RF_s= RF_s= RF_W_addr=ra RF_W_wr= Subtract RF_Rp_addr=rb RF_Rp_rd= RF_s= RF_s= RF_Rq_addr=rc RF_Rq_rd= RF_W_addr=ra RF_W_wr= alu_s= alu_s= RF_Rp_zero Jump-if-zero RF_Rp_addr=ra RF_Rp_rd= Jump-ifzero-jmp PC_ld= RF_Rp_zero' 33!

34 IPS FS diagram! 2 e m o r y a d r e s s c o m p u t a t i o n A L U S r c A = A L U S r c B = A L U O p = Cycle " S t a r t Cycle 3" I n s t r u c t i o n f e t c h e m R e a d A L U S r c A = I o r D = I R W r i t e A L U S r c B = A L U O p = P C W r t e P C S o u r c e = B r a n c h c o m p l e t i o n E x e c u t o n 6 8 A L U S r c A = A L U S r c A = A L U S r c B = A L U S r c B = A L U O p = A L U O p = P C W r t e C o n d P C S o u r c e = I n s t r u c t i o n d e t c o d e / r e g i s t e r f e tc h i 9 A L U S r c A = A L U S r c B = A L U O p = ( O p = J ') J u m p c o m p l e t o n P C W r i t e P C S o u r c e = Cycle 2" 3 ( O p = ' L W ') e m o r y a c c e s s 5 e m o r y a c c e s s 7 R - t y p e c o m p l e t o n e m R e a d I o r D = e m W r i t e I o r D = R e g D s t = R e g W r i t e e m t o R e g = Cycle 4" 4 W r t e - b a c k s t e p R e g D s t = R e g W r i t e e m t o R e g = Cycle 5" 34!

35 ight also store control signals in RO! 2 3 e m o r y a d r e s s c o m p u t a t i o n A L U S r c A = A L U S r c B = A L U O p = ( O p = ' L W ') e m o r y a c c e s s e m R e a d I o r D = 5 S t a r t e m o r y a c c e s s e m W r i t e I o r D = 7 I n s t r u c t i o n f e t c h e m R e a d A L U S r c A = I o r D = I R W r i t e A L U S r c B = A L U O p = P C W r t e P C S o u r c e = 6 E x e c u t o n A L U S r c A = A L U S r c B = A L U O p = R e g D s t = R e g W r i t e e m t o R e g = R - t y p e c o m p l e t o n B r a n c h c o m p l e t i o n 8 A L U S r c A = A L U S r c B = A L U O p = P C W r t e C o n d P C S o u r c e = I n s t r u c t i o n d e t c o d e / r e g i s t e r f e tc h i 9 A L U S r c A = A L U S r c B = A L U O p = ' ) ( O p = J J u m p c o m p l e t o n P C W r i t e P C S o u r c e = Control Logic (in RO)! Input! Output! P"C"W" r"i"t"e" P"C"W" r"i"t"e"c"o"n"d" I"o"r"D" "e"m"r"e"a"d" "e"m"w" r"i"t"e" I"R"W" r"i"t"e" "e"m" t"o"r"e"g" P"C"S"o"u"r"c"e" A"L"U"O"p" A"L"U"S" r"c"b" A"L"U"S" r"c"a" R"e"g"W" r"i"t"e" R"e"g"D"s"t" N"S"3" N"S"2" N"S"" N"S"" 4 R e g D s t = R e g W r i t e e m t o R e g = W r t e - b a c k s t e p O"p"5" O"p"4" O"p"3" O"p"2" O"p"" O"p"" Instruction Register! Opcode Field! S"3" S"2" S"" S"" S" t"a"t"e" r"e"g" " i"s"t"e"r" 35!

36 Exceptions! Exceptions: unexpected events from within the processor! arithmetic overflow! undefined instruction! switching from user program to OS! Interrupts: unexpected events from outside of the processor! I/O request! Consequence: alter the normal flow of instruction execution! Key issues:! detection! action! save the address of the offending instruction in the EPC! transfer control to OS at some specified address! Exception type indication:! status register! interrupt vector! Another reason that register naming conventions are important.! 36!

37 FS with Exception Handling! 37!

38 Datapath with Exception Handling! 38!

CSE Computer Architecture I

CSE Computer Architecture I Execution Sequence Summary CSE 30321 Computer Architecture I Lecture 17 - Multi Cycle Control Michael Niemier Department of Computer Science and Engineering Step name Instruction fetch Instruction decode/register

More information

Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle

Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory

More information

Review. Combined Datapath

Review. Combined Datapath Review Topics:. A single cycle implementation 2. State Diagrams. A mltiple cycle implementation COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot

More information

CPU DESIGN The Single-Cycle Implementation

CPU DESIGN The Single-Cycle Implementation CSE 202 Computer Organization CPU DESIGN The Single-Cycle Implementation Shakil M. Khan (adapted from Prof. H. Roumani) Dept of CS & Eng, York University Sequential vs. Combinational Circuits Digital circuits

More information

Processor Design & ALU Design

Processor Design & ALU Design 3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of

More information

Project Two RISC Processor Implementation ECE 485

Project Two RISC Processor Implementation ECE 485 Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor

More information

Designing MIPS Processor

Designing MIPS Processor CSE 675.: Introdction to Compter Architectre Designing IPS Processor (lti-cycle) Presentation H Reading Assignment: 5.5,5.6 lti-cycle Design Principles Break p eection of each instrction into steps. The

More information

Topics: A multiple cycle implementation. Distributed Notes

Topics: A multiple cycle implementation. Distributed Notes COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot # lticycle Implementation of a IPS Processor Topics: A mltiple cycle implementation Distribted

More information

Instruction register. Data. Registers. Register # Memory data register

Instruction register. Data. Registers. Register # Memory data register Where we are headed Single Cycle Problems: what if we had a more complicated instrction like floating point? wastefl of area One Soltion: se a smaller cycle time have different instrctions take different

More information

Pipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2

Pipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2 Pipelining CS 365 Lecture 12 Prof. Yih Huang CS 365 1 Traditional Execution 1 2 3 4 1 2 3 4 5 1 2 3 add ld beq CS 365 2 1 Pipelined Execution 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5

More information

Implementing the Controller. Harvard-Style Datapath for DLX

Implementing the Controller. Harvard-Style Datapath for DLX 6.823, L6--1 Implementing the Controller Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 6.823, L6--2 Harvard-Style Datapath for DLX Src1 ( j / ~j ) Src2 ( R / RInd) RegWrite MemWrite

More information

Simple Instruction-Pipelining (cont.) Pipelining Jumps

Simple Instruction-Pipelining (cont.) Pipelining Jumps 6.823, L9--1 Simple ruction-pipelining (cont.) + Interrupts Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Src1 ( j / ~j ) Src2 ( / Ind) Pipelining Jumps

More information

Spiral 1 / Unit 3

Spiral 1 / Unit 3 -3. Spiral / Unit 3 Minterm and Maxterms Canonical Sums and Products 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Function Synthesis use Canonical Sums/Products -3.2 Outcomes I know the

More information

EC 413 Computer Organization

EC 413 Computer Organization EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks

More information

Lecture 9: Control Hazard and Resolution. James C. Hoe Department of ECE Carnegie Mellon University

Lecture 9: Control Hazard and Resolution. James C. Hoe Department of ECE Carnegie Mellon University 18 447 Lectre 9: Control Hazard and Resoltion James C. Hoe Department of ECE Carnegie ellon University 18 447 S18 L09 S1, James C. Hoe, CU/ECE/CALC, 2018 Yor goal today Hosekeeping simple control flow

More information

Lecture 13: Sequential Circuits, FSM

Lecture 13: Sequential Circuits, FSM Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines 1 Clocks A microprocessor is composed of many different circuits that are operating simultaneously if each

More information

CSCI-564 Advanced Computer Architecture

CSCI-564 Advanced Computer Architecture CSCI-564 Advanced Computer Architecture Lecture 8: Handling Exceptions and Interrupts / Superscalar Bo Wu Colorado School of Mines Branch Delay Slots (expose control hazard to software) Change the ISA

More information

3. (2) What is the difference between fixed and hybrid instructions?

3. (2) What is the difference between fixed and hybrid instructions? 1. (2 pts) What is a "balanced" pipeline? 2. (2 pts) What are the two main ways to define performance? 3. (2) What is the difference between fixed and hybrid instructions? 4. (2 pts) Clock rates have grown

More information

Lecture 13: Sequential Circuits, FSM

Lecture 13: Sequential Circuits, FSM Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,

More information

ECE290 Fall 2012 Lecture 22. Dr. Zbigniew Kalbarczyk

ECE290 Fall 2012 Lecture 22. Dr. Zbigniew Kalbarczyk ECE290 Fall 2012 Lecture 22 Dr. Zbigniew Kalbarczyk Today LC-3 Micro-sequencer (the control store) LC-3 Micro-programmed control memory LC-3 Micro-instruction format LC -3 Micro-sequencer (the circuitry)

More information

Simple Instruction-Pipelining. Pipelined Harvard Datapath

Simple Instruction-Pipelining. Pipelined Harvard Datapath 6.823, L8--1 Simple ruction-pipelining Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. fetch decode & eg-fetch execute

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital

More information

Control. Control. the ALU. ALU control signals 11/4/14. Next: control. We built the instrument. Now we read music and play it...

Control. Control. the ALU. ALU control signals 11/4/14. Next: control. We built the instrument. Now we read music and play it... // CS 2, Fall 2! CS 2, Fall 2! We built the instrument. Now we read music and play it... A simple implementa/on uc/on uct r r 2 Write r Src Src Extend 6 Mem Next: path 7-2 CS 2, Fall 2! signals CS 2, Fall

More information

[2] Predicting the direction of a branch is not enough. What else is necessary?

[2] Predicting the direction of a branch is not enough. What else is necessary? [2] When we talk about the number of operands in an instruction (a 1-operand or a 2-operand instruction, for example), what do we mean? [2] What are the two main ways to define performance? [2] Predicting

More information

Simple Instruction-Pipelining. Pipelined Harvard Datapath

Simple Instruction-Pipelining. Pipelined Harvard Datapath 6.823, L8--1 Simple ruction-pipelining Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. I fetch decode & eg-fetch execute memory Clock period

More information

Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS222: Processor Design: Multi Cycle Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Mid Semester Exam Multi Cycle design Outline Clock periods in single cycle and

More information

[2] Predicting the direction of a branch is not enough. What else is necessary?

[2] Predicting the direction of a branch is not enough. What else is necessary? [2] What are the two main ways to define performance? [2] Predicting the direction of a branch is not enough. What else is necessary? [2] The power consumed by a chip has increased over time, but the clock

More information

Computer Architecture ELEC2401 & ELEC3441

Computer Architecture ELEC2401 & ELEC3441 Last Time Pipeline Hazard Computer Architecture ELEC2401 & ELEC3441 Lecture 8 Pipelining (3) Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Structural Hazard Hazard Control

More information

1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished?

1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished? 1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished? 2. (2 )What are the two main ways to define performance? 3. (2 )What

More information

Designing Single-Cycle MIPS Processor

Designing Single-Cycle MIPS Processor CSE 32: Introdction to Compter Architectre Designing Single-Cycle IPS Processor Presentation G Stdy:.-. Gojko Babić 2/9/28 Introdction We're now ready to look at an implementation of the system that incldes

More information

Lecture 12: Pipelined Implementations: Control Hazards and Resolutions

Lecture 12: Pipelined Implementations: Control Hazards and Resolutions 18-447 Lectre 12: Pipelined Implementations: Control Hazards and Resoltions S 09 L12-1 James C. Hoe Dept of ECE, CU arch 2, 2009 Annoncements: Spring break net week!! Project 2 de the week after spring

More information

Design of Digital Circuits Lecture 14: Microprogramming. Prof. Onur Mutlu ETH Zurich Spring April 2017

Design of Digital Circuits Lecture 14: Microprogramming. Prof. Onur Mutlu ETH Zurich Spring April 2017 Design of Digital Circuits Lecture 4: Microprogramming Prof. Onur Mutlu ETH Zurich Spring 27 7 April 27 Agenda for Today & Next Few Lectures! Single-cycle Microarchitectures! Multi-cycle and Microprogrammed

More information

ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference)

ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference) ECE 3401 Lecture 23 Pipeline Design Control State Register Combinational Control Logic New/ Modified Control Word ISA: Instruction Specifications (for reference) P C P C + 1 I N F I R M [ P C ] E X 0 PC

More information

Lecture 3, Performance

Lecture 3, Performance Lecture 3, Performance Repeating some definitions: CPI Clocks Per Instruction MHz megahertz, millions of cycles per second MIPS Millions of Instructions Per Second = MHz / CPI MOPS Millions of Operations

More information

CSE Computer Architecture I

CSE Computer Architecture I Single cycle Conrol Implemenaion CSE 332 Compuer Archiecure I l x I Lecure 7 - uli Cycle achines i i [ ] I I r l ichael Niemier Deparmen of Compuer Science and Engineering I ] i X.S. Hu 5- X.S. Hu 5-2

More information

NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1

NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 Multi-processor vs. Multi-computer architecture µp vs. DSP RISC vs. DSP RISC Reduced-instruction-set Register-to-register operation Higher throughput by using

More information

4. (3) What do we mean when we say something is an N-operand machine?

4. (3) What do we mean when we say something is an N-operand machine? 1. (2) What are the two main ways to define performance? 2. (2) When dealing with control hazards, a prediction is not enough - what else is necessary in order to eliminate stalls? 3. (3) What is an "unbalanced"

More information

CMP 334: Seventh Class

CMP 334: Seventh Class CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative

More information

INF2270 Spring Philipp Häfliger. Lecture 8: Superscalar CPUs, Course Summary/Repetition (1/2)

INF2270 Spring Philipp Häfliger. Lecture 8: Superscalar CPUs, Course Summary/Repetition (1/2) INF2270 Spring 2010 Philipp Häfliger Summary/Repetition (1/2) content From Scalar to Superscalar Lecture Summary and Brief Repetition Binary numbers Boolean Algebra Combinational Logic Circuits Encoder/Decoder

More information

CPSC 3300 Spring 2017 Exam 2

CPSC 3300 Spring 2017 Exam 2 CPSC 3300 Spring 2017 Exam 2 Name: 1. Matching. Write the correct term from the list into each blank. (2 pts. each) structural hazard EPIC forwarding precise exception hardwired load-use data hazard VLIW

More information

Computer Architecture. ECE 361 Lecture 5: The Design Process & ALU Design. 361 design.1

Computer Architecture. ECE 361 Lecture 5: The Design Process & ALU Design. 361 design.1 Computer Architecture ECE 361 Lecture 5: The Design Process & Design 361 design.1 Quick Review of Last Lecture 361 design.2 MIPS ISA Design Objectives and Implications Support general OS and C- style language

More information

CMP N 301 Computer Architecture. Appendix C

CMP N 301 Computer Architecture. Appendix C CMP N 301 Computer Architecture Appendix C Outline Introduction Pipelining Hazards Pipelining Implementation Exception Handling Advanced Issues (Dynamic Scheduling, Out of order Issue, Superscalar, etc)

More information

61C In the News. Processor Design: 5 steps

61C In the News. Processor Design: 5 steps www.eetimes.com/electronics-news/23235/thailand-floods-take-toll-on--makers The Thai floods have already claimed the lives of hundreds of pele, with tens of thousands more having had to flee their homes

More information

From Sequential Circuits to Real Computers

From Sequential Circuits to Real Computers 1 / 36 From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2017 2 / 36 Introduction What we

More information

UNIVERSITY OF WISCONSIN MADISON

UNIVERSITY OF WISCONSIN MADISON CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,

More information

Lecture 3, Performance

Lecture 3, Performance Repeating some definitions: Lecture 3, Performance CPI MHz MIPS MOPS Clocks Per Instruction megahertz, millions of cycles per second Millions of Instructions Per Second = MHz / CPI Millions of Operations

More information

Latches. October 13, 2003 Latches 1

Latches. October 13, 2003 Latches 1 Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory

More information

Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers

Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers -2. -2.2 piral / Unit 2 Basic Boolean Algebra Logic Functions Decoders Multipleers Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name eamples of each.

More information

TEST 1 REVIEW. Lectures 1-5

TEST 1 REVIEW. Lectures 1-5 TEST 1 REVIEW Lectures 1-5 REVIEW Test 1 will cover lectures 1-5. There are 10 questions in total with the last being a bonus question. The questions take the form of short answers (where you are expected

More information

Building a Computer. Quiz #2 on 10/31, open book and notes. (This is the last lecture covered) I wonder where this goes? L16- Building a Computer 1

Building a Computer. Quiz #2 on 10/31, open book and notes. (This is the last lecture covered) I wonder where this goes? L16- Building a Computer 1 Building a Computer I wonder where this goes? B LU MIPS Kit Quiz # on /3, open book and notes (This is the last lecture covered) Comp 4 Fall 7 /4/7 L6- Building a Computer THIS IS IT! Motivating Force

More information

ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University

ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University Prof. Mi Lu TA: Ehsan Rohani Laboratory Exercise #4 MIPS Assembly and Simulation

More information

EXAMPLES 4/12/2018. The MIPS Pipeline. Hazard Summary. Show the pipeline diagram. Show the pipeline diagram. Pipeline Datapath and Control

EXAMPLES 4/12/2018. The MIPS Pipeline. Hazard Summary. Show the pipeline diagram. Show the pipeline diagram. Pipeline Datapath and Control The MIPS Pipeline CSCI206 - Computer Organization & Programming Pipeline Datapath and Control zybook: 11.6 Developed and maintained by the Bucknell University Computer Science Department - 2017 Hazard

More information

Microprocessor Power Analysis by Labeled Simulation

Microprocessor Power Analysis by Labeled Simulation Microprocessor Power Analysis by Labeled Simulation Cheng-Ta Hsieh, Kevin Chen and Massoud Pedram University of Southern California Dept. of EE-Systems Los Angeles CA 989 Outline! Introduction! Problem

More information

CS 52 Computer rchitecture and Engineering Lecture 4 - Pipelining Krste sanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste! http://inst.eecs.berkeley.edu/~cs52!

More information

Design of Sequential Circuits

Design of Sequential Circuits Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

More information

A Second Datapath Example YH16

A Second Datapath Example YH16 A Second Datapath Example YH16 Lecture 09 Prof. Yih Huang S365 1 A 16-Bit Architecture: YH16 A word is 16 bit wide 32 general purpose registers, 16 bits each Like MIPS, 0 is hardwired zero. 16 bit P 16

More information

CMP 338: Third Class

CMP 338: Third Class CMP 338: Third Class HW 2 solution Conversion between bases The TINY processor Abstraction and separation of concerns Circuit design big picture Moore s law and chip fabrication cost Performance What does

More information

Basic Computer Organization and Design Part 3/3

Basic Computer Organization and Design Part 3/3 Basic Computer Organization and Design Part 3/3 Adapted by Dr. Adel Ammar Computer Organization Interrupt Initiated Input/Output Open communication only when some data has to be passed --> interrupt. The

More information

Review: Single-Cycle Processor. Limits on cycle time

Review: Single-Cycle Processor. Limits on cycle time Review: Single-Cycle Processor Jump 3:26 5: MemtoReg Control Unit LUControl 2: Op Funct LUSrc RegDst PCJump PC 4 uction + PCPlus4 25:2 2:6 2:6 5: 5: 2 3 WriteReg 4: Src Src LU Zero LUResult Write + PC

More information

Logic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson

Logic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson Logic Deign CS 270: Mathematical Foundation of Computer Science Jeremy Johnon Logic Deign Objective: To provide an important application of propoitional logic to the deign and implification of logic circuit.

More information

COVER SHEET: Problem#: Points

COVER SHEET: Problem#: Points EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

CPU DESIGN The Single-Cycle Implementation

CPU DESIGN The Single-Cycle Implementation 22 ompter Organization Seqential vs. ombinational ircits Digital circits can be classified into two categories: DESIGN The Single-ycle Implementation. ombinational ircits: m, 2. Seqential ircits: flip-flops,

More information

ECE/CS 250 Computer Architecture

ECE/CS 250 Computer Architecture ECE/CS 250 Computer Architecture Basics of Logic Design: Boolean Algebra, Logic Gates (Combinational Logic) Tyler Bletsch Duke University Slides are derived from work by Daniel J. Sorin (Duke), Alvy Lebeck

More information

Arithmetic and Logic Unit First Part

Arithmetic and Logic Unit First Part Arithmetic and Logic Unit First Part Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ALU1-1 Typical

More information

Introduction to CMOS VLSI Design Lecture 1: Introduction

Introduction to CMOS VLSI Design Lecture 1: Introduction Introduction to CMOS VLSI Design Lecture 1: Introduction David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Introduction Integrated circuits: many transistors

More information

Mark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions

Mark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic

More information

Combinational vs. Sequential. Summary of Combinational Logic. Combinational device/circuit: any circuit built using the basic gates Expressed as

Combinational vs. Sequential. Summary of Combinational Logic. Combinational device/circuit: any circuit built using the basic gates Expressed as Summary of Combinational Logic : Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: www.seas.gwu.edu/~bhagiweb/cs3/ Combinational device/circuit: any circuit

More information

From Sequential Circuits to Real Computers

From Sequential Circuits to Real Computers From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2018 1 / 39 Introduction I What we have

More information

ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates

ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates ECE 250 / CPS 250 Computer Architecture Basics of Logic Design Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Andrew Hilton (Duke), Alvy Lebeck (Duke) Benjamin Lee (Duke), and Amir

More information

2

2 Computer System AA rc hh ii tec ture( 55 ) 2 INTRODUCTION ( d i f f e r e n t r e g i s t e r s, b u s e s, m i c r o o p e r a t i o n s, m a c h i n e i n s t r u c t i o n s, e t c P i p e l i n e E

More information

Numbers and Arithmetic

Numbers and Arithmetic Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu

More information

Enrico Nardelli Logic Circuits and Computer Architecture

Enrico Nardelli Logic Circuits and Computer Architecture Enrico Nardelli Logic Circuits and Computer Architecture Appendix B The design of VS0: a very simple CPU Rev. 1.4 (2009-10) by Enrico Nardelli B - 1 Instruction set Just 4 instructions LOAD M - Copy into

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

VHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES

VHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES VHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES 1.Devarasetty Vinod Kumar/ M.tech,2. Dr. Tata Jagannadha Swamy/Professor, Dept of Electronics and Commn. Engineering, Gokaraju Rangaraju

More information

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit Digital Techniques 1. Binary System The digital computer is the best example of a digital system. A main characteristic of digital system is its ability to manipulate discrete elements of information.

More information

ALU A functional unit

ALU A functional unit ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes

CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN

More information

Computer Architecture

Computer Architecture Computer Architecture QtSpim, a Mips simulator S. Coudert and R. Pacalet January 4, 2018..................... Memory Mapping 0xFFFF000C 0xFFFF0008 0xFFFF0004 0xffff0000 0x90000000 0x80000000 0x7ffff4d4

More information

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits. CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!

More information

Administrivia. Course Objectives. Overview. Lecture Notes Week markem/cs333/ 2. Staff. 3. Prerequisites. 4. Grading. 1. Theory and application

Administrivia. Course Objectives. Overview. Lecture Notes Week markem/cs333/ 2. Staff. 3. Prerequisites. 4. Grading. 1. Theory and application Administrivia 1. markem/cs333/ 2. Staff 3. Prerequisites 4. Grading Course Objectives 1. Theory and application 2. Benefits 3. Labs TAs Overview 1. What is a computer system? CPU PC ALU System bus Memory

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19

More information

CS61C : Machine Structures

CS61C : Machine Structures CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS

More information

Formal Verification of Systems-on-Chip

Formal Verification of Systems-on-Chip Formal Verification of Systems-on-Chip Wolfgang Kunz Department of Electrical & Computer Engineering University of Kaiserslautern, Germany Slide 1 Industrial Experiences Formal verification of Systems-on-Chip

More information

Verilog HDL:Digital Design and Modeling. Chapter 11. Additional Design Examples. Additional Figures

Verilog HDL:Digital Design and Modeling. Chapter 11. Additional Design Examples. Additional Figures Chapter Additional Design Examples Verilog HDL:Digital Design and Modeling Chapter Additional Design Examples Additional Figures Chapter Additional Design Examples 2 Page 62 a b y y 2 y 3 c d e f Figure

More information

Computer Architecture

Computer Architecture Lecture 2: Iakovos Mavroidis Computer Science Department University of Crete 1 Previous Lecture CPU Evolution What is? 2 Outline Measurements and metrics : Performance, Cost, Dependability, Power Guidelines

More information

System Data Bus (8-bit) Data Buffer. Internal Data Bus (8-bit) 8-bit register (R) 3-bit address 16-bit register pair (P) 2-bit address

System Data Bus (8-bit) Data Buffer. Internal Data Bus (8-bit) 8-bit register (R) 3-bit address 16-bit register pair (P) 2-bit address Intel 8080 CPU block diagram 8 System Data Bus (8-bit) Data Buffer Registry Array B 8 C Internal Data Bus (8-bit) F D E H L ALU SP A PC Address Buffer 16 System Address Bus (16-bit) Internal register addressing:

More information

Binary addition example worked out

Binary addition example worked out Binary addition example worked out Some terms are given here Exercise: what are these numbers equivalent to in decimal? The initial carry in is implicitly 0 1 1 1 0 (Carries) 1 0 1 1 (Augend) + 1 1 1 0

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS

More information

CMU Introduction to Computer Architecture, Spring 2015 HW 2: ISA Tradeoffs, Microprogramming and Pipelining

CMU Introduction to Computer Architecture, Spring 2015 HW 2: ISA Tradeoffs, Microprogramming and Pipelining CMU 18-447 Introduction to Computer Architecture, Spring 2015 HW 2: ISA Tradeoffs, Microprogramming and Pipelining Instructor: Prof Onur Mutlu TAs: Rachata Ausavarungnirun, Kevin Chang, Albert Cho, Jeremie

More information

Pipelined Datapath. Reading. Sections Practice Problems: 1, 3, 8, 12 (2) Lecture notes from MKP, H. H. Lee and S.

Pipelined Datapath. Reading. Sections Practice Problems: 1, 3, 8, 12 (2) Lecture notes from MKP, H. H. Lee and S. Pipelined Datapath Lectre notes from KP, H. H. Lee and S. Yalamanchili Sections 4.5 4. Practice Problems:, 3, 8, 2 Reading (2) Pipeline Performance Assme time for stages is v ps for register read or write

More information

ICS 233 Computer Architecture & Assembly Language

ICS 233 Computer Architecture & Assembly Language ICS 233 Computer Architecture & Assembly Language Assignment 6 Solution 1. Identify all of the RAW data dependencies in the following code. Which dependencies are data hazards that will be resolved by

More information

Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995

Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1 Technology Trends: Microprocessor Capacity 100000000 10000000 Pentium Transistors 1000000

More information

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control Logic and Computer Design Fundamentals Chapter 8 Sequencing and Control Datapath and Control Datapath - performs data transfer and processing operations Control Unit - Determines enabling and sequencing

More information

Digital Design. Register Transfer Specification And Design

Digital Design. Register Transfer Specification And Design Principles Of Digital Design Chapter 8 Register Transfer Specification And Design Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential

More information

Lecture: Pipelining Basics

Lecture: Pipelining Basics Lecture: Pipelining Basics Topics: Performance equations wrap-up, Basic pipelining implementation Video 1: What is pipelining? Video 2: Clocks and latches Video 3: An example 5-stage pipeline Video 4:

More information

Load. Load. Load 1 0 MUX B. MB select. Bus A. A B n H select S 2:0 C S. G select 4 V C N Z. unit (ALU) G. Zero Detect.

Load. Load. Load 1 0 MUX B. MB select. Bus A. A B n H select S 2:0 C S. G select 4 V C N Z. unit (ALU) G. Zero Detect. 9- Write D data Load eable A address A select B address B select Load R 2 2 Load Load R R2 UX 2 3 UX 2 3 2 3 Decoder D address 2 Costat i Destiatio select 28 Pearso Educatio, Ic.. orris ao & Charles R.

More information

Hakim Weatherspoon CS 3410 Computer Science Cornell University

Hakim Weatherspoon CS 3410 Computer Science Cornell University Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. memory inst 32 register

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 752 Advanced Computer Architecture I.

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 752 Advanced Computer Architecture I. Last (family) name: Solution First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 752 Advanced Computer Architecture I Midterm

More information

Design at the Register Transfer Level

Design at the Register Transfer Level Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic

More information