Digital System Clocking: High-Performance and Low-Power Aspects. Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M.

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1 Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003

2 Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 2

3 Clock Frequency of Selected Historic Computers and Supercomputers System Intro Date Technology Class Nominal Clock Period (ns) Nominal Clock Frequency (MHz) Cray-X-MP Cray-1S,-1M CDC Cyber 180/990 IBM 3090 Amdahl 58 IBM 308X Univac 1100/90 MIPS-X HP-900 Motorola Bellmac-32A MSI ECL MSI ECL ECL ECL LSI ECL LSI TTL LSI ECL VLSI CMOS VLSI CMOS VLSI CMOS VLSI CMOS Vector Processor Vector Processor Mainframe Mainframe Mainframe Mainframe Mainframe Microprocessor Micro-mainframe Microprocessor Microprocessor , , Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 3

4 The concept of Finite-State Machine: FSM (Hoffman Model) Inputs (X) Combinational Logic Outputs (Y) Y=Y(X, S n ) Clocked Storage Elements Present State: S n Clock Next State S n+1 S n+1 = f (S n, X) Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 4

5 Another Representation of FSM Clocked Storage Elements: Flip-Flops and Latches should be viewed as synchronization elements, not merely as storage elements! Their main purpose is to synchronize fast and slow paths: prevent the fast path from corrupting the state Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 5

6 Another Representation of FSM Clocked Storage Elements: Flip-Flops and Latches should be viewed as synchronization elements, not merely as storage elements! Their main purpose is to synchronize fast and slow paths: prevent the fast path from corrupting the state Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 6

7 State Changes in the Finite-State Machine X t Combinational Y t X t+1 Combinational Y t+1 Logic Logic S n S n+1 Clock U D CQ U D CQ Y = S n-1 S n S n+1 Time Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 7

8 Diagram of a Pipelined System IAR Instr. Cache IR Register File Decode ALU Data Cache Register File WA Instruction Fetch Decode Execute Cache Access Write Back φ φ 0 1 φ0 φ1 φ0 φ1 φ0 φ1 φ0 φ1 WRITE READ Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 8

9 Machine Execution Phases with Respect to the Machine Cycle: Clock Cycles MC-0 MC-1 Instruction Fetch Dependency Resolution MC-2 Instruction Issue Clocks: Φ 0 Φ 1 Block Address Instruction Cache Cache Block Rename and Allocate Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 9

10 Increase in the Clock Frequency and Decrease in the Number of Logic Levels 10,000 1,000 Mhz 100 Intel IBM Power PC DEC Gate delays/clock P6 601, 603 Pentium(R) 21264S 21164A A MPC Processor Freq scales 2X per technology generation Pentium(R) II Pentium III Gate Delays/Clock Period Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 10

11 System clocking schemes: (a) single-phase clock; (b) two-phase clock; (c) multiple-phase clock Clk (a) φ 1 φ 2 (b) φ 1 φ 2 φ 3 φ 4 φ k

12 Local generation of Two-Phase Clocks as used in IBM S/390 G4 CLKG C1 A_CLK SCAN_IN IN L1 L2 Q (SCAN_OUT) C2 B_CLK CLKG C2_ENABLE C2 C1_DISABLE C1 Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 12

13 V DD Out Control voltage Temperature Sensor Compenstation Network (a) (a) Crystal oscillator (b) (b) Temperature-compensated crystal oscillator

14 On-Chip Clock Insertion Delay ext. Clk Clock driver int. Clk D Clk Insertion delay D Clk Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 14

15 Phase-Locked Loop Block Diagram and Operation PLL Clock driver ext. Clk PD p cv VCO C load LP C load int. Clk C load ext. Clk int. Clk p cv 135 o out of phase 45 o out of phase Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 15

16 Delay-Locked Loop Block Diagram and Operation DLL ext. Clk PD p cv Clock driver LP C load VCDL C load int. Clk C load ext. Clk int. Clk p cv 135 o out of phase 45 o out of phase Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 16

17 PLL Frequency Multiplication PLL ext. Clk A PD LP VCO B Clock driver Cload C int. Clk f C = f A int. Clk ext. Clk Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 17

18 Ring-Oscillator-Based VCO with CMOS Inverters as Delay Elements V reg 1 n= 2k+ 1 T inv f osc 1 = ; k 1 2nT inv Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 18

19 LC Tank-Based VCO, Equivalent AC Circuit Model and Current Waveform L it () C L Req C I tail I tail I tail Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 19

20 Clock Parameters: Period (T), Width, Rise and Fall Times t rise t fall Clock W w = W T - duty cycle T Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 20

21 Clock Parameters: Period, Width, Clock Skew and Clock Jitter t DRVCLK Ref_Clock t skew t skew t + jit t jit Received Clock T t RCVCLK Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 21

22 Clock Uncertainties t DRV_CLK Ref_Clock t skew t skew t jit t + jit Received Clock trcv_clk T Clock uncertainty: jitter+skew Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 22

23 The Concept of Logic Islands (Wagner 1988), Copyright 1988 IEEE Island 1 Island 2 Crystal Oscillator Divide, shape, and buffer Island 4 Shape and buffer Island 3 Subisland A Subisland B Subisland C Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 23

24 Clock Tuning Points (Wagner 1988), Copyright 1988 IEEE System Oscillator Clock divider/buffer-- Observation point 0 Delay element Tuning delay - Tune-point level 1 Delay in clock-waveform manipulation + cable delay to on-board input On-board clock-control chip Tuning delay- Tune-point level 2 Clock-control chip clock gating + clock-chopping delay Clock-distribution chip Tuning delay- Tune-point level 3 Clock-distribution chip Clock-powering delay On-chip delay Bistable-element clock-input delay Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 24

25 Various Clock Shaping Elements and Obtained Clock Signals. (Wagner 1988), Copyright 1988 IEEE Clock In Clock In Clock In Clock In Element A delay = d g delay = D delay = d i Element B Element C Element D Clock Out Clock Out Clock Out Clock Out (a) Positive pulse Input Clock O W Time Chop (Element A) D+d 1 Shrink (Element C) Chop (Element D) d 2 D+d 2 d 2 W-D W+D Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 25 (b)

26 Crystal Oscillator Clock distribution network within a system, (b) on the board, and (c) tuning of the clock. (Wagner 1988), Copyright 1988 IEEE T Gate CPU Section 1 System clock (square wave) Gate remote section Board 1 Clock In Gate CPU Section 2 Gate CPU (a) Chip 1 Clock in Clock-distribution chip Shaping and powering To boards 1-3 To boards 4-6 To boards 7-9 RAM 1 Write Strobe in Logic chip 1 RAM chip 1 (b) Board 1 Clock In Tune Point 1 Tune Point 2 Tunable clock chopper Clockpowering tree Early clocks Tune Point 2 Clock chopper Clockpowering tree Normal clocks Tune Point 4 Clock chopper Clockpowering tree Late clocks Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 26 (c)

27 Clock distribution methods: (a) an RC matched tree, and (b) a grid (Bailey and Benschneider 1998), Copyright 1988, IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 27

28 RC delay matched clock distribution topologies: (a) a binary tree, (b) an H tree, (c) an X tree, (d) an arbitrary matched RC matched tree (From Bailey in Chandrakasan et al. 2001), Copyright 1988, IEEE (a) (b) (c) Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 28 (d)

29 Clock distribution grid used in a DEC Alpha 600-MHz processor (Bailey and Benschneider 1998), Copyright 1988, IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 29

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