Design of CMOS Adaptive-Bandwidth PLL/DLLs

Transcription

1 Design of CMOS Adaptive-Bandwidth PLL/DLLs Jaeha Kim May 2004 At Samsung Electronics, Inc.

2 Adaptive-Bandwidth PLL/DLL PLL/DLLs that scale their loop dynamics proportionally with the reference frequency An adaptive-bandwidth PLL maintains: Constant ω n /ω ref Constant ζ Against process, temperature, and voltage variations This talk presents how to design such PLL/DLLs in modern sub-100nm CMOS processes Jaeha Kim 2

3 Why Adaptive-Bandwidth? log(f VCO ) Desired frequency range Constrained by stability Adaptive BW Fixed BW Perf. Loss V CTRL Bandwidth must scale with frequency to sustain the best jitter performance over a wide range Jaeha Kim 3

4 Why Adaptive-Bandwidth? (2) (a) f VCO f target BW (b) fast typ slow V required tuning range CTRL BW limit set by f target /10 fast typ slow Perf. Loss Even if your target is a single frequency point: PVT variations cause uncertainties in loop parameters Designers are forced to make conservative choices (suboptimal) A PLL that can adapt to PVT is needed Reduces uncertainties V CTRL Jaeha Kim 4

5 This Talk Derives criteria for adaptive-bandwidth PLL/DLLs In closed-loop parameters (ω n, ζ) In open-loop parameters (C φ, C ω ) Examines PLL/DLLs published in literature: Self-biased PLL/DLLs [Maneatis96,03] Regulated-supply PLL/DLLs [Sidiropoulos,Kim] Discusses how to verify bandwidth scaling in simulation and in measurement Direct estimation of open-loop parameters Jaeha Kim 5

6 Outline Overview on adaptive-bandwidth PLL/DLLs Criteria for adaptive-bandwidth PLL/DLLs Cases in charge-pump PLL/DLLs Examples in literature Estimation of PLL/DLL open-loop parameters Conclusions Jaeha Kim 6

7 Phase-Locked Loop φ ref, ω ref Phase Detector (PD) φ err Loop Filter (LF) V CTRL VCO φ vco, ω vco N φ out, ω out Tries to lock (φ out, ω out ) to (φ ref, ω ref ) Thus, (φ vco, ω vco ) = N (φ ref, ω ref ) (freq. multiplication) PD compares φ out and φ ref LF adjusts phase/frequency of the VCO clock Jaeha Kim 7

8 Second-order PLL Dynamics Compare (PD) Update (LF) φ ref (s) φ err K P K I /s ω P ωi ω out (s) 1/s φ out (s) Integral control : ω I (s) = K I φ err (s)/s Proportional control : ω P (s) = K P φ err (s) Higher-order terms Jaeha Kim 8

9 Derive ω n and ζ Open-loop transfer function, G PLL (s): G PLL (s) = φ φ out err (s) (s) = sk P 2 Closed-loop transfer function, H PLL (s): H PLL (s) = = φ φ s out ref 2 sk + (s) (s) P sk + K P I + K s G = 1+ G I + K PLL PLL s I 2 2ζω n + 2ζω s + ω n s 2 n + ω 2 n Jaeha Kim 9

10 Therefore, Derive ω n and ζ (2) ω n = K I ζ = K P 2ω n = K P 2 K I Adaptive-bandwidth PLL requires Constant ω n /ω ref Constant ζ K I = ω n2 ω ref2, K P = 2ζω n ω ref Jaeha Kim 10

11 Let s take a different view φ err is actually a discrete-time quantity Most clocks today take binary values PD can measure phase difference only when there is a clock edge (once every cycle) PLL can be viewed as a discrete-time system that makes proper action upon the phase error sampled every reference cycle Jaeha Kim 11

12 Open-loop Transfer in DT Domain Integral control ω I (s) = K I φ err (s)/s in DT: ω n = 1 I [n] = ωi(ntref ) = KI Tref φerr(itref ) i Proportional control φ P (s) = K P φ err (s)/s in DT: φ n = 1 P [n] = φp(ntref ) = KP Tref φerr(itref ) i T ref is the reference cycle time, 2π/ω ref Jaeha Kim 12

13 Open-loop Transfer in DT Domain (2) The change in ω I and φ P that the loop filter makes upon the sampled phase error φ err : ω = ω [n] ω = K φ = φ = K I I P P T ref [n] φ T ref I φ P [n 1] φ err err = [n 1] = 2πK ω ref I 2πK ω ω I and φ P are the sums of past ω[n] s and φ[n] s, respectively, each of which is φ err [n] ref φ P err φ err Jaeha Kim 13

14 A New Discrete-Time PLL Model Compare (PD) Update (LF) φ ref [n] φ err C φ C ω φ ω Σ φ P ω I Σ 1/s φ out [n] Since K I = ω n2 and K P = 2ζω n, ω ω ref φ = = 2π 4πζ ( ) ω n ω ref 2 φ ( ω ) n ωref φerr err Jaeha Kim 14

15 Adaptive-BW PLL Criteria in DT Upon the detection of the phase error φ err, an adaptive-bandwidth PLL updates its relative frequency ω I /ω ref and phase φ P by φ err scaled by some fixed constants, C ω and C φ, respectively: ω ω φ = ref C err err where C ω =2π(ω n /ω ref ) 2 and C φ =4πζ(ω n /ω ref ) φ = C ω = 0.02 and C φ = 0.7 ω n /ω ref = 0.056, ζ = 0.99 φ C ω φ Jaeha Kim 15

16 What about DLLs? Compare (PD) Update (LF) D ref (s) D err K D /s D out (s) Locks delay instead of phase Integral control alone is sufficient Closed-loop transfer function H DLL (s): H DLL D (s) = D out ref (s) (s) = KD s + K D ω n s + ω Jaeha Kim 16 n

17 Discrete-Time DLL Model Compare (PD) Update (LF) D ref [n] D err C D D Σ D out [n] Discrete-time open-loop transfer: D n = 1 out [n] = KD Tref Derr(iTref ) i LF update upon the detected D err : D = = D K out D [n] D T ref D out err [n 1] = 2π( ω n ω ref ) D err Jaeha Kim 17

18 Adaptive-Bandwidth DLL Constant ω n /ω ref implies that the DLL must update its delay by D err times a fixed constant: D = C D D err where C D = 2π(ω n /ω ref ) C D of 0.5 ω n /ω ref of 0.08 Jaeha Kim 18

19 Summary Adaptive-bandwidth PLL/DLLs satisfy: PLL: ω/ω ref = C ω φ err, φ = C φ φ err DLL: D = C D D err The criteria are independent of implementation Analog or digital Hints how to estimate bandwidth of a PLL/DLL Compare φ err and ω, φ made by the PLL Jaeha Kim 19

20 Charge-Pump PLL Charge Pump based LF I CP φ ref PFD V CTRL R VCO (K VCO ) φ vco C φ out Clock Divider ( N) Loop parameters: I CP, R, C, K VCO (rad/s V), N Jaeha Kim 20

21 DT Open-loop Transfer of CP PLL Updates made by CP PLL each cycle: ω = I φ = I CP CP T C err R T K err VCO N K = VCO N K VCO N K VCO N I C CP I φ ω CP Adaptive-bandwidth PLL requires: C ω = ω/ω ref /φ err constant C φ = φ/φ err constant = err ref φ R ω err ref Jaeha Kim 21

22 Criteria for I CP and R Charge-pump current I CP must satisfy: 1 I CP 1 K = C C ω ω 1 2 ref = V ω N V CTRL VCO 2 ωref VCO CTRL 1 ω ref /N = ω 1 2 ref ω V T V ref CTRL ref CTRL Loop-filter resistance R must satisfy: R = I CP T C ref φ K ω ref VCO /N Cφ 1 = C C ω ω ref Jaeha Kim 22

23 Adaptive-BW Criteria for CP DLL The case for charge-pump DLL is similar: D = K VCDL I C CP D Since C D = D/D err must be constant and K VCDL is defined as - D out / V CTRL : I 1 CP = C 1 K C D D V out CTRL VCDL err Jaeha Kim 23

24 Summary The criteria to achieve adaptive bandwidth then boil down to: I CP - V CTRL / T ref R T ref Charge-pump current must adjust for change in T ref (=N T vco ) and K VCO Loop-filter resistance must scale with T ref Let s see how people did it Jaeha Kim 24

25 Self-Biased PLL/DLLs [Maneatis] Replica-Feedback Biasing V DD V DD Differential Stage with Symmetric Load V SWING V FF V SWING V O - V O + V I + V I - V CTRL I BIAS V BIAS V BIAS I BIAS V SWING V BIAS Jaeha Kim 25

26 Symmetric-Load Buffers Symmetric I-V characteristics Average resistance R sym = V SWING /I BIAS Equal rise and fall: low jitter sensitivity [Hajimiri] I BIAS V SWING V I BIAS /2 I 0 V SWING /2 V SWING Jaeha Kim 26

27 Replica-Feedback Biasing Adjusts I BIAS so that V SWING equals V CTRL Maintains R sym = V CTRL /I BIAS against PVT V DD V DD V FF V SWING V CTRL I BIAS V BIAS Jaeha Kim 27

28 Key Tricks to Adaptive Bandwidth Let I CP scale with I BIAS /N and R with N/g m,sym CP shares V BIAS with VCO buffers Output Z of replica-feedback biasing serves as R UP DN CP V FF 1/g m V BN BIAS CP C 1 V CTL CTRL Replica-Feedback Biasing Jaeha Kim 28

29 New Tricks [Maneatis03] To scale I CP 1/N and R N: Use multi-stage programmable current mirror Use sampled feedforward loop filter I IN I OUT V BD S 5 S 4 S 3 S 2 S 1 S 0 x32 x16 x8 x4 x2 x1 Jaeha Kim 29

30 Sampled Feedforward Filter Network UP DN CP C 2 V FF g m 1/g m V BN BIAS CP V RST C 1 V CTRL CTL Replica-Feedback Biasing φ err is sampled and held constant for N T VCO V FF is reset at end of ref. cycle (V RST =V CTRL ) Jaeha Kim 30

31 More Elegant Solution V FF 1/g m UP DN CP C 2 g m V BN BIAS C 1 Replica-Feedback Biasing V CTL CTRL Since V RST =V CTRL, reset V FF to V CTRL directly And eliminate one charge-pump Jaeha Kim 31

32 Does It Satisfy I CP - V CTRL / T ref? PLL keeps R sym = V CTRL /I BIAS and I CP I BIAS /N T VCO C B V CTRL /I BIAS = C B R sym It follows that: I 1 CP,desired T V T N V I N BIAS ref CTRL vco CTRL I V = N V BIAS CTRL I V BIAS CTRL CTRL C 1 = B I V I CTRL BIAS N BIAS ( g R 1) m,sym sym Jaeha Kim 32

33 And R T ref? R desired T ref = N C B R sym N R sym R N/g m,sym Again, we need constant g m,sym R sym!! In fact, Maneatis uses g m,sym in places of R sym in his expressions Jaeha Kim 33

34 R sym vs. g m,sym I CP =I CP,desired and R=R desired if g m,sym R sym is const. But it is true only when V SWING >> V TH Jaeha Kim 34

35 Bandwidth and ζ Scaling ω n /ω ref ratio and ζ creep up as V SWING drops Problematic as V DD /V TH continues to scale down Jaeha Kim 35

36 Possible Remedies Use zero-v TH devices for the symmetric load Cause for g m,sym R sym change in the first place Not always available Use output divider to keep the VCO swing high e.g. use output division of 100 to lock VCO at 1GHz instead of 10MHz Tighter control over ω n and ζ at the cost of power Need extra mechanism to find a proper divide ratio Jaeha Kim 36

37 Regulated-Supply PLL/DLLs [Sidiropoulos] CMOS Inverter V CTRL V BIAS I BIAS V I V O V SWING Jaeha Kim 37

38 Regulated-Supply PLL/DLLs VCO/VCDL is made up of CMOS inverters Smaller voltage headroom required and larger swing Single-ended stage; no static current (low power) but no common-mode noise rejection Linear voltage regulator serves the role of replica-feedback biasing in self-biased PLL Direct regulation of V SWING to V CTRL (since no replica) Effective output resistance of the inverter: R inv = V SWING /I BIAS Jaeha Kim 38

39 Bandwidth Made Adaptive In similar ways with self-biased PLLs: V SWING is regulated to V CTRL I CP is scaled to I BIAS /N R is scaled to N/g m,inv Thus, reg.-supply PLLs suffer similar limitations: Bandwidth and ζ scaling rely on constant g m,inv R inv ω n /ω ref ratio and ζ deviate as V SWING approaches V TH Jaeha Kim 39

40 Adaptive BW Taken to Full Scale [Kim02] Adaptive Power Supply Regulator f ref f Coarse Control Reference VCO Adaptive Supply, V Local Multiphase Clock Recovery Fine Control Local Multiphase Clock Generation Fine Control Local VCO Local VCO 1:5 Demultiplexing Receiver 5:1 Multiplexing Transmitter Jaeha Kim 40

41 Estimation of PLL/DLL Parameters Want to verify if my PLL/DLL is built as intended Extract PLL/DLL parameters (ω n, ζ, etc.) Find out why if they are not as intended Want a common methodology that can be used both in simulation and in lab measurements So that we can compare their results easily Also want to assess non-2nd-order effects High-order poles/zeros, loop latency, static offset, etc. Jaeha Kim 41

42 Prior Art Estimate ω n and ζ from Gardner s equations: Need individual measures of I CP, R, C, K VCO, etc. Measure H(ω) from the PLL/DLL s response while sweeping the input modulation frequency Easily done in the lab, but time-consuming in SPICE Estimate ω n and ζ by curve-fitting the timedomain response to a presumed model Accuracy depends on the model s correctness Closed-loop response is not a sensitive measure Jaeha Kim 42

43 Proposed: Use the Open-loop Model The new discrete-time, open-loop transfer model opens a new way of estimating parameters: PLL: ω/ω ref = C ω φ err, φ = C φ φ err DLL: D = C D D err Measure the sampled error (φ err, D err ) and the corresponding updates ( ω, φ, D) made by the loop Then calculate C ω, C φ, and C D Jaeha Kim 43

44 Closed-loop vs. Open-loop Response When a closed-loop step response has ringing, it is hard to tell whether it is due to: Too small ζ, Low 3rd-order pole frequency, or Excessive loop delay It is easy with an open-loop response! Good for debugging Jaeha Kim 44

45 1. Measure a PLL Transient Apply a step change to φ ref in SPICE PLL must be in lock before the change Measure the transient of φ out [n] From the position of each clock edge in time Find φ err [n] = φ ref [n]-φ out [n] Jaeha Kim 45

46 2. Derive h[n] by Deconvolution The open-loop impulse response of a PLL h[n] can be calculated by deconvolution: h[0] h[n] Caveats: = φ = φ out out [0] φ [n] Works only for linear systems Sensitive to errors in h[n] s for small n s err [0] n 1 k= 0 φ err h[k] φ [0] err [n k],n 1 Jaeha Kim 46

47 3. Extract C φ & C ω from h[n] h[n] A unit impulse in φ err results in: ω = C ω ω ref φ = C φ 2πC ω h[n] C φ + 2πC ω n C φ n C φ and C ω are found easily by a linear fit Jaeha Kim 47

48 Getting More Out of h[n] h[n] 0 1 2πC ω C φ Loop Delay, d d d+1 d+2 Higher-order Transients n h[n] also shows: Loop delay by the position of the first nonzero h[n] Transients due to higher-order poles and/or zeros C φ and C ω can still be measured from the asymptote (given large n) Jaeha Kim 48

49 It Also Works for DLLs h[n] : 1st-order DLL : higher-order DLL D = C D D err 1st-order DLL has h[n] C D, n 1 C D 0 1 d d+1 d+2 Loop Delay, d n h[n] of a DLL also shows: Loop delay, d Higher-order transients Jaeha Kim 49

50 Conclusions A general design methodology for adaptivebandwidth PLLs and DLLs is presented General criteria expressed in open-loop parameters Principles applied to charge-pump PLLs Methods to verify your PLLs Now, you ve got all tools to build better PLLs! sub-100nm CMOS processes; low V DD /V TH, high leakage, poor matching, etc. Is digital or semi-digital PLL an answer? Jaeha Kim 50

51 References J. G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, JSSC Nov S. Sidiropoulos, et al., Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers, VLSI J. Kim, et al., Adaptive-Supply Serial Links with Sub-1V Operation and Per-pin Clock Recovery, JSSC Nov J. G. Maneatis, et al., Self-Biased High-Bandwidth Low- Jitter 1-to-4096 Multiplier Clock Generator PLL, JSSC Dec J. Kim, et al., Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach, TCASII, Nov Jaeha Kim 51