Combinational vs. Sequential. Summary of Combinational Logic. Combinational device/circuit: any circuit built using the basic gates Expressed as

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1 Summary of Combinational Logic : Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: Combinational device/circuit: any circuit built using the basic gates Expressed as Truth table Digital circuit Boolean function Any boolean function can be expressed as two level function Minimization procedure: Karnaugh Map Try to minimize the number of gates, and inputs to gates, in a two level circuit Combinational vs. Sequential Combinational Circuit always gives the same output for a given set of inputs ex: adder always generates sum and carry, regardless of previous inputs Sequential Circuit stores information output t depends d on stored information (state) t plus input so a given input might produce different outputs, depending on the stored information example: vending machine Current total increases when you insert coins output depends on previous state useful for building memory elements and state machines Sequential Logic Build a device, using combinational logic devices, to store a value RS Latch (also called SR Latch) concept of memory Methodology behind design of sequential logic circuits Finite State Machines Example of Vending machine Combine sequential and combinational logic devices to assemble a simple processor!

2 Sequential Circuits Storage Elements We need to design a device capable of storing information Store a bit value Build it using the devices we have thus far Use feedback circuit To be useful, sequential device needs mechanism for setting its state R-S Latch: Output = previous value Or Set output to new value (0 or ), and hold this new value till next write into the device Stable circuit Feedback Circuits Output point of circuit retains value indefinitely Unstable circuit State that remains constant only for a duration of a few gate delays Feedback Circuits To retain their state values, sequential circuits rely on feedback. Feedback in digital circuits occurs when an output is looped back to the input. A simple example of this concept is shown below. If Q is 0 it will always be 0, if it is, it will always be. Why? Feedback Circuits What if we had three gates in the circuit?

3 R-S Latch: Simple Storage Element R-S Latch Summary R is used to reset or clear the element set it to zero. S is used to set the element set it to one If both R and S are one, out could be either zero or one. quiescent state -- holds its previous value note: if a is, b is 0, and vice versa 0 0 R = S = hold current value in latch S = 0, R= set value to R = 0, S = set value to 0 R = S = 0 both outputs equal one final state determined by electrical properties of gates Don t do it! Clocked Flip-Flops/Circuits Subsystem in a computer consists of a large number of combinational and sequential devices Each sequential device is like an SR latch which is in one of two states As machine executes its cycle, the states of all sequential devices change with time To control large collection of devices in an orderly (synchronized) fashion, machine maintains a clock Requires all devices to change their states at the same time Clock generates sequence of pulses Clock As the name implies, sequential logic circuits require a means by which events can be sequenced. State changes are controlled by clocks. A clock is a special circuit that sends electrical pulses through a circuit. Clocks produce electrical waveforms such as: 3

4 Clocked Circuits State changes occur in sequential circuits only when the clock ticks. Circuits can change state on (a)) the rising edge or falling edge edge triggered circuits, or (b) when the clock pulse reaches its highest voltage level level triggered. Time between pulses is the period of the clock Frequency = /period Clocked RS Latch Flip Flop Every sequential device has a Clock (CK) input in addition to its other inputs Device designed to respond to inputs only during a clock pulse Where do we add clock to the RS Latch? Clocked RS Latch = RS Flip Flop Shield NAND gates (latch) from effect of S,R except when clock is high When clk is low the inputs to the NAND gates are both regardless of S,R No change in latch output value When clk is high, values of R and S pass to the NAND gates i.e., latch Clocked Latches Flip Flop SR Flip Flop: Reverse of RS?? More common latch is the SR latch Have input as undefined 00 holds state Set S= to set latch to Set R= to set latch to 0 Replace NAND gates by NOR gates! clock

SR Flip Flop The SR flip-flop actually has three inputs: S, R, and its current output, Q. Thus, we can construct a truth table for this circuit, as shown at the right.

5 SR Latch/Flip-flop SR Latch Behaviour the most basic sequential logic components, the SR flip-flop. The SR stands for set/reset. The behavior of an SR flip flop is described by a characteristic table. Q(t) means the value of the output at time t. Q(t+) is the value of Q after the next clock pulse. SR Flip Flop The SR flip-flop actually has three inputs: S, R, and its current output, Q. Thus, we can construct a truth table for this circuit, as shown at the right. Notice the two undefined values. When both S and R are, the SR flip-flop is unstable. Concept of Memory and Write to Memory We want ONE input to the latch We want to control when to update value in the latch (output) When write is enabled, we want Output = Value of Input Else output = old value of output

6 Gated D-Latch Two inputs: D (data) and WE (write enable) when WE =, latch is set to value of D S = NOT(D), R = D when WE = 0, latch holds previous value S = R = D Flip Flop Behaviour Typical modeling of D flip flop simplifies things Input D= then at clock pulse, output of flip flop becomes Input D=0 then at clock pulse, output becomes 0 D Flip Flop The D flip-flop is the fundamental circuit of computer memory. D flip-flops are usually illustrated using the block diagram shown below. Modify latch to make it a clocked flip flop The characteristic table for the D flip-flop flop is shown at the right. Next Storage Devices Temporary storage in a computer? Where are variables stored before being sent to the arithmetic unit for operations on them? Register Can we build an n-bit register using latches? What about main memory Disk Later 6

7 Register A register stores a multi-bit value. We use a collection of D-latches, all controlled by a common WE. When WE=, n-bit value D is written to register. Representing Multi-bit Values Number bits from right (0) to left (n-) just a convention -- could be left to right, but must be consistent Use brackets to denote range: D[l:r] denotes bit l to bit r, from left to right A = A[:9] = 000 A[:0] = 0 May also see A<:9>, especially in hardware block diagrams. Memory We know how to store m-bit number in a register How about many m-bit numbers? Bank of registers? How to fetch a specific m-bit number? addressing Memory Now that we know how to store bits, we can build a memory a logical k m array of stored bits. Address Space: number of locations (usually a power of ) k = n locations Addressability: number of bits per location (e.g., byte-addressable) m bits 7

8 Memory Memory Looking from the outside, what do we need? Looking from the outside, what do we need? ADDR IN WE OUT Memory - Memory - A large number of addressable fixed size locations Address Space n bits allow the addressing of n memory locations. Example: bits can address =,777, locations (i.e. M locations). If each location holds byte (= 8 bits) then the memory is MB. If each location holds one word (3 bits = bytes) then it is 6 MB. Addressability Computers are either byte or word addressable - i.e. each memory location holds either 8 bits ( byte), or a full standard word for that computer ( bits for the LC-3, more typically 3 bits, though h now many machines use 6 bit words). Normally, a whole word is written and read at a time: If the computer is word addressable, this is simply a single address location. If the computer is byte addressable, and uses a multi-byte word, then the word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines). 8

Memory Given address, fetch contents at that address Select or

D-latch Each location consists of w bits (here w = ) w = 8 if the

address bits (here bits => locations) decoder circuit translates

Example Reading a location in memory A by 3 bits memory: two

9 Memory Given address, fetch contents at that address Select or enable one of many locations ADDR WE IN OUT Each bit is a gated D-latch Each location consists of w bits (here w = ) w = 8 if the memory is byte addressable Addressing n locations means log n address bits (here bits => locations) decoder circuit translates address into of n locations Building a Memory WE A[:0] D Memory Example Reading a location in memory A by 3 bits memory: two address lines: A[:0] three data lines: D[:0] one control line: WE One gated D-latch 9

10 More Memory Details Course Adminis-trivia This is no longer the way actual memory is implemented. fewer transistors, much more dense, relies on electrical properties But the logical structure is very similar. address decoder word select line word write enable Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM) fast, maintains data as long as power applied Dynamic RAM (DRAM) slower but denser, bit storage decays must be periodically refreshed Also, non-volatile memories: ROM, PROM, flash, Lab this week and next is Project completion Project code Dlc code checker tells you if rules violated and if there is a syntax error Review sequential logic HW3, Teamwork 3, Teamwork posted Solutions to HW, and Quiz, posted Work on Teamhomework in class next class Quiz 3 next Tuesday Exam : October 7 Reading: You should have completed reading Chapters,,3 Look up Univ. Maryland notes linked from lectures webpage Summary of Digital Logic Design of Sequential Logic Circuits Combinational logic Storage elements R-S Latches and D-latch Concept of memory: address space and addressability Sequential circuits next! Recall the vending machine example Progress from state (current total) to new state (new total) 0

11 Compare and Contrast A Vending Machine Combinational Logic Circuits Make decisions Same inputs always produce same output Depends on what is happening now Sequential Logic Circuits Make decisions and store information Output depends on inputs AND state Depends on what has happened in the past as well as what is happening now Input valid coins: Q (cents) D (0) or N () Keep track of current total Is it 7 cents or more? When it reaches 7 or more: Generate output States of the machine? Finite State Machines State Machine The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FSMs). FSMs consist of a set of nodes that hold the states of the machine and a set of arcs that connect the states. Directed graph to represent a FSM type of sequential circuit Combines combinational logic with storage Remembers state, and changes output (and state) based on inputs and current state State Machine Moore and Mealy machines are two types of FSMs that are equivalent. They differ only in how they express the outputs of the machine. Moore machines place outputs on each node/state Associate an output with each state Mealy machines present their outputs on the transitions. Inputs Combinational Logic Circuit Storage Elements Outputs

12 Sequential Logic Circuits - State The concept of state the state of a system is a snapshot of all relevant elements at a moment in time. a given system will often have only a finite number of possible states. For many systems, we can define the rule which determines under what conditions a system can move from one state to another. Example the game of tic-tac-toe has only a certain number of possible dispositions of Xs and Os on the 3x3 grid. A given game of tic-tac-toe will progress through a subset of these possible states (until someone wins) - i.e. it traverses a specific path through state space, one move at a time. Sequential Logic Circuits Finite State Machines State Machine Inputs Combinational Logic Circuit Storage Elements Outputs The output is a function of the current input and the previous state It is computed by the combinational logic circuit The state is stored in the storage element The new state is also a function of the previous state and the current input This can work only if we make transitions from one state to another at well-defined times - this is why they are called sequential circuits. Many systems meet the following five conditions: A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all allowed state transitions An explicit specification of the rules for each external output value a microprocessor is a perfect candidate for description as a FSM.

13 The Clock Storage: Master-Slave Flipflop Frequently, a clock circuit triggers transition from one state to the next. A pair of gated D-latches, to isolate next state from current state. 0 One Cycle time At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external inputs. Not always required. During st phase (clock=), previously-computed state becomes current state and is sent to the logic circuit. During nd phase (clock=0), next state, computed by logic circuit, is stored in Latch A. Storage Example: Blinking Traffic Sign Each master-slave flip-flop stores one state bit. The number of storage elements (flip-flops) needed is determined by the number of states (and the representation of each state). Each bit can be 0 or = states N bits can represent N states Example: If a FSM has states, then the circuit needs log = storage elements. Fewer the states, less hardware needed Concept of Minimization of States for a given FSM 3 DANGER MOVE RIGHT 3

14 3 3 DANGER DANGER MOVE RIGHT MOVE RIGHT 3 3 DANGER DANGER MOVE RIGHT MOVE RIGHT

15 3 3 DANGER DANGER MOVE RIGHT MOVE RIGHT 3 3 DANGER DANGER MOVE RIGHT MOVE RIGHT

16 Example: Traffic Sign Traffic Sign State Diagram A blinking traffic sign: How many states states No lights on & on,, 3, & on,, 3,, & on (repeat as long as switch is turned on) How many bits to represent the states S S 0 With S S 0 values: 00, 0, 0, State bit S State bit S0 Switch off Switch on Outputs Transition on each clock cycle. Note we really have 3 groups of lights to be controlled = 3 control lines X,Y,Z Group : Lights and ; controlled by Z If Z= then Group lights ( and ) are switched on Group : lights 3 & ; controlled by Y Group 3: Light ; controlled by X 0 00 all off 0 0 grp on 0 0 0, all on grp, on

17 When is group on? Finite State Machine Example - in states 0, 0 and - but only when the switch IN is on! Logic expressions for X,Y,Z Depends on S 0 and S and Input is on If Input is off then X,Y,Z are al 0 can you come up with a logic expression for next state values of fs 0 and S? Depends on current values of S 0 and S and Input is on Input off then both bits are set to 0 since next state is 00 Next state value of S0 denoted S 0 = if current state is 00 or current state 0 and In= When do we switch to the next state? the two bits of S[:0] are updated at every clock cycle we have to make sure that the new state does not propagate to the combinational circuit input until the next clock cycle. Outputs (depend only on state: S S 0 ) S S 0 Z Y X Traffic Sign Truth Tables Lights and Lights 3 and Light Next State: S S 0 (depend on state and input) Whenever In=0, next state is 00. Switch In S S 0 S S 0 0 X X Traffic Sign Logic Z= (S S 0 + S S 0 + S S 0 ).In Y = (S S 0 + S S 0 ).In X = (S S 0 ).In Master-slave flipflop 7

Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements Storage State Machine MARMUX [0:0] [8:0] [:0] ZEXT [7:0] SEXT SEXT SEXT MARMUX

18 From Logic to Processor Data Path LC-3 Data Path The data path of a computer is all the logic used to process information. Eg. data path of the LC-3. Combinational Logic Combinational Logic Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements Storage State Machine MARMUX [0:0] [8:0] [:0] ZEXT [7:0] SEXT SEXT SEXT MARMUX ADDRMUX LD.IR gatemarmux ADDRMUX IR 0 [:0] + SEXT PCMUX LD.PC ADDRMUX N Z P LOGIC PC PCMUX LD.CC R gatepc + ADDRMUX FINITE STATE MACHINE DR LD.REG 3 SR 3 REG FILE SR SR OUT OUT SRMUX gatealu B A ALU 3 SR What Next? Next topic: The von Neumann model of computer architecture Basic components How instructions are processed The LC3 computer and instruction set GateMDR LD.MDR MDR LD.MAR MEMORY MAR INPUT OUTPUT MEM.EN, R.W 8

19 Recall: what are Computers meant to do? We will be solving problems that are describable in English (or Greek or French or Hindi or Chinese or...) and using a box filled with electrons and magnetism to accomplish the task. This is accomplished using a system of well defined (sometimes) transformations that have been developed over the last 0+ years. Problem Transformation - levels of abstraction The desired behavior: the application Natural Language Algorithm Program Machine Architecture Micro-architecture The building blocks: electronic devices Logic Circuits Devices Putting it all together The goal: Turn a theoretical device - Turing s Universal Computational Machine - into an actual computer... interacting with data and instructions from the outside world, and producing output data. Smart building blocks: We have at our disposal a powerful collection of combinational and sequential logic devices. Now we need a master plan... 9

Introduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison

Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by