COE 328 Final Exam 2008

Transcription

1 COE 328 Final Exam Design a comparator that compares a 4 bit number A to a 4 bit number B and gives an Output F=1 if A is not equal B. You must use 2 input LUTs only.

2 2. Given the following logic circuit, clock signal, and input waveforms: a) Derive the state assigned table b) Sketch the waveforms for Q1, Q2, Y1, and Y2 in the space provided. Note: Assume zero delay for all gates and flip flops. Figure 1 X=0 X=1 Q 2 Q 1 Y 2 Y 1 Y 2 Y CLK /CLR X Q1 Q2 Y1 Y Time (ns) Figure 2

3 3. Given the following logic circuit, derive its state table and state diagram. If the following sequencee is applied to the x input of the circuit with the initial sate 01, determine the resulting output sequence on z output. Q 2 Q x=0 y 2 y x=1 y 2 y x= z x= Reset 0/0 S 0 1/1 S 2 1/0 1/0 0/1 w = 11 0/1 S 1 0/0 S 3 1/1 S S 1 S 0 x 1 0 z=y S 0 S S 3 S S S 1 S S 0 1 1

4 4. The state diagram for a finite state machine (FSM) with one input w and two outputs z2 and z1 is given below w=0 A/01 B/10 w=0 w=0 w=1 D/00 w=1 w=1 C/00 w=0 w=1 a) Does the above state diagram use a Moore or Mealy-type model to represent the FSM? Explain your answer. The state diagram represents Moore type FSM, since outputs are completely defined by states and do not depend on inputs. b) What is the minimum number of state variables required to represent the states? Explain your answer. Two state variables are required, because 2 2 = 4, where 4 is the number of states. c) Using the state assignment: A=00, B=01, C=11, and D=10, develop the next state and output equations for implementing the FSM.

5 w=0 w=1 Q 2 Q 1 D 2 D 1 D 2 D 1 z 2 z 1 A B C D D 2 D 1 w \ Q 2 Q w \ Q 2 Q z 2 z 1 Q 2 \ Q Q 2 \ Q

6 5. Assuming that an 8 x 4 bit EPROM is available, explain how the FSM can be implemented with the state assignment in Part C. Fill in the contents of the EPROM in the table below and clearly explain what the addresses and contents of the EPROM represent. Content Address D 3 D 2 D 1 D 0 w A 2 A A 0 D 0 EEPROM D 0 Q 0 D 2 D 1 D 1 Q 2 Q 1 w A 1 D 2 D 3 z 1 D 1 Q 1 FF z 2 w=0 w=1 Q 2 Q 1 D 2 D 1 D 2 D 1 z 2 z 1 A B C D

7 6. Which circuit does the following VHDL code represent? LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY system IS PORT (Clock, Reset : IN STD_logic; z : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END system; ARCHITECTURE Behavior OF system IS TYPE State_type IS (A,B,C); SIGNAL y: State_type; BEGIN PROCESS (Reset, Clock) BEGIN IF Reset='0' THEN y<=a; ELSIF(Clock'EVENT AND Clock='1') THEN CASE y IS WHEN A=> THEN y<=b; WHEN B=> THEN y<=c; WHEN C=> THEN y<=a; END CASE; END IF; END PROCESS; PROCESS(y) BEGIN CASE y IS WHEN A=> z <= ''110''; WHEN B=> z <= ''101''; WHEN C=> z <= ''011''; END CASE; END PROCESS; END Behavior; Reset Clk Mod 3 Q 2 A/ 11 B/ 10 Reset Counter Q 1 Q 0 C/ 01

8 7. This question deals with the processor in LAB7 (See also the Appendix) a) The switches (SW) are set to 0110; carry bit (C) equals to 1, program counter (PC) equals to 1010, accumulator (ACCA) equals to 0110, Random Access Memory location 1010 (RAM (A)) contains 1111 and program memory location 1010 (EPROM3 (A)) contains DA hex. What are the contents of PC, ACCA, C, and RAM (A) after the execution of the current instruction? PC=1010 ACCA=0110 C=1 RAM(A)=1111 SW=0110 EPROM(A)=DA= PC=1010 ACCA=0110 C=1 RAM(A)=1111 b) Write a program (not to exceed 16 instructions) for the processor of LAB7 to search the content of memory locations 3 and 4 for a specific number that is specified by the switches. If the number is found in memory location 3 or 4, display the exact memory location that the number is stored at. Display 0 if the number is not found in memory location 3 or 4. (Use comments with each instruction to explain your program). 0 LDAA 3 ; A=M(3) 1 JEQ 6 ; SW=M(3) 2 LDAA 4 ; A=M(4) 3 JEQ 11 ; SW=M(11) 4 CLRA ; SW Not = M(3) or M(4) 5 JMP 5 ; display 0 6 CLRA ; A=0 7 SEC ; C=1 8 ROLA ; A=1 9 ROLA ; A=3 10 JMP 10 ; display 3 11 CLRA ; A=0 12 INCA ; A=1 13 ROLA ; A=2 14 ROLA ; A=4 15 JMP 15 ; display 4

9 c) In the Processor Instruction Set list above, it is desired to change the STSW N instruction to the STEQ N instruction. The STEQ N instruction would compare contents of the accumulator to data from the switches. If they equal to each other, the data in the accumulator would be inverted and stored into memory location N. Otherwise, control would be transferred to the next instruction in the program storage. Fill in the table for the STEQ N instruction shown below. EPROMs 1&2 Address Lines EPROM1 EPROM2 EPROM3 PAL ACCA ALU181 Data Path 161 EPROM JP N0 OP Code MCode NCC L1 L0 M S3 S2 S1 S0 /AS WR SM /PECNTA1+A0+ A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D X STEQ N X X X X X X X STEQ N X

10 Appendix The processor below is the one used in project 7. It uses an ALU whose functions are listed on the following page. The processor instruction set is also given on the following page. Shift Register Operating Modes Mode Hold L1 0 0 L0 Shift Right 0 1 Shift Leftt 1 0 Parallel Load 1 1

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