Lab #10: Design of Finite State Machines

Transcription

1 Lab #10: Design of Finite State Machines ECE/COE 0501 Date of Experiment: 3/1/2017 Report Written: 3/4/2017 Submission Date: 3/15/2017 Nicholas Haver 1 H a v e r

2 PURPOSE The purpose of this lab was to design, simulate, build, and test a synchronous finite state machine. The overall purpose of the circuit was to output one of four possible bit strings, depending on a two-bit input. The circuit was a simple pulse width modulation motor controller. The circuit was designed as a Mealy Machine, with the state of the circuit stored in 74LS74A D flip-flops. While a Mealy Machine requires fewer states and inputs than a Moore Machine, the corresponding logic is usually more complex. After completing initial design on paper, the circuit was designed and simulated in Altera Quartus II. The circuit was then constructed on a breadboard, and its function was compared to that predicted by the simulation. In constructing the circuit in the real world, time delays more accurate than those generated by Altera Quartus II are able to be observed. PROCEDURE 1) The circuit was designed given the following input/output specifications: A B Z Table 1: Given inputs and outputs for finite state machine design 2) Given the specifications in Table 1, a state transition diagram was created, showing the next state for each combination of inputs and present states, and a state table, shown in Table 2, was determined. 3) Based on the state table, K-maps, shown in Tables 3-6, were used to determine the input logic (Equations 1-3) for each of the three D input bits (D2, D1, D0), as well as the output bit Z (Equation 4). 4) Based on the input and output logic, the required number of gates and integrated circuits was calculated, shown in Table 7. 5) A schematic was designed in the graphic editor of Altera Quartus II using 7474 D flip-flops, as shown in Figure 1. As shown, the presets and clears were set to high. 6) A clock square wave with a period of 40ns and each combination of the two input bits were constructed in a vector waveform file and the circuit was compiled and simulated in Altera Quartus II, shown in Figure 2. 7) After the schematic was tested and correct functionality was confirmed, the circuit was constructed on the breadboard. Two non-inverted logic sources were used for the inputs. The following integrated circuits were used: 555 (timer), 7474 (dual D flip-flop), 7408 (AND gate), 7432 (OR gate), and 7486 (XOR gate). 8) After constructing the circuit, the clock and output signals were observed in the oscilloscope to verify circuit functionality, and the circuit was checked by a TA. 9) The circuit was optimized to minimize the length of wire used. 10) The clock signal, inputs X1 and X0, and output Z were connected to a logic analyzer, and a waveform display was generated to verify that the circuit was functioning properly. 2 H a v e r

3 RESULTS A B Q 2 Q 1 Q 0 Q(t+1) 2 Q(t+1) 1 Q(t+1) 0 Z D 2 D 1 D Table 2: Mealy Machine State Table Based on State Transition Diagram Q 2Q 1 / Q Table 3: D 2 Input Logic K-Map D 2 = Q 2 (Q 1 Q 0 ) (1) Q 2Q 1 / Q Table 4: D 1 Input Logic K-Map D 1 = Q 1 Q 0 (2) Q 2Q 1 / Q Table 5: D 0 Input Logic K-Map D 0 = Q 0 (3) 3 H a v e r

4 X 0 = 0 X 0 = 1 Q 2Q 1/Q 0X Q 2Q 1/Q 0X Table 6: Z Output Logic K-Map Z = Q 2 X 1 + Q 2 Q 1 Q 0 + Q 1 Q 0 X 1 + Q 2 Q 1 X 0 + Q 0 X 1 X 0 + Q 1 X 1 X 0 + Q 2 Q 0 X 0 Z = (Q 2 X 1 )(Q 1 Q 0 + Q 0 X 0 + Q 1 X 0 ) Q 2 X 1 (4) Logic Gates Packs XOR 4 1 AND 6 2 OR 2 1 D Flip-Flop 4 2 Table 7: Required Gates/Packs for Input / Output Logic Figure 1: Schematic that was built and simulated in Altera Quartus II prior to real circuit construction Figure 2: Altera Quartus II simulation of Figure 1 schematic 4 H a v e r

5 After observing output Z on the oscilloscope, the clock (CLK 1), X0 (D2), X1 (D1), and Z(D0) were wired up to the Intronix LogicPort logic analyzer. The outputs for each of the 4 combinations of inputs are shown in Figures 3 6. Figure 3: Logic output for inputs X 0 = 0 and X 1 = 0 Figure 4: Logic output for inputs X 0 = 1 and X 1 = 0 Figure 5: Logic output for X 0 = 0 and X 1 = 1 Figure 6: Logic output for X 0 = 1 and X 1 = 1 Figure 7: 74LS74A dual D flip-flop pin configuration Figure 8: 74LS74A dual D flip-flop logic diagram 5 H a v e r

6 For circuit construction on the breadboard, 74LS74A integrated circuits were used. The circuits each contain 2 rising edge-triggered D flip-flops, so 2 integrated circuits were used. The pin configuration and logic diagram for the 74LS74A are shown in Figure 7 and Figure 8. Figure 9: 555 Timer chip pin configuration and characteristic equations To generate the clock signal, a 555 timer chip was used. The period and duty cycle can be configured based on the resistor and capacitor values shown in the schematic. Equation 5 relates the clock period to the resistor and capacitor values used as shown in Figure 9. T = (R fa + 2R fb ) C f (5) To implement the input logic for D2, D1, and D0, as well as the output logic for Z, AND, OR, and XOR integrated circuits were used. Circuit diagram for integrated circuits 7408 (AND), 7432 (OR), and 7486 (XOR) are shown in Figure 10, Figure 11, and Figure H a v e r

7 Figure 10: Logic diagram and pin configuration for 7408 AND integrated circuit Figure 11: Logic diagram and pin configuration for 7432 OR integrated circuit 7 H a v e r

8 Figure 12: Logic diagram and pin configuration for 7486 XOR integrated circuit CONCLUSION This experiment required the design, simulation, construction and testing of a synchronous finite state machine. After designing and simulating the circuit using Altera Quartus II, the circuit was constructed on a breadboard using two 74LS74A dual D flip-flop integrated circuits. A state transition diagram and state table were created to determine the input logic for the D inputs, and the output logic for the Z output. Using K-maps, the logic was optimized, and a circuit was constructed using AND, OR, and XOR gates, and a 555 timer chip for the clock signal. Using the Intronix LogicPort logic analyzer, the outputs Q2, Q1, Q0, and Z were observed for each combination of the two input bits X1 and X0. The overall purpose of the circuit was to output one of four possible bit strings, depending on a two-bit input. The circuit was a simple pulse width modulation motor controller and could be used in applications such as controlling a variable speed motor. REFERENCES Dr. Alex Jones s laboratory instructions ECE/COE 0501 Lab Manual Data sheets for 555, 7474, 7408, 7432, and 7486 integrated circuits Lab Partner: Jenn Gingerich 8 H a v e r