Outcomes. Unit 14. Review of State Machines STATE MACHINES OVERVIEW. State Machine Design

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1 4. Outcomes 4.2 Unit 4 tate Machine Design I can create a state iagram to solve a sequential problem I can implement a working state machine given a state iagram 4.3 Review of tate Machines 4.4 TATE MACHINE OVERVIEW We've implemente state machines in software, now let's see how we can buil them in harware tate machines are escribe with state iagrams that show various states, transition arrows between them, an outputs to be generate base on the current state We use the state to help us know which step of an algorithm we are currently at

2 Harware tate Machines Harware vs. oftware M Comparison Harware (finite) state machines of (Ms) provie the brains or control for electronic an electro-mechanical systems Many custom harware esigns use a harware-base M to control their operation Goal is to generate output values at When you nee time epenent HW outputs, you can use an M Ms require an logic elements equential Logic to remember what step (state) we re in Encoes everything that has happene in the past Combinational Logic to prouce outputs an fin what state to go to next Generates outputs base on what state we re in an the input values Harware Ms Changes state (makes a transition) every Uses a to store the current state Designer can choose state 'coes' arbitrarily but the choice can greatly affect the of the circuit Uses (foun from a truth table an K-Map or other means) to implement the state transition arrows Must implement the initial state value using the signal oftware Ms Changes state (makes a transition) when software the inputs (which coul be very low frequency) Uses a to store the current state Programmer can choose state 'coes' with little implication Uses to implement the state transition arrows Must implement the initial value of the state variable Comparison: M in W an HW tate Machine Example int main() { unsigne char state=; // init state unsigne char input, output; while() { _elay_ms(); // choose appropriate elay input = PIND & ( << PD); if(state == ){ PORTD &= ~( << PD7); // output off if( input ){ state = ; /* transition */ } else { state = 2; /* transition */ } } else if(state == ){ PORTD &= ~( << PD7); // output on if( input ){ state = 2; } else { state = ; } } else if(state == 2) { PORTD = ( << PD7); // output on if(!input ) { state = ; } } } return ; } oftware Implementation (Input) () D D PRE PRE tate Diagram () () Harware Implementation Design a sequence etector to check for the combination "" Input,, provies -bit per clock Check the sequence of for "" in successive clocks If "" etecte, output = (= all other times) "" equence Detector

3 Another tate Diagram Example 4.9 Correct pecification of tate Diagrams 4. equence Detector shoul output = when the sequence is foun in consecutive orer init = = = = or HW especially, it is critical that exactly from a state may be true at a time We can't go at once an if we on't tell it explicitly where to go next, it may go to any ranom state If you want to stay in a state, inclue an explicit arrow On the 2 n example if you want to stay in, inclue a loopback labele = tate Diagram for equence Detector ee the en of this slie set for more etaile solutions an explanations. Correct pecification of tate Diagrams 2 Exactly one transition from a state may be true at a time Make sure the conitions you associate with the arrows coming out of a state are (< 2 true) but all inclusive (> true) 4. tate Machines The HW for a state machines can be broken into 3 sections of logic tate Memory (M) Just s to remember the Logic (NL) Combo logic to etermine the next state Essentially implements the transition conitions Logic (OL) Combo logic to prouce the outputs 4.2 ALWAY ouble check your transitions to ensure they are mutually exclusive.

4 tate Machine tate Machines inputs NET TATE The inputs will be the value of the next state logic output. On the next clock ege the outputs will change base on these inputs. Logic next state Di tate Memory (lip- lops) current state i CURRENT TATE The outputs represent the current state (the state we re in right now) unction Logic outputs Below is a circuit implementing a state machine, notice how it breaks into the 3 sections (Input) () () D OL NL D D M () clock Important: tate is always represente an store by the flip-flop outputs in the system TATE MACHINE DEIGN 4.5 tate Diagram vs. tate Machine tate Diagrams. tates 2. Transition Conitions 3. s tate Machines require sequential logic to remember the current state (w/ just combo logic we coul only look at the current value of, but now we can take 4 separate actions when =) = init = = = = = = = = = = tate Diagram for equence Detector = tate Machine. tate Memory => lip lops (s) n- s => 2 n states 2. Logic (NL) combinational logic logic for inputs 3. unction Logic (OL) MOORE: f(state) MEALY: f(state + inputs) (Input) () () D OL NL D D M 4.6 ()

5 tate Machine Design tate Machine Design tate machine esign involves taking a problem escription an coming up with a state iagram an then esigning a circuit to implement that operation Problem Description tate Diagram Circuit Implementation Coming up with a state iagram is non-trivial Requires creative solutions Designing the circuit from the state iagram is one accoring to a simple set of steps To come up w/ a state iagram to solve a problem Write out an algorithm or to solve the problem Each step in your algorithm will usually be in your state iagram Ask yourself what past inputs nee to be an that will usually lea to a state representation Consecutive Detector Given a single-bit input,, set the output to if the last 2 values of have been EAMPLE Consecutive 's Detector

6 6 teps of tate Machine Design 4.2 Transition Table tate Diagram 2. Transition/ Table ( -> *) 3. tate Assignment Determine the # of s require Assign binary coes to replace symbolic names 4. Rename i* to Di 5. K-Maps for NL (Di values) an OL One K-Map for every input One K-Map for every output of OL 6. Draw out the circuit Convert state iagram to transition/output table how & as a function of an Input = = = 2 = = = = = = Current tate Input () 2 2 Next tate () Transition Table 4.23 Transition Table 4.24 Now assign binary coes to represent states The orer oesn't matter. Use on't cares for unuse state coes = = = 2 = = = = tate Assignment Mapping = tate -- 2 = Current tate Input * * Notice we use Gray Coe orer. This will help in a future step Convert state iagram to transition/output table = = tate tate * * tate * * = = = 2 = = = = = = Here we have rerawn the 8 row table from the previous slie into 4 rows & 2 columns. We've also separate the output since it oesn't epen on but only an

7 Rename * to D Upate Table The goal is to prouce logic for the inputs to the s D,D : (aka "excitation equations") or D- s * will be whatever D is at the ege NL D M ET OL in a truth table for the flip-flop inputs (Di) an output () tate tate = = * D * D tate * D * D D ET = = = 2 = = = = eeback = = Karnaugh Maps Karnaugh Maps Now nee to perform K-Maps for D, D, an Now nee to perform K-Maps for D, D, an = = tate tate D D tate D D = = tate tate D D tate D D D = D = D =

8 Karnaugh Maps 4.29 Implementing the Circuit 4.3 Now nee to perform K-Maps for D, D, an = = tate tate D D tate D D D = D = ' = Implements the consecutive s etector NL M OL GND D ET D GND ET eeback Implementing an Initial tate 4.3 Implementing an Initial tate 4.32 How can we make the machine start in on reset (or power on?) lip-flops by themselves will initialize to a state ( or ) when power is turne on Use the CLEAR an P inputs on our flip-flops in the state memory When CLEAR is active the initializes = When P is active the initializes = = = 2 = = = = = D P = =

9 Implementing an Initial tate Implementing an Initial tate We assigne the binary coe = so we must initialize our flip-flops to = = = = 2 = = = = = = tate Assignment Mapping tate -- 2 Use the inputs of your s along with the signal to initialize them to s We on't nee the P inputs so GND them (Input) () D D PRE PRE () () Implementing an Initial tate Alternate tate Assignment When is activate s initialize to an then when it goes back to the s look at the D inputs Important act: The coes we assign to our states can have a big impact on the size of the NL an OL Let us work again with a ifferent set of assignments orces s to because it s connecte to the inputs = = Out put Once goes to, the s look at the D inputs tate -- 2 Ol Assignments tate tate tate New Assignments

10 Alternate tate Assignment Upate Circuit & Reset Conition tate tate = = * =D * =D tate * =D *= D 2 Outp ut Consier the initial state implementation = = (Input) () D PRE () D PRE () D = ' D = '+ = = Notice the ifferent state assignment le to larger circuits (NL is consierably larger). We will generally provie you the state assignment! 4.39 Traffic Light Controller 4.4 Design the controller for a traffic light at an intersection Main street has a protecte turn while small street oes not ensors embee in the street to etect cars waiting to turn Let = to check if any car is waiting implify an only have Green an Re lights (no yellow) EAMPLE 2 mall treet Turn ensor Turn ensor 2 Overall sensor output = + 2

11 tate Assignment Design of the traffic light controller with main turn arrow Represent states with some binary coe Coes: 3 tates => 2 bit coe: =G, =MG, =MTG Turn ensor 4.4 K-Maps in logic for each input by using K-Maps Current tate = = tate tate * * tate * * G MTG MG N/A MT M MG = 4.42 Turn ensor 2 Overall sensor output = + 2 tate Diagram G = MTG = Main treet D = + D = 4.43 Water Pump 4.44 Implement the water pump controller using the High an Low sensors as inputs Recall the H an L sensor prouce when water is covering them an otherwise EAMPLE 3 O P= ON P=

12 L Transition Table O P= ON P= L H H H L = H L = H L = H L = ymbol ym. * ym. * ym. * ym. * O ON Note: The tate Value, forms the Pump output (i.e. when we want the pump to be on an othewise) H L Alternating Priority Arbiter EAMPLE 4 D = Problem Description tate Diagram Two igital evices (Device an Device ) can request to use a share resource via iniviual request signals: R (from Dev) an R (from Dev) An arbiter will examine the requests an issue a grant signal to the appropriate evice (G to Dev an G to Dev). Requests are examine uring cycle an a grant will be generate on the next, an active for one cycle If only one evice makes a request uring a cycle, it shoul receive the grant on the next. If both evices request on the same cycle, the grant shoul be given to the evice who hasn't receive a grant in the longest time. R R Alternating Prioritizing Arbiter G G Cycle R R G G Complete the state iagram R' R' PW R PG G= PW R' R' R Cycle R R t. G G PG G= R R'

13 Transition Table in the NL an OL Complete the transition table R' R' PW R R' R' PG G= R' R R' R R' R' R R PW R' R' R PG G= R R' R R = R R = R R = R R = t. t* * * t* * * t* * * t* * * G G PW PW PG PG PG PW PW PG PG PG PG PW PG PG PG R' R PG PW PG PG PG R R = R R = R R = R R = t. t* * * t* * * t* * * t* * * G G PW PW PG PG PG PW PW PG PG PG PG PW PG PG PG RR RR G = G = PG PW PG PG PG D = D = inal Circuit NL M OL R R D ET G D ET G EAMPLE 5 eeback

14 tate Machine Example tate Diagram Design a sequence etector to check for the combination "" Input,, provies -bit per clock Check the sequence of for "" in successive clocks If "" etecte, output Z= (Z= all other times) Be sure to hanle overlapping sequences "" equence Detector Z = init Z= Transition Table Transition Table Translate the state iagram into the transition output table = = tate 2 tate* 2* * * tate* 2* * * Z init init init Outp ut Translate the state iagram into the transition output table = = tate 2 tate* D2 D D tate* D2 D D Z init init init Outp ut

15 NL & OL Drawing the Circuit = = tate 2 tate* D2 D D tate* D2 D D Z init init init Out put 2 Z = D 2 = 2 D = D = Waveform for Detector CLOCK 2 ELECTED OLUTION TATE INITIAL TATE I Z

16 Another tate Diagram Example Another tate Diagram Example equence Detector shoul output = when the sequence is foun in consecutive orer equence Detector shoul output = when the sequence is foun in consecutive orer We have to remember the,, along the way = = = = = = = = init = = = = = = init = = = = = = = = tate Diagram for equence Detector = A initially is not part of the sequence so stay in init = Another in means you have, but that secon can be the start of the sequence A in means you have which can t be part of the sequence 4.63 Alternating Detector 4.64 Design a state machine to check if sensor prouces two s in a row (i.e. 2 consecutive s) or two s in a row (i.e. 2 consecutive s) ALTERNATING EUENCE DETECTOR G A= = G A= = = = G A= = G A= = G = Last cycle we got, two cycles ago we got G = Last cycle we got, two cycles ago we got G = Got 2 consecutive s G = Got 2 consecutive 's = =

17 Transition Table Transition Table Convert state iagram to transition/output table how & as a function of an Input G A= = G A= = = = G A= = G A= = = = Current tate Input () Next tate (A) G G G G G G G G G G G G G G G G Now assign binary coes to represent states G A= = G A= = = = = G A= G A= = = = tate Assignment Mapping tate G G G G Current tate Input * * A Transition Table Excitation Table Convert state iagram to transition/output table = = The goal is to prouce logic for the inputs to the s (D,D ) these are the excitation equations tate tate tate A G G G NL ( Logic) M (tate Memory) OL ( unction Logic) G G G D D (t) G G G G G G A = = G G A= = A= = = = G G A= A= = = Here we have rerawn the 8 row table from the previous slie into 4 rows & 2 columns. We've also separate the output A since it oesn't epen on but only an (t) (t) D eeback (t)

18 Excitation Table Excitation Table Using your transition table you know what you want * to be, but how can you make that happen? or D- s * will be whatever D is at the ege NL ( Logic) D M (tate Memory) D (t) OL ( unction Logic) A In a D- * will be whatever D is, so if we know what we want * to be just make sure that s what the D input is = = tate tate D D tate D D A G G G G G G D D (t) G G G G G G (t) (t) eeback Karnaugh Maps Karnaugh Maps Now nee to perform K-Maps for D, D, an A Now nee to perform K-Maps for D, D, an A = = tate tate D D tate D D A G G G G G G G G G G G G = = tate tate D D tate D D A G G G G G G G G G G G G D = D = D =

19 Karnaugh Maps Implementing the Circuit Now nee to perform K-Maps for D, D, an A = = tate tate D D tate D D A G G G G G G G G G G G G Implements the alternating etector NL ( Logic) D M (tate Memory) D (t) OL ( unction Logic) A unuse D (t) D = D = A = + = NOR (t) (t) eeback Implementing an Initial tate Implementing an Initial tate How can we make the machine start in G on reset (or power on?) lip-flops by themselves will initalize to a ranom state ( or ) when power is turne on G A= = = = = = G A= = Use the inputs of your s along with the signal to initialize them to s (t) (t) NL ( Logic) D D M (tate Memory) PRE PRE (t) (t) OL ( unction Logic) A G A= G A= = = eeback

20 Implementing an Initial tate Alternate tate Assignment We on't want to initialize our flip-flops to 's (only =) so we just on't use PRE (tie to 'off'='') (t) (t) NL ( Logic) D D M (tate Memory) PRE PRE (t) (t) OL ( unction Logic) A Important act: The coes we assign to our states can have a big impact on the size of the NL an OL Let us work again with a ifferent set of assignments tate G G G G Ol Assignments = = tate tate tate A G G G G G G G G G G G G New Assignments Out put eeback 4.79 Alternate tate Assignment tate tate = = *= D *= D tate * =D * =D A G G G G G G G G G G G G D = xor xor D = + A =