# Lecture 8: Combinational Circuits

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1 Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004

2 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates est P/N ratio Slide

3 Example module mux(input s, d0, d, output y); assign y s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. Slide 3

4 Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. Slide 5

5 Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. Slide 8

6 Compound Gates Logical Effort of compound gates unit inverter OI OI i + C + CD C C D D E C Complex OI i i i( ) + C + DE i C C 4 C 4 D 4 C D C D E E 6 D C g 3/3 g 6/3 g g p 3/3 g 6/3 g g g C 5/3 g C g C p 7/3 g D g D p g E p Slide 0

7 Example 4 The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the NND and compound gate designs. Slide

8 NND Solution D0 S D S Slide 4

9 Compound Solution D0 S D S Slide 6

10 Example 5 nnotate your designs with transistor sizes that achieve this delay. Slide 8

11 Input Order Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? If arrives latest? x 6C C Slide 0

12 Inner & Outer Inputs Outer input is closest to rail () Inner input is closest to output () If input arrival time is known Connect latest input to inner terminal Slide

13 symmetric Gates symmetric gates favor one input over another Ex: suppose input of a NND gate is most critical g g Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same reset g total g + g symmetric gate approaches g on critical input ut total logical effort goes up reset 4/3 Slide 3

14 Symmetric Gates Inputs can be made perfectly symmetric Slide 5

15 Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. Slide 6

16 HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction ut larger for the other direction Slide 8

17 Catalog of Skewed Gates Inverter NND NOR unskewed 4/3 4/3 4/ /3 5/3 5/3 HI-skew / 5/6 5/3 5/4 LO-skew 4/3 /3 Slide 9

18 symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 Slide 3

19 est P/N Ratio We have selected P/N ratio for unit rise and fall resistance (µ -3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter t pdf t pdr t pd Differentiate t pd w.r.t. P Least delay for P P Slide 33

20 P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest.44 P/N ratio Slide 35

21 Observations For speed: NND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages Slide 37

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