Introduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline

Transcription

1 Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Eample Summar Slide

2 Introduction Chip designers face a bewildering arra of choices What is the best circuit topolog for a function? How man stages of logic give least dela? How wide should the transistors be???? Logical effort is a method to make these decisions Uses a simple model of dela Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable smmetries Slide 3 Eample Ben Bitdiddle is the memor designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the A[3:0] A[3:0] decoder for a register file. 3 bits Decoder specifications: 6 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementar address inputs A[3:0] Each input ma drive 0 unit-sized transistors Ben needs to decide: How man stages to use? How large should each gate be? How fast can decoder operate? :6 Decoder Register File 6 words Slide

3 Dela in a Logic Gate Epress delas in process-independent unit d = d abs τ τ = 3RC ps in 80 nm process 0 ps in 0.6 µm process Slide 5 Dela in a Logic Gate Epress delas in process-independent unit d dabs = τ Dela has two components d = f + p Slide 6 3

4 Dela in a Logic Gate Epress delas in process-independent unit d Dela has two components d = d abs τ = f + p Effort dela f =gh(a.k.a. stage effort) Again has two components Slide 7 Dela in a Logic Gate Epress delas in process-independent unit d = d abs τ Dela has two components d = f + p Effort dela f = gh (a.k.a. stage effort) Again has two components g: logical effort Measures relative abilit of gate to deliver current g for inverter Slide 8

5 Dela in a Logic Gate Epress delas in process-independent unit d = d abs τ Dela has two components d = f + p Effort dela f = gh (a.k.a. stage effort) Again has two components h: electrical effort = C out / C in Ratio of output to input capacitance Sometimes called fanout Slide 9 Dela in a Logic Gate Epress delas in process-independent unit d Dela has two components d = d abs τ = f + p Parasitic dela p Represents dela of gate driving no load Set b internal parasitic capacitance Slide 0 5

6 Dela Plots d = f + p = gh + p Normalized Dela: d input NAND g = p = d = Inverter g = p = d = Electrical Effort: h = C out / C in Slide Dela Plots d = f + p = gh + p What about NOR? Normalized Dela: d input NAND Inverter g = /3 p = d = (/3)h + g = p = d = h + Effort Dela: f 0 Parasitic Dela: p Electrical Effort: h = C out / C in Slide 6

7 Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from dela vs. fanout plots Or estimate b counting transistor widths A Y A B Y A B Y C in = 3 g = 3/3 C in = g = /3 C in = 5 g = 5/3 Slide 3 Catalog of Gates Logical effort of common gates Gate tpe Number of inputs 3 n Inverter NAND /3 5/3 6/3 (n+)/3 NOR 5/3 7/3 9/3 (n+)/3 Tristate / mu XOR, XNOR, 6,, 6 8, 6, 6, 8 Slide 7

8 Catalog of Gates Parasitic dela of common gates In multiples of p inv ( ) Gate tpe Number of inputs 3 n Inverter NAND 3 n NOR 3 n Tristate / mu 6 8 n XOR, XNOR 6 8 Slide 5 Eample: Ring Oscillator Estimate the frequenc of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Dela: p = Stage Dela: d = Frequenc: f osc = Slide 6 8

9 Eample: Ring Oscillator Estimate the frequenc of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Dela: p = Stage Dela: d = Frequenc: f osc = /(*N*d) = /N 3 stage ring oscillator in 0.6 µm process has frequenc of ~ 00 MHz Slide 7 Eample: FO Inverter Estimate the dela of a fanout-of- (FO) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Dela: p = Stage Dela: d = Slide 8 9

10 Eample: FO Inverter Estimate the dela of a fanout-of- (FO) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Dela: p = Stage Dela: d = 5 The FO dela is about 00 ps in 0.6 µm process 60 ps in a 80 nm process f/3 ns in an f µm process Slide 9 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort G = g i C H = C out-path in-path F = f = gh i i i 0 g = h = /0 g = 5/3 h = / g 3 = /3 h 3 = z/ z g = h = 0/z 0 Slide 0 0

11 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH? G = g i C H = out path C in path F = f = gh i i i Slide Paths that Branch No! Consider paths that branch: G = H = GH = h = h = F = GH? Slide

12 Paths that Branch No! Consider paths that branch: G = H = 90 / 5 = 8 5 GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = 6 F = g g h h = 36 = GH Slide 3 Branching Effort Introduce branching effort Accounts for branching between stages in path Con path b = C B= b i + C on path off path Now we compute the path effort F = GBH Note: h i = BH Slide

13 Multistage Delas Path Effort Dela Path Parasitic Dela Path Dela D F = f P= p i D = d = D + P i i F Slide 5 Designing Fast Circuits D = d = D + P i F Dela is smallest when each stage bears same effort fˆ = gh = F i i N Thus minimum dela of N stage path is N D = NF + P This is a ke result of logical effort Find fastest possible dela Doesn t require calculating gate sizes Slide 6 3

14 Gate Sizes How wide should the gates be for least dela? fˆ = gh= g C = in i C C out in gc i fˆ out i Working backward, appl capacitance transformation to find input capacitance of each gate given load it drives. Check work b verifing input cap spec is met. Slide 7 Eample: 3-stage path Select gate sizes and for least dela from A to B A 8 5 B 5 Slide 8

15 A Eample: 3-stage path 8 Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort ˆf = Parasitic Dela P = Dela D = 5 B 5 Slide 9 A Eample: 3-stage path 8 5 B 5 Logical Effort G = (/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 5/8 Branching Effort B = 3 * = 6 Path Effort F = GBH = 5 Best Stage Effort 3 f ˆ = F = 5 Parasitic Dela P = = 7 Dela D = 3*5 + 7 = =. FO Slide 30 5

16 Eample: 3-stage path Work backward for sizes = = A 8 5 B 5 Slide 3 Eample: 3-stage path Work backward for sizes = 5 * (5/3) / 5 = 5 = (5*) * (5/3) / 5 = 0 5 A P: N: P: N: 6 P: N: 3 B 5 Slide 3 6

17 Best Number of Stages How man stages should a path use? Minimizing number of stages is not alwas fastest Eample: drive 6-bit datapath with unit inverter Initial Driver D = Datapath Load N: f: D: Slide 33 Best Number of Stages How man stages should a path use? Minimizing number of stages is not alwas fastest Eample: drive 6-bit datapath with unit inverter Initial Driver D = NF /N + P = N(6) /N + N Datapath Load N: f: D: Fastest Slide 3 7

18 Derivation Consider adding inverters to end of path How man give least dela? N i= ( ) Define best stage effort n D = NF + p + N n p i inv D N N N = F ln F + F + pinv = 0 N ( ) p + ρ lnρ = 0 inv ρ = F N Logic Block: n Stages Path Effort F N - n Etra Inverters Slide 35 Best Stage Effort ( ) p + ρ lnρ = 0 inv has no closed-form solution Neglecting parasitics (p inv = 0), we find ρ =.78 (e) For p inv =, solve numericall for ρ = 3.59 Slide 36 8

19 Sensitivit Analsis How sensitive is dela to using eactl the best number of stages?.6 D(N) /D(N) (ρ=6) (ρ =.) < ρ < 6 gives dela within 5% of optimal We can be slopp! I like ρ = N / N Slide 37 Eample, Revisited Ben Bitdiddle is the memor designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the A[3:0] A[3:0] decoder for a register file. 3 bits Decoder specifications: 6 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementar address inputs A[3:0] Each input ma drive 0 unit-sized transistors Ben needs to decide: How man stages to use? How large should each gate be? How fast can decoder operate? :6 Decoder Register File 6 words Slide 38 9

20 Number of Stages Decoder effort is mainl electrical and branching Electrical Effort: H = Branching Effort: B = If we neglect logical effort (assume G = ) Path Effort: F = Number of Stages: N = Slide 39 Number of Stages Decoder effort is mainl electrical and branching Electrical Effort: H = (3*3) / 0 = 9.6 Branching Effort: B = 8 If we neglect logical effort (assume G = ) Path Effort: F = GBH = 76.8 Number of Stages: N = log F = 3. Tr a 3-stage design Slide 0 0

21 Gate Sizes & Dela Logical Effort: G = Path Effort: F = Stage Effort: ˆf = Path Dela: Gate sizes: D = z = = A[3] A[3] A[] A[] A[] A[] A[0] A[0] z word[0] 96 units of wordline capacitance z word[5] Slide Gate Sizes & Dela Logical Effort: G = * 6/3 * = Path Effort: F = GBH = 5 /3 Stage Effort: f ˆ = F = 5.36 Path Dela: D= 3 fˆ =. Gate sizes: z = 96*/5.36 = 8 = 8*/5.36 = 6.7 A[3] A[3] A[] A[] A[] A[] A[0] A[0] z word[0] 96 units of wordline capacitance z word[5] Slide

22 Comparison Compare man alternatives with a spreadsheet Design NAND-INV NAND-NOR INV-NAND-INV NAND-INV-INV-INV NAND-NOR-INV-INV NAND-INV-NAND-INV INV-NAND-INV-NAND-INV NAND-INV-NAND-INV-INV-INV N G 0/9 0/9 6/9 6/9 6/9 P D Slide 3 Review of Definitions Term number of stages logical effort electrical effort branching effort effort effort dela parasitic dela dela Stage g h = b = Cout Cin Con-path + Coff-path Con-path f = gh f p d = f + p Path N G = g i H = Cout-path Cin-path B = b i F = GBH D F = fi P= p i D = d = D + P i F Slide

23 Method of Logical Effort ) Compute path effort ) Estimate best number of stages 3) Sketch path with N stages ) Estimate least dela 5) Determine best stage effort F = GBH N = log F N D = NF + P ˆ N f = F 6) Find gate sizes C ini = gc i fˆ outi Slide 5 Limits of Logical Effort Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic dela model Neglects input rise time effects Interconnect Iteration required in designs with wire Maimum speed onl Not minimum area/power for constrained dela Slide 6 3

24 Summar Logical effort is useful for thinking of dela in circuits Numeric logical effort characterizes gates NANDs are faster than NORs in CMOS Paths are fastest when effort delas are ~ Path dela is weakl sensitive to stages, sizes But using fewer stages doesn t mean faster paths Dela of path is about log F FO inverter delas Inverters and NAND best for driving large caps Provides language for discussing fast circuits But requires practice to master Slide 7