for System Modeling, Analysis, and Optimization

Size: px
Start display at page:

Download "for System Modeling, Analysis, and Optimization"

Transcription

1 Fundamental Algorithms for System Modeling, Analysis, and Optimization Stavros Tripakis UC Berkeley EECS 144/244 Fall 2013 Copyright 2013, E. A. Lee, J. Roydhowdhury, S. A. Seshia, S. Tripakis All rights reserved Timed automata Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 1 / 22

2 Timed Automata A formal model for dense-time systems [Alur and Dill(1994)] Developed mainly with verification in mind: in the basic TA variant, model-checking is decidable But also an elegant theoretical extension of the standard theory of regular and ω-regular languages. Many different TA variants, some undecidable. We will look at a basic variant. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 2 / 22

3 Timed Automaton A TA is a tuple C: finite set of clocks (C, Q, q 0, Inv, ) Q: finite set of control states; q 0 Q: initial control state Inv: a function assigning to each q Q an invariant : a finite set of actions, each being a tuple (q, q, g, C ) q, q Q: source and destination control states g: clock guard C : set of clocks to reset to 0, C C Invariants and guards are simple constraints on clocks, e.g., c 1, 0 < c 1 < 2 c 2 = 4, etc. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 3 / 22

4 Timed Automaton A TA is a tuple C: finite set of clocks (C, Q, q 0, Inv, ) Q: finite set of control states; q 0 Q: initial control state Inv: a function assigning to each q Q an invariant : a finite set of actions, each being a tuple (q, q, g, C ) q, q Q: source and destination control states g: clock guard C : set of clocks to reset to 0, C C Invariants and guards are simple constraints on clocks, e.g., c 1, 0 < c 1 < 2 c 2 = 4, etc. Can also have atomic propositions labeling control states, labels on actions, communication via shared memory or message passing, etc. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 3 / 22

5 Example: Timed Automaton A simple light controller: touch c 2 touch touch off light bright c := 0 c < 2 touch C = {c} Q = { off, light, bright } q 0 = off touch: action label (can be seen as the input symbol) Inv(q) = true for all q Q Actions: (off, light, true, {c}), (light, off, c 2, {}),... Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 4 / 22

6 Event-based vs. state-based models High-level: touch c 2 touch touch off light bright c := 0 c < 2 Low-level: touch Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 5 / 22

7 Timed Automata: Semantics A TA (C, Q, q 0, Inv, ) defines a transition system such that Set of states: S = Q R C + (S, S 0, R) R C + : the set of all functions v : C R + each v is called a valuation: it assigns a value to every clock Set of initial states: S 0 = {(q 0, v 0 )}, where we define v 0 (c) = 0 for all c C (i.e., all clocks are initially set to 0) Set of transitions: R = R t R d Rt : set of transitions modeling passage of time Rd : set of discrete transitions ( jumps between control states) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 6 / 22

8 Timed Automata: Semantics A TA (C, Q, q 0, Inv, ) defines a transition system such that Set of states: S = Q R C + (S, S 0, R) R C + : the set of all functions v : C R + each v is called a valuation: it assigns a value to every clock Set of initial states: S 0 = {(q 0, v 0 )}, where we define v 0 (c) = 0 for all c C (i.e., all clocks are initially set to 0) we could also define S 0 = {q 0 } R C + what does this say? Set of transitions: R = R t R d Rt : set of transitions modeling passage of time Rd : set of discrete transitions ( jumps between control states) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 6 / 22

9 Timed Automata: Discrete and Time Transitions where: R t = { ( (q, v), (q, v + t) ) t t : v + t = Inv(q)} R d = { ( (q, v), (q, v ) ) a = (q, q, g, C ) : v = g v = v[c := 0]} v + t is a new valuation u such that u(c) = v(c) + t for all c if g is a constraint, then v = g means v satisfies g v[c := 0] is a new valuation u such that u(c) = 0 if c C and u(c) = v(c) otherwise Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 7 / 22

10 Timed Automata: Discrete and Time Transitions where: R t = { ( (q, v), (q, v + t) ) t t : v + t = Inv(q)} R d = { ( (q, v), (q, v ) ) a = (q, q, g, C ) : v = g v = v[c := 0]} v + t is a new valuation u such that u(c) = v(c) + t for all c if g is a constraint, then v = g means v satisfies g v[c := 0] is a new valuation u such that u(c) = 0 if c C and u(c) = v(c) otherwise Instead of ( (q, v), (q, v + t) ) R t we write (q, v) (q, v + t). Instead of ( (q, v), (q, v ) ) a R d we write (q, v) (q, v ). t Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 7 / 22

11 Example: Alarm Modeled as a Timed Automaton stopped cancel? c 10 off c 10 c = 10 RING! Inv(off) = c 10 : automaton cannot spend more than 10 time units at control state off. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 8 / 22

12 Example: Alarm Modeled as a Timed Automaton stopped cancel? c 10 off c 10 c = 10 RING! Inv(off) = c 10 : automaton cannot spend more than 10 time units at control state off. What if we omit the invariant? Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 8 / 22

13 Example: Alarm Modeled as a Timed Automaton stopped cancel? c 10 off c 10 c = 10 RING! Does it work correctly if cancel arrives exactly when c = 10? Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 9 / 22

14 Example: Alarm Modeled as a Timed Automaton stopped cancel? c 10 off c 10 c = 10 RING! Does it work correctly if cancel arrives exactly when c = 10? Depends on the semantics of composition: if it s non-deterministic (as usually done) then alarm may still ring. Otherwise, must give higher priority to the cancel transition. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 9 / 22

15 Timed Automata Model-Checking: Reachability Basic question: is a given control state q reachable? i.e., does there exist some reachable state s = (q, v) in the transition system defined by the timed automaton? Many interesting questions about timed automata can be reduced to this question. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 10 / 22

16 Timed Automata Model-Checking: Reachability Basic question: is a given control state q reachable? i.e., does there exist some reachable state s = (q, v) in the transition system defined by the timed automaton? Many interesting questions about timed automata can be reduced to this question. Is the basic control-state reachability question decidable? Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 10 / 22

17 Timed Automata Reachability Not the same as discrete-state reachability! q 0 q 1 q 2 q 3 q 4 c 1 := 0 c 2 := 0 c 2 > 1 c 1 1 q 4 is reachable if we ignore the timing constraints. But is it really reachable? Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 11 / 22

18 Timed Automata Reachability Not the same as discrete-state reachability! q 0 q 1 q 2 q 3 q 4 c 1 := 0 c 2 := 0 c 2 > 1 c 1 1 q 4 is reachable if we ignore the timing constraints. But is it really reachable? No: at q 3, c 2 > 1 and c 1 c 2, therefore c 1 > 1 also. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 11 / 22

19 Timed Automata Model-Checking: Reachability A less obvious example: Fischer s mutual exclusion protocol. Suppose we have many processes, each behaving like the TA above. Is mutual-exclusion guaranteed? I.e., at most 1 process is in critical section (control state cs) at any given time. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 12 / 22

20 Timed Automata Model-Checking: Reachability Brute-force idea: exhaustive state-space exploration of the transition system defined by the timed automaton does not work since state-space is infinite (even uncountable) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 13 / 22

21 Timed Automata Model-Checking: Reachability Brute-force idea: exhaustive state-space exploration of the transition system defined by the timed automaton does not work since state-space is infinite (even uncountable) Yet problem is decidable! [Alur-Dill 94] Key idea: Region equivalence: partitions the state-space into finite number of equivalence classes (regions) Perform reachability on finite (abstract) state-space Can prove that q is reachable in the abstract space iff it is reachable in the concrete space Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 13 / 22

22 The Region Equivalence y Fig. 3: Set of regio straints with two clo Key idea: two valuations v 1, v 2 are equivalent iff: 2 2) 1. v 1 satisfies a guard g iff v 2 satisfies g. ( X +1)2. Note tha 2. 1 rect for M-bounded v 1 can lead to some v 1 satisfying a guard g with a discrete transition iff v 2 can do the same. 3. 0v 1 can1 lead2to some v x1 satisfying a guard g with a timeregion automata f (a) transition Partition iffcompatible v 2 can dowith the same. constraints, not with time elapsing (the two Let A be a timed au Region = equivalence class w.r.t. region equivalence = set of Let allm be the max points and can not be equivalent) equivalent valuations. of the constraints o of regions for A. F y Region in gray: subsections, we get 1 < region x < 2defined 1 < by: y < 2 Alur x > y. and Dill [6, 7] 2 Other 8 regions: < 1 < x < 2 fication of timed sy x = y = 0, 1 0 < 1 < y 2 : x = y < 1, {x} {y} x = 0 0 < y < 1, Theorem 1 (Alur & x etc. equivalently empti (b) Partition compatible with constraints, time elapsing (and resets) Pictures in this and other slides taken from [Bouyer(2005)]. automata. It is (for both diagonal- Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 14 / 22

23 The Region Equivalence: 0 1Finiteness 2 x (a) Partition compatible with constraints, notclasses: with timebounded elapsing (the by two constant c = Finite number of equivalence maximal constant appearing points and in a can guard notor be invariant. equivalent) y 2 1 region defined by: 8 < 1 < x < 2 1 < y < 2 : {x} < {y} x Some regions are unbounded, e.g.: x > 2 0 < y < 1 x > 2 y > 2 etc. (b) Partition compatible with constraints, time elapsing (and resets) Fig. 2: Diagonal-free region partitioning for two clocks and maximal constant 2 Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 15 / 22

24 0 1 2 x Region x automata for classic (a) Partition compatible with con-(astraints, not with time elapsing (the twostraints, not with time elapsing Let(the Mtwo be the maximal const Partition compatible Let withacon- be a timed automaton w points and can not be equivalent) points and can not be equivalent) A graph of regions: one region space for each control of the location. constraints of A, the s of regions for A. From the re y y subsections, we get the follow region defined by: Alur and Dill region [6, defined 7], which by: is < 1 < x < 2 fication of timed 8 systems. < 1 < x < < y < 2 1 < y < 2 : : {x} < {y} {x} < {y} Theorem 1 (Alur & Dill 90 s x equivalently x emptiness) is d (b) Partition compatible with constraints, time elapsing q 1 (and resets) straints, time elapsing q 2 (and resets) (b) Partition compatible automata. with con- It is a PSPACE (for both diagonal-free as we automata). Nodes: pairs Fig. (q, 2: r) Diagonal-free where region partitioning Fig. 2: Diagonal-free for two region partitioning for two clocks and maximal constant 2 clocks and maximal constant Although 2 this theorem has bee q is a control location of the timed automaton. the proof we choose to sketc where it is written in details. r is a region. It is easy to prove (and left as an It exercise) easy tothe prove fol-(anlowing lemma: lowing lemma: left as an exercise) the fol- Proof. [Sketch] PSPACE mem size of th region automaton Two types of edges: Lemma 1 The partitioning R M the size of the original auto df Lemma (X) is a1 set The ofpartitioning regions for the constraints Cdf M(X). NLOGSPACE complexity of th R M df (X) is a set of regions for the constraints a (q, r) (q, r ): discrete transition lem Cdf M(X). in classical untimed graph (q, r) time Roughly (q, r counting ): time transition all possible Roughly combinations counting all ability possible in timed combinations automata can b above, we can bound the number above, of we regions can bound in the PSPACE-hardness number of regions can be in prov R M (X) by 2 X. X!.(2M + 2) R X M (X) where by 2 X. X!.(2M is termination + 2) X of where a linearly X isboun The Region Graph Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 16 / 22

25 Decidability Theorem ([Alur and Dill(1994)]) reachable state (q, v) in a timed automaton iff reachable node (q, r) in its region graph. Finite # regions and control states Region graph is finite Reachability is decidable. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 17 / 22

26 The Problem with Regions STATE EXPLOSION! Worst-case number of regions: O(2 n n! c n ) where n is the number of clocks and c is the maximal constant. This is actually often close to the actual number of regions no practical tool uses regions. Model-checkers for TA (Uppaal, Kronos,...) have improved upon the region-graph idea and use symbolic techniques. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 18 / 22

27 ints (x 1 3) (x 2 5) (x 1 x 2 4). zone, Fromdepicted Regions below to Zones the right, can be repnted by the DBM below (on the left) Zone: a convex union of regions, e.g., x 1 3 x 2 5 x 1 x 2 4. x 0 x 1 x one can have several representations using s. For example, the zone of the previous ple can equivalently be represented by the Termination needs som lated to properties of t ciated with timed auto then relies on the follo proved as an exercise. Lemma 2 Let A be R be a set of regions and ➂ (for A). Consi p i=1 R i (with R i R following holds: - p i=1 R i is a fini - [Y 0] 1 ( p i= gions (for any set - g ( p i=1 R i) is is a constraint of Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 19 / 22

28 ints (x 1 3) (x 2 5) (x 1 x {v 2 : 4). X Termination i, j, v(x i ) needs v(x j som ) zone, Fromdepicted Regions below to Zones the right, can be repnted by the DBM below (on the lated to properties of t left). 0 where γ < simply means that γ i Zone: a convex union of regions, e.g., without x 1 3 bound. ciated x 2 5 This with timed auto x 1 xsubset 2 4. of n is will be denoted, then in what relies follows, on theby follo M proved as an exercise. x 0 x 1 x follows, to simplify notations, we will 2 5 all constraints are non-strict, so that c DBMs will be Lemma elements 2of Let A{ }. be 1 2 R be a set of regions 2 Example 3 Consider and ➂ (for the zone A). defined Consi p straints (x i=1 R 1 3) (xi 2 (with 5) R i (x 1 R This zone, depicted following belowholds: on the right, Key property: can be represented efficiently resented usingby difference the DBM one can have several representations using - bound below p i=1 s. For example, the zone of the previous R (on the lef matrices (DBMs) [Dill(1989)]. i is a fini ple can equivalently be represented by the - [Y 0] 1 ( p x 0 x 1 x 2 i= x 0 gions (for any set x 1 3 x x x 2 +4 : x g ( p2 x i=1 R 2 5 i) is is a constraint of Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 19 / 22

29 Symbolic Manipulations of Zones using DBMs DBMs = the BDDs of the timed automata world. Time elapse, guard intersection, clock resets, are all easily implementable in DBMs. Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 20 / 22

30 Symbolic Manipulations of Zones using DBMs DBMs = the BDDs of the timed automata world. Time elapse, guard intersection, clock resets, are all easily implementable in DBMs. Is zone union implementable with DBMs? Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 20 / 22

31 Symbolic Manipulations of Zones using DBMs DBMs = the BDDs of the timed automata world. Time elapse, guard intersection, clock resets, are all easily implementable in DBMs. Is zone union implementable with DBMs? No! The union of two zones in general is not a zone. often state explosion even with zones... Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 20 / 22

32 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

33 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

34 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

35 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

36 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

37 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

38 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) let time elapse: Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

39 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) let time elapse: (q 1, c 2 c 1 ) Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

40 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) let time elapse: (q 1, c 2 c 1 ) take discrete transition to q 2 : Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

41 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) let time elapse: (q 1, c 2 c 1 ) take discrete transition to q 2 : cannot because c 1 > 1 c 2 1 c 2 c 1 is UNSAT Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

42 Timed Automata Reachability: Simple Example q 0 c 1 := 0 q 1 c 1 > 1 q 2 c 2 1 Is q 2 reachable? (initially, c 1 = c 2 = 0) Symbolic reachability analysis: step symbolic state initially: (q 0, c 1 = 0 c 2 = 0) let time elapse: (q 0, c 1 = c 2 ) take discrete transition to q 1 : (q 1, c 1 = 0 c 2 c 1 ) let time elapse: (q 1, c 2 c 1 ) take discrete transition to q 2 : cannot because c 1 > 1 c 2 1 c 2 c 1 is UNSAT therefore q 2 not reachable Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 21 / 22

43 Bibliography R. Alur. Timed automata. NATO-ASI 1998 Summer School on Verification of Digital and Hybrid Systems, R. Alur and D. Dill. A theory of timed automata. Theoretical Computer Science, 126: , P. Bouyer. An introduction to timed automata. At D. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems, volume 407 of LNCS, pages Springer, Stavros Tripakis: EECS 144/244 Fall 2013 Timed Automata 22 / 22

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Sanjit A. Seshia and Randal E. Bryant Computer Science Department Carnegie Mellon University Verifying Timed Embedded Systems

More information

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang Timed Automata Semantics, Algorithms and Tools Zhou Huaiyang Agenda } Introduction } Timed Automata } Formal Syntax } Operational Semantics } Verification Problems } Symbolic Semantics & Verification }

More information

Models for Efficient Timed Verification

Models for Efficient Timed Verification Models for Efficient Timed Verification François Laroussinie LSV / ENS de Cachan CNRS UMR 8643 Monterey Workshop - Composition of embedded systems Model checking System Properties Formalizing step? ϕ Model

More information

The algorithmic analysis of hybrid system

The algorithmic analysis of hybrid system The algorithmic analysis of hybrid system Authors: R.Alur, C. Courcoubetis etc. Course teacher: Prof. Ugo Buy Xin Li, Huiyong Xiao Nov. 13, 2002 Summary What s a hybrid system? Definition of Hybrid Automaton

More information

Timed Automata VINO 2011

Timed Automata VINO 2011 Timed Automata VINO 2011 VeriDis Group - LORIA July 18, 2011 Content 1 Introduction 2 Timed Automata 3 Networks of timed automata Motivation Formalism for modeling and verification of real-time systems.

More information

Recent results on Timed Systems

Recent results on Timed Systems Recent results on Timed Systems Time Petri Nets and Timed Automata Béatrice Bérard LAMSADE Université Paris-Dauphine & CNRS berard@lamsade.dauphine.fr Based on joint work with F. Cassez, S. Haddad, D.

More information

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Discrete Systems Lecture: Automata, State machines, Circuits Stavros Tripakis University of California, Berkeley Stavros

More information

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints Chapter 10 Timed Automata In the previous chapter, we have discussed a temporal logic where time was a discrete entities. A time unit was one application of the transition relation of an LTS. We could

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related work

More information

Undecidability Results for Timed Automata with Silent Transitions

Undecidability Results for Timed Automata with Silent Transitions Fundamenta Informaticae XXI (2001) 1001 1025 1001 IOS Press Undecidability Results for Timed Automata with Silent Transitions Patricia Bouyer LSV, ENS Cachan, CNRS, France bouyer@lsv.ens-cachan.fr Serge

More information

On decision problems for timed automata

On decision problems for timed automata On decision problems for timed automata Olivier Finkel Equipe de Logique Mathématique, U.F.R. de Mathématiques, Université Paris 7 2 Place Jussieu 75251 Paris cedex 05, France. finkel@logique.jussieu.fr

More information

State-Space Exploration. Stavros Tripakis University of California, Berkeley

State-Space Exploration. Stavros Tripakis University of California, Berkeley EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 State-Space Exploration Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE

More information

EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016

EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 Discrete Event Simulation Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley)

More information

Real-Time Systems. Lecture 15: The Universality Problem for TBA Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany

Real-Time Systems. Lecture 15: The Universality Problem for TBA Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany Real-Time Systems Lecture 15: The Universality Problem for TBA 2013-06-26 15 2013-06-26 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: Extended Timed

More information

Robust Reachability in Timed Automata: A Game-based Approach

Robust Reachability in Timed Automata: A Game-based Approach Robust Reachability in Timed Automata: A Game-based Approach Patricia Bouyer, Nicolas Markey, and Ocan Sankur LSV, CNRS & ENS Cachan, France. {bouyer,markey,sankur}@lsv.ens-cachan.fr Abstract. Reachability

More information

Reachability Results for Timed Automata with Unbounded Data Structures

Reachability Results for Timed Automata with Unbounded Data Structures Acta Informatica manuscript No. (will be inserted by the editor) Reachability Results for Timed Automata with Unbounded Data Structures Ruggero Lanotte Andrea Maggiolo-Schettini Angelo Troina Received:

More information

arxiv: v1 [cs.fl] 25 Nov 2018

arxiv: v1 [cs.fl] 25 Nov 2018 Real-Time Systems Modeling and Analysis Lakhan Shiva Kamireddy [0000 0001 6007 5408] University of Colorado, Boulder CO 80302, USA {lakhan.kamireddy}@colorado.edu arxiv:1811.10083v1 [cs.fl] 25 Nov 2018

More information

TCTL model-checking of Time Petri Nets

TCTL model-checking of Time Petri Nets 1 TCTL model-checking of Time Petri Nets Hanifa Boucheneb 1, Guillaume Gardey 2,3 and Olivier H. Roux 2 Affiliations : 1 : École polytechnique de Montréal, C.P. 6079, succ. Centre-ville Montréal H3C3A7

More information

Robust Controller Synthesis in Timed Automata

Robust Controller Synthesis in Timed Automata Robust Controller Synthesis in Timed Automata Ocan Sankur LSV, ENS Cachan & CNRS Joint with Patricia Bouyer, Nicolas Markey, Pierre-Alain Reynier. Ocan Sankur (ENS Cachan) Robust Control in Timed Automata

More information

Clock Matrix Diagrams

Clock Matrix Diagrams Clock Matrix Diagrams U N I V E R S I T A S S A R A V I E N I S S Bachelor s Thesis Daniel Fass daniel@react.cs.uni-sb.de Reactive Systems Group Department of Computer Science Universität des Saarlandes

More information

Lecture 6: Reachability Analysis of Timed and Hybrid Automata

Lecture 6: Reachability Analysis of Timed and Hybrid Automata University of Illinois at Urbana-Champaign Lecture 6: Reachability Analysis of Timed and Hybrid Automata Sayan Mitra Special Classes of Hybrid Automata Timed Automata ß Rectangular Initialized HA Rectangular

More information

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations (Extended Abstract) Gaoyan Xie, Cheng Li and Zhe Dang School of Electrical Engineering and

More information

The State Explosion Problem

The State Explosion Problem The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis

More information

Folk Theorems on the Determinization and Minimization of Timed Automata

Folk Theorems on the Determinization and Minimization of Timed Automata Folk Theorems on the Determinization and Minimization of Timed Automata Stavros Tripakis VERIMAG Centre Equation 2, avenue de Vignate, 38610 Gières, France www-verimag.imag.fr Abstract. Timed automata

More information

Monitoring and Fault-Diagnosis with Digital Clocks

Monitoring and Fault-Diagnosis with Digital Clocks Author manuscript, published in "6th Int. Conf. on Application of Concurrency to System Design (ACSD'06) (2006)" Monitoring and Fault-Diagnosis with Digital Clocks Karine Altisen Verimag Laboratory Karine.Altisen@imag.fr

More information

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone Hourglass Automata Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone The University of Western Australia. yuki.osada@research.uwa.edu.au, {tim.french,mark.reynolds}@uwa.edu.au, 21306592@student.uwa.edu.au

More information

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for?

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for? Computer Engineering and Networks Overview Discrete Event Systems Verification of Finite Automata Lothar Thiele Introduction Binary Decision Diagrams Representation of Boolean Functions Comparing two circuits

More information

Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication

Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication Stavros Tripakis Abstract We introduce problems of decentralized control with communication, where we explicitly

More information

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey Language Preservation Problems in Parametric Timed Automata Étienne André and Nicolas Markey June 2015 Research report LSV-15-05 (Version 1) Laboratoire Spécification & Vérification École Normale Supérieure

More information

The efficiency of identifying timed automata and the power of clocks

The efficiency of identifying timed automata and the power of clocks The efficiency of identifying timed automata and the power of clocks Sicco Verwer a,b,1,, Mathijs de Weerdt b, Cees Witteveen b a Eindhoven University of Technology, Department of Mathematics and Computer

More information

Beyond Lassos: Complete SMT-Based Bounded Model Checking for Timed Automata

Beyond Lassos: Complete SMT-Based Bounded Model Checking for Timed Automata Beyond Lassos: Complete SMT-Based ed Model Checking for d Automata Roland Kindermann, Tommi Junttila, and Ilkka Niemelä Aalto University Department of Information and Computer Science P.O.Box 15400, FI-00076

More information

An Introduction to Hybrid Systems Modeling

An Introduction to Hybrid Systems Modeling CS620, IIT BOMBAY An Introduction to Hybrid Systems Modeling Ashutosh Trivedi Department of Computer Science and Engineering, IIT Bombay CS620: New Trends in IT: Modeling and Verification of Cyber-Physical

More information

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Stavros Tripakis David Broman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report

More information

A Decidable Class of Planar Linear Hybrid Systems

A Decidable Class of Planar Linear Hybrid Systems A Decidable Class of Planar Linear Hybrid Systems Pavithra Prabhakar, Vladimeros Vladimerou, Mahesh Viswanathan, and Geir E. Dullerud University of Illinois at Urbana-Champaign. Abstract. The paper shows

More information

Dense-Timed Pushdown Automata

Dense-Timed Pushdown Automata Dense-Timed Pushdown Automata Parosh Aziz Abdulla Uppsala University Sweden Mohamed Faouzi Atig Uppsala University Sweden Jari Stenman Uppsala University Sweden Abstract We propose a model that captures

More information

Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata

Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata IT 12 034 Examensarbete 15 hp Juli 2012 Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata Kristiina Ausmees Institutionen för informationsteknologi Department of Information Technology

More information

A Simplified Approach for Testing Real-Time Systems Based on Action Refinement

A Simplified Approach for Testing Real-Time Systems Based on Action Refinement A Simplified Approach for Testing Real-Time Systems Based on Action Refinement Saddek Bensalem, Moez Krichen, Lotfi Majdoub, Riadh Robbana, Stavros Tripakis Verimag Laboratory, Centre Equation 2, avenue

More information

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS TKK Reports in Information and Computer Science Espoo 2008 TKK-ICS-R3 MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS Jussi Lahtinen ABTEKNILLINEN KORKEAKOULU TEKNISKA HÖGSKOLAN HELSINKI UNIVERSITY OF

More information

An introduction to Uppaal and Timed Automata MVP5 1

An introduction to Uppaal and Timed Automata MVP5 1 An introduction to Uppaal and Timed Automata MVP5 1 What is Uppaal? (http://www.uppaal.com/) A simple graphical interface for drawing extended finite state machines (automatons + shared variables A graphical

More information

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA Time(d) Petri Net Serge Haddad LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA haddad@lsv.ens-cachan.fr Petri Nets 2016, June 20th 2016 1 Time and Petri Nets 2 Time Petri Net: Syntax and Semantic

More information

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Stavros Tripakis Aalto University and University of California, Berkeley Abstract FMI (Functional Mockup Interface) is a standard

More information

Using non-convex approximations for efficient analysis of timed automata: Extended version

Using non-convex approximations for efficient analysis of timed automata: Extended version Using non-convex approximations for efficient analysis of timed automata: Extended version Frédéric Herbreteau, D. Kini, B. Srivathsan, Igor Walukiewicz To cite this version: Frédéric Herbreteau, D. Kini,

More information

Sanjit A. Seshia EECS, UC Berkeley

Sanjit A. Seshia EECS, UC Berkeley EECS 219C: Computer-Aided Verification Explicit-State Model Checking: Additional Material Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: G. Holzmann Checking if M satisfies : Steps 1. Compute Buchi

More information

Serge Haddad Mathieu Sassolas. Verification on Interrupt Timed Automata. Research Report LSV-09-16

Serge Haddad Mathieu Sassolas. Verification on Interrupt Timed Automata. Research Report LSV-09-16 Béatrice Bérard Serge Haddad Mathieu Sassolas Verification on Interrupt Timed Automata Research Report LSV-09-16 July 2009 Verification on Interrupt Timed Automata Béatrice Bérard 1, Serge Haddad 2, Mathieu

More information

Hybrid systems and computer science a short tutorial

Hybrid systems and computer science a short tutorial Hybrid systems and computer science a short tutorial Eugene Asarin Université Paris 7 - LIAFA SFM 04 - RT, Bertinoro p. 1/4 Introductory equations Hybrid Systems = Discrete+Continuous SFM 04 - RT, Bertinoro

More information

Basic Problems in Multi-View Modeling

Basic Problems in Multi-View Modeling Basic Problems in Multi-View Modeling Jan Reineke Stavros Tripakis Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2014-4 http://www.eecs.berkeley.edu/pubs/techrpts/2014/eecs-2014-4.html

More information

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Ulrich Kühne LSV ENS de Cachan, 94235 Cachan Cedex, France, kuehne@lsv.ens-cachan.fr 1 Introduction Boost converter circuits are an important

More information

A Brief Introduction to Model Checking

A Brief Introduction to Model Checking A Brief Introduction to Model Checking Jan. 18, LIX Page 1 Model Checking A technique for verifying finite state concurrent systems; a benefit on this restriction: largely automatic; a problem to fight:

More information

TIMED automata, introduced by Alur and Dill in [3], have

TIMED automata, introduced by Alur and Dill in [3], have 1 Language Inclusion Checking of Timed Automata with Non-Zenoness Xinyu Wang, Jun Sun, Ting Wang, and Shengchao Qin Abstract Given a timed automaton P modeling an implementation and a timed automaton S

More information

Symbolic Real Time Model Checking. Kim G Larsen

Symbolic Real Time Model Checking. Kim G Larsen Smbolic Real Time Model Checking Kim G Larsen Overview Timed Automata Decidabilit Results The UPPAAL Verification Engine Datastructures for zones Liveness Checking Algorithm Abstraction and Compositionalit

More information

models based on maximality semantics present concurrent actions differently from choice [11], because of non atomicity of actions. These models advoca

models based on maximality semantics present concurrent actions differently from choice [11], because of non atomicity of actions. These models advoca Maximality-based Region Graph: a Novel Alternative Riadh MATMAT Ilham KITOUNI Souad GUELLATI D-Eddine SAIDOUNI, MISC Laboratory, Constantine 2 University, 25000, Algeria {matmat; kitouni; guellati; saidouni}@misc-umc.org

More information

Abstractions and Decision Procedures for Effective Software Model Checking

Abstractions and Decision Procedures for Effective Software Model Checking Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture

More information

When are Timed Automata Determinizable?

When are Timed Automata Determinizable? When are Timed Automata Determinizable? Christel Baier 1, Nathalie Bertrand 2, Patricia Bouyer 3, and Thomas Brihaye 4 1 Technische Universität Dresden, Germany 2 INRIA Rennes Bretagne Atlantique, France

More information

Design and Verification of Long Running Transactions in a Timed Framework

Design and Verification of Long Running Transactions in a Timed Framework Design and Verification of Long Running Transactions in a Timed Framework Ruggero Lanotte a, Andrea Maggiolo Schettini b, Paolo Milazzo b, Angelo Troina c, a Dipartimento di Scienze della Cultura, Politiche

More information

An Introduction to Timed Automata

An Introduction to Timed Automata An Introduction to Timed Automata Patricia Bouer LSV CNRS & ENS de Cachan 6, avenue du Président Wilson 943 Cachan France email: bouer@lsv.ens-cachan.fr Introduction Explicit timing constraints are naturall

More information

Partial Order Reductions for Timed Systems

Partial Order Reductions for Timed Systems Partial Order Reductions for Timed Systems Johan Bengtsson 1 Bengt Jonsson 1 Johan Lilius 2 Wang Yi 1 1 Department of Computer Systems, Uppsala University, Sweden. Email: {bengt,johanb,yi}@docs.uu.se 2

More information

models, languages, dynamics Eugene Asarin PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics LIAFA - University Paris Diderot and CNRS

models, languages, dynamics Eugene Asarin PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics LIAFA - University Paris Diderot and CNRS models, s, LIAFA - University Paris Diderot and CNRS PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics Context A model for verification of real-time systems Invented by Alur and Dill in early

More information

Diagnosis of Dense-Time Systems using Digital-Clocks

Diagnosis of Dense-Time Systems using Digital-Clocks Diagnosis of Dense-Time Systems using Digital-Clocks Shengbing Jiang GM R&D and Planning Mail Code 480-106-390 Warren, MI 48090-9055 Email: shengbing.jiang@gm.com Ratnesh Kumar Dept. of Elec. & Comp. Eng.

More information

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University Modelling Real-Time Systems Henrik Ejersbo Jensen Aalborg University Hybrid & Real Time Systems Control Theory Plant Continuous sensors actuators Task TaskTask Controller Program Discrete Computer Science

More information

Robustness and Implementability of Timed Automata

Robustness and Implementability of Timed Automata Robustness and Implementability of Timed Automata Martin De Wulf, Laurent Doyen, Nicolas Markey, and Jean-François Raskin Computer Science Departement, Université Libre de Bruxelles, Belgium Abstract.

More information

Lecture 11: Timed Automata

Lecture 11: Timed Automata Real-Time Systems Lecture 11: Timed Automata 2014-07-01 11 2014-07-01 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: DC (un)decidability This Lecture:

More information

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main Real-Time Systems Lecture 10: Timed Automata 2013-06-04 10 2013-06-04 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: PLC, PLC automata This Lecture:

More information

Liveness in L/U-Parametric Timed Automata

Liveness in L/U-Parametric Timed Automata Liveness in L/U-Parametric Timed Automata Étienne André and Didier Lime [AL17] Université Paris 13, LIPN and École Centrale de Nantes, LS2N Highlights, 14 September 2017, London, England Étienne André

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University Email: {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related

More information

Timed Automata with Observers under Energy Constraints

Timed Automata with Observers under Energy Constraints Timed Automata with Observers under Energy Constraints Patricia Bouyer-Decitre Uli Fahrenberg Kim G. Larsen Nicolas Markey LSV, CNRS & ENS Cachan, France Aalborg Universitet, Danmark /9 Introduction The

More information

Computer-Aided Program Design

Computer-Aided Program Design Computer-Aided Program Design Spring 2015, Rice University Unit 3 Swarat Chaudhuri February 5, 2015 Temporal logic Propositional logic is a good language for describing properties of program states. However,

More information

On Reachability for Hybrid Automata over Bounded Time

On Reachability for Hybrid Automata over Bounded Time On Reachability for Hybrid Automata over Bounded Time Thomas Brihaye, Laurent Doyen 2, Gilles Geeraerts 3, Joël Ouaknine 4, Jean-François Raskin 3, and James Worrell 4 Université de Mons, Belgium 2 LSV,

More information

The Verification of Real Time Systems using the TINA Tool

The Verification of Real Time Systems using the TINA Tool Proceedings of the 17th World Congress The International Federation of Automatic Control The Verification of Real Time Systems using the TINA Tool Pedro M. Gonzalez del Foyo Jose Reinaldo Silva Dept. Of

More information

State Explosion in Almost-Sure Probabilistic Reachability

State Explosion in Almost-Sure Probabilistic Reachability State Explosion in Almost-Sure Probabilistic Reachability François Laroussinie Lab. Spécification & Vérification, ENS de Cachan & CNRS UMR 8643, 61, av. Pdt. Wilson, 94235 Cachan Cedex France Jeremy Sproston

More information

Automata, Logic and Games: Theory and Application

Automata, Logic and Games: Theory and Application Automata, Logic and Games: Theory and Application 1. Büchi Automata and S1S Luke Ong University of Oxford TACL Summer School University of Salerno, 14-19 June 2015 Luke Ong Büchi Automata & S1S 14-19 June

More information

Modeling & Control of Hybrid Systems. Chapter 7 Model Checking and Timed Automata

Modeling & Control of Hybrid Systems. Chapter 7 Model Checking and Timed Automata Modeling & Control of Hybrid Systems Chapter 7 Model Checking and Timed Automata Overview 1. Introduction 2. Transition systems 3. Bisimulation 4. Timed automata hs check.1 1. Introduction Model checking

More information

EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014

EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 Discrete Event Simulation Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley)

More information

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science

More information

Alan Bundy. Automated Reasoning LTL Model Checking

Alan Bundy. Automated Reasoning LTL Model Checking Automated Reasoning LTL Model Checking Alan Bundy Lecture 9, page 1 Introduction So far we have looked at theorem proving Powerful, especially where good sets of rewrite rules or decision procedures have

More information

DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES

DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES Maxim Gromov 1, Khaled El-Fakih 2, Natalia Shabaldina 1, Nina Yevtushenko 1 1 Tomsk State University, 36 Lenin Str.. Tomsk, 634050, Russia gromov@sibmail.com,

More information

On Timed Components and their Abstraction

On Timed Components and their Abstraction On Timed Components and their Abstraction Ramzi Ben Salah VERIMAG 2, av. de Vignate 386 Gieres, France Ramzi.Salah@imag.fr Marius Bozga VERIMAG 2, av. de Vignate 386 Gieres, France Marius.Bozga@imag.fr

More information

Introduction to Embedded Systems

Introduction to Embedded Systems Introduction to Embedded Systems Edward A. Lee & Sanjit A. Seshia UC Berkeley EECS 124 Spring 2008 Copyright 2008, Edward A. Lee & Sanjit A. Seshia, All rights reserved Lecture 6: Modeling Modal Behavior,

More information

Symmetry Reduction and Compositional Verification of Timed Automata

Symmetry Reduction and Compositional Verification of Timed Automata Symmetry Reduction and Compositional Verification of Timed Automata Hoang Linh Nguyen University of Waterloo Waterloo, Canada Email: nhoangli@uwaterloo.ca Richard Trefler University of Waterloo Waterloo,

More information

Synchronized Recursive Timed Automata

Synchronized Recursive Timed Automata Synchronized Recursive Timed Automata Yuya Uezato 1 and Yasuhiko Minamide 2 1 University of Tsukuba uezato@score.cs.tsukuba.ac.jp 2 Tokyo Institute of Technology minamide@is.titech.ac.jp Abstract. We present

More information

Classes and conversions

Classes and conversions Classes and conversions Regular expressions Syntax: r = ε a r r r + r r Semantics: The language L r of a regular expression r is inductively defined as follows: L =, L ε = {ε}, L a = a L r r = L r L r

More information

Software Verification with Abstraction-Based Methods

Software Verification with Abstraction-Based Methods Software Verification with Abstraction-Based Methods Ákos Hajdu PhD student Department of Measurement and Information Systems, Budapest University of Technology and Economics MTA-BME Lendület Cyber-Physical

More information

Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences

Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences Patricia Bouyer 1, Serge Haddad 2, Pierre-Alain Reynier 1 1 LSV, CNRS & ENS Cachan, France 2 LAMSADE, CNRS & Université

More information

Part I: Definitions and Properties

Part I: Definitions and Properties Turing Machines Part I: Definitions and Properties Finite State Automata Deterministic Automata (DFSA) M = {Q, Σ, δ, q 0, F} -- Σ = Symbols -- Q = States -- q 0 = Initial State -- F = Accepting States

More information

Verifying Quantitative Properties of Continuous Probabilistic Timed Automata

Verifying Quantitative Properties of Continuous Probabilistic Timed Automata Verifying Quantitative Properties of Continuous Probabilistic Timed Automata Marta Kwiatkowska 1, Gethin Norman 1, Roberto Segala 2 and Jeremy Sproston 2 1 University of Birmingham, Birmingham B15 2TT,

More information

An Efficient State Space Generation for the Analysis of Real-Time Systems

An Efficient State Space Generation for the Analysis of Real-Time Systems University of Pennsylvania ScholarlyCommons Departmental Papers (CIS) Department of Computer & Information Science May 2000 An Efficient State Space Generation for the Analysis of Real-Time Systems Inhye

More information

Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata

Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata WOJCIECH PENCZEK ICS PAS, Warsaw, Poland joint work with Agata Półrola University of Lodz, Poland Many thanks

More information

Decision Problems for Parametric Timed Automata

Decision Problems for Parametric Timed Automata Decision Problems for Parametric Timed Automata Étienne André 1,2, Didier Lime 1, and Olivier H. Roux 1 1 École Centrale de Nantes, IRCCyN, CNRS, UMR 6597, France 2 Université Paris 13, Sorbonne Paris

More information

Automata-based Verification - III

Automata-based Verification - III CS3172: Advanced Algorithms Automata-based Verification - III Howard Barringer Room KB2.20/22: email: howard.barringer@manchester.ac.uk March 2005 Third Topic Infinite Word Automata Motivation Büchi Automata

More information

Scaling BDD-based Timed Verification with Simulation Reduction

Scaling BDD-based Timed Verification with Simulation Reduction Scaling BDD-based Timed Verification with Simulation Reduction Truong Khanh Nguyen 1,Tian Huat Tan 2, Jun Sun 2, Jiaying Li 2, Yang Liu 3, Manman Chen 2, Jin Song Dong 4 Autodesk 1 Singapore University

More information

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata Control Synthesis of Discrete Manufacturing Systems using Timed Finite utomata JROSLV FOGEL Institute of Informatics Slovak cademy of Sciences ratislav Dúbravská 9, SLOVK REPULIC bstract: - n application

More information

Automata-theoretic Decision of Timed Games

Automata-theoretic Decision of Timed Games Automata-theoretic Decision of Timed Games Marco Faella a, Salvatore La Torre b, Aniello Murano a a Università degli Studi di Napoli Federico II, 80126 Napoli {faella, murano}@na.infn.it b Università degli

More information

Controller Synthesis for MTL Specifications

Controller Synthesis for MTL Specifications Controller Synthesis for MTL Specifications Patricia Bouyer, Laura Bozzelli, and Fabrice Chevalier LSV, CNRS & ENS Cachan, France {bouyer,bozzelli,chevalie}@lsv.ens-cachan.fr Abstract. We consider the

More information

Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method

Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method Laurent Fribourg and Ulrich Kühne LSV ENS de Cachan, 94235 Cachan, France {kuehne,fribourg}@lsv.ens-cachan.fr Abstract.

More information

Verification of Polynomial Interrupt Timed Automata

Verification of Polynomial Interrupt Timed Automata Verification of Polynomial Interrupt Timed Automata Béatrice Bérard 1, Serge Haddad 2, Claudine Picaronny 2, Mohab Safey El Din 1, Mathieu Sassolas 3 1 Université P. & M. Curie, LIP6 2 ENS Cachan, LSV

More information

Lower-Bound Constrained Runs in Weighted Timed Automata

Lower-Bound Constrained Runs in Weighted Timed Automata Lower-Bound Constrained Runs in Weighted Timed Automata Patricia Bouyer LSV ENS Cachan & CNRS Email: bouyer@lsv.ens-cachan.fr Kim G. Larsen Dept. Computer Science Aalborg. Email:kgl@cs.aau.dk Nicolas Markey

More information

COMPILING REAL-TIME SCENARIOS INTO A TIMED AUTOMATON*

COMPILING REAL-TIME SCENARIOS INTO A TIMED AUTOMATON* COMPILING REAL-TIME SCENARIOS INTO A TIMED AUTOMATON* Aziz Salah, Rachida Dssouli, Guy Lapalme Département d Informatique et de Recherche Opérationnelle, Université de Montréal, H3T 1J4 Montreal, PQ, Canada

More information

Reachability-Time Games on Timed Automata (Extended Abstract)

Reachability-Time Games on Timed Automata (Extended Abstract) Reachability-Time Games on Timed Automata (Extended Abstract) Marcin Jurdziński and Ashutosh Trivedi Department of Computer Science, University of Warwick, UK Abstract. In a reachability-time game, players

More information

Verification of Linear Duration Invariants by Model Checking CTL Properties

Verification of Linear Duration Invariants by Model Checking CTL Properties UNU-IIST International Institute for Software Technology Verification of Linear Duration Invariants by Model Checking CTL Properties Miaomiao Zhang, Dang Van Hung and Zhiming Liu June 2008 UNU-IIST Report

More information

Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago

Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago Symmetry Reductions. A. Prasad Sistla University Of Illinois at Chicago Model-Checking Concurrent PGM Temporal SPEC Model Checker Yes/No Counter Example Approach Build the global state graph Algorithm

More information