EE201l Homework #8. Datapath Design

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1 EE20l Homework #8 Datapath Design Instructor: G. Puvvada. Datapath and control design: You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a complete data path. Notice that you can bring either P or Q on bus # (B_ONE) or bus #2 (B_TWO). SMALL_REG is only tied to B_ONE where as BIG_REG is only tied to B_TWO.. 4-state state machine.. Complete the state diagram below by writing state transition conditions. /RESET PQL Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG. I Initial CPQ Compare P with Q on B_ONE on B_TWO QPL Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG...2 Complete the one-hot implementation of the above 4-state state machine on page 3. Before you produce the outputs, answer the following questions...2. Can we say that whenever we put P or Q on one of the two buses, we may put the other on the other bus? YES / NO..2.2 Can we say that, in the initial state, we may drive the buses even though it is not necessary? YES / NO..2.3 Can we say that we either load both SMALL_REG and BIG_REG or load none? YES / NO..3 Complete the waveform on page 4 4/4/06 EE20L Homework #8 / 7

2 Read this page. You do not need to do anything on this page 4/4/06 EE20L Homework #8 2 / 7

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4 Properties 50n 200n SYS_CLK wire /RESET wire wire QI wire QCPQ wire QPQL wire QQPL wire /P2B wire /Q2B wire /P2B2 wire /Q2B2 wire FGS wire /SMALL_LOAD wire /BIG_LOAD wire P wire[3:0] Q wire[3:0] SMALL wire[3:0] BIG wire[3:0] 0.0m 200n 400n 600n 800n u.2u.4u.6u.8u 2u 2.2u 2.4u XX XX 06 A 05 Page of, Row, Column A A A A 4/4/06 EE20L Homework #8 4 / 7

5 .2 3-state state machine.2. The state machine design in. above is a (Mealy / Moore) as the outputs generated are not influenced by the inputs. The outputs are completely determined by the current state. Let us now reduce the states by combining CPQ and PQL into CPQL compare and load. The load operation is conditional in the CPQL state as can be seen below. This 3-state state machine is a (Mealy / Moore). Complete the state diagram below. /RESET I Initial CPQL Compare P (on B_ONE) with Q (on B_TWO). If appropriate Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG. QPL Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG..2.2 Complete the one-hot implementation of the 3-state state machine on page Complete the waveform on page 7. 4/4/06 EE20L Homework #8 5 / 7

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7 Properties 50n 50n SYS_CLK wire /RESET wire wire QI wire QCPQL wire QQPL wire /P2B wire /Q2B wire /P2B2 wire /Q2B2 wire FGS wire /SMALL_LOAD wire /BIG_LOAD wire P wire[3:0] Q wire[3:0] SMALL wire[3:0] BIG wire[3:0] 0.0m 50n 300n 450n 600n 750n 900n.05u.2u.35u.5u.65u.8u.95u 2.u 2.25u 2.4u XX 04 AA XX Page of, Row, Column AA AA AA AA 4/4/06 EE20L Homework #8 7 / 7

8 2. Problem to solve: Add the smaller of P and Q to the smaller of X and Y and deposit the sum in the 4-bit register S. Though P, Q, X, and Y are all 3-bit unsigned numbers, we are using standard 4-bit TTL components in this design. The sum is a 4-bit sum. You do NOT need to refer to a TTL book. S <== smaller {P, Q} + smaller {X, Y} 2. The DPU: The DPU (Data Path Unit on the next page) is nearly complete. Please analyze the same and answer the following questions. 2.. Describe the function of the TTL chip 74LS244 briefly. Use terms such as two-state buffer, tristate buffer, inverting, non-inverting, active-low, active-high, quad / 4-bit wide, etc Comparator connections and labels: Write VCC or GND in the boxes. Decide what you want to connect to the input pins A3 and B3 and show the same on page Adder connections: Decide what you want to connect to the input pins A4, B4 and C0 and to the output pin S4 and show the same on page. Note: A 4-bit sum is produced by adding two 3-bit items Register connections and labels: Write VCC or GND or S_LOAD or /S_LOAD or CLK in the two boxes. Decide what you want to connect to the input pin 4D and show the same on page Among P, Q, X and Y and can be led to any of the two buses whereas can only go on to BUS # and can only go on to Bus # Describe the relation to be satisfied among the six control signals, /P2B, /P2B2, /Q2B, /Q2B2, /X2B, and /Y2B2 so that there will not be any bus-contention. Describe the relation in words as well as in boolean equation form. 4/4/06 EE20L Homework #8 8 / 7

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10 2..7 Which of the following operations are feasible (to perform in one clock) using this data path? Circle the ones that are feasible and cross-out others. Compare P and Q Compare P and X Compare X and Y Compare Q and Y S <-- P + Q S <-- P + X S <-- P + Y S <-- Q + Q S <-- X + X S <-- Y 2.2 State diagram for the CU (Control Unit) to perform S <-- smaller {P, Q} + smaller {X, Y} Complete all missing transition conditions in the following state diagram. To arrive at the state transition conditions, consider whether it is appropriate to use actual signals such as FLS (or FLS) which are available in the datapath or whether it is appropriate to use fictitious signals (not available in the datapath) such as P>Q, X>Y, etc. Notice the numbering of the states to facilitate possible implementation of the state machine using the microprogrammed control unit method. Is it ok if Mr. Bruin makes a mistake and swaps the numbers 2 and 5 for the states QXY and QXY2? OK / Not OK ~Reset 0 QI Initial 2 QXY Compare X, Y On BUS # QPQ Compare P, Q On BUS #2 On BUS # 5 Qxy2 Compare X, Y On BUS # QSPX S <- P + X QSPY S <- P + Y QSQX S <- Q + X QSQY S <- Q + Y 4/4/06 EE20L Homework #8 0 / 7

11 2.2. If P = Q and X = Y, which of the following sums gets deposited in S as per your state diagram? Circle the right one(s). P + X P + Y Q + X Q + Y 2.3 Assuming that a ONE-HOT method is used for implementing this state machine, complete the output function table below and produce the 7 outputs using standard gates (AND, OR, NAND, NOR, INVERTER) Output Function Table Output Control Current State QI /P2B /P2B2 /Q2B /Q2B2 /X2B /Y2B2 /S_LOAD /P2B /P2B2 /Q2B QPQ /Q2B2 QXY QXY2 /X2B QSPX QSPY /Y2B2 QSQX QSQY /S_LOAD 2.4 Assuming that a microprogrammed CU method is used for implementing this state machine, arrive at the following design parameters: Number of locations in the microprogram memory: Number of address pins on the microprogram memory: Size of the microprogram Counter: Size of the branch address field: Number of distinct branch conditions: Size of the condition select mux: Size of the condition select filed: Size of the control signal (output control signal) field: Total size of the micro-instruction: (putting together the condition select filed, the branch address field, and the control signal field) Size of the microprogram memory needed: 4/4/06 EE20L Homework #8 / 7

12 3. Design of a DPU (data path unit): This DPU needs to have a two 4-bit registers, A and B, and a 4-bit adder. The CU (control unit) sends to the DPU four signals as follows. Signal CLEAR AS/BS AD/BD Purpose To clear the registers A and B asynchronously Select A as the source or B as the source Select A as the destination or B as the destination Do the operation (add constant C to the selected source) and deposit the result into the selected destination) (of course, do it at the clock edge) Complete the function table below Operation SYS_CLK CLEAR AS/BS AD/BD Clear A, B X 0 X X X No Change to A or B X 0 X X A = A + C SYS_CLK CLEAR CONTROL UNIT AS/BS AD/BD NC A B A[4:] B[4:] C4 ADDER C0 GND S[4:] C 4 CU DPU The constant C comes from another unit. Here we are interested in only completing the DPU. 4/4/06 EE20L Homework #8 2 / 7

13 For storage elements: Use two 74LS73A registers for A and B. Processing element(s): Use a 74LS83A 4-bit binary adder for processing (adding in this case). Routing elements: Do you need any multiplexers or demultiplexers? Can you wisely make use of the tristate outputs of the two 74LS73A registers so as to avoid another mux chip? Think of bussing (forming a tristate bus of) the outputs of the two registers A and B and leading the bus to the input of the adders. 7 A 74LS83A Make an effort to use the right symbols for the gates to make the schematic readable. Some of the gating arrangements are given below. You may not need to use all of them! AD / BD AD / BD AD / BD AD / BD AS / BS AS / BS AD / BD 4/4/06 EE20L Homework #8 3 / 7

14 4. Datapath, State Diagram, and Control Unit (one-hot) design Serial vote counting: Inspect 8 votes (V0-V7) serially (one after another) through a mux. and find whether it is a DRAW (DRAW = TIE = equal number of YES and NO votes, i.e. four each). Here, we do not need any other inference such as Majority Vote, etc. Partially complete state diagram is given later. Names of the states are: I = INITIAL C = COUNTING DDT = DONE DRAW TRUE DDNT= DONE DRAW NOT TRUE The datapath unit consists of mainly an 8-to- mux 74LS5 to select one vote at a time, three 74LS63A counters called S-Counter (to produce select lines for the 8-to- mux), Y-Counter (to keep track of the YES votes), and N-Counter (to keep track of the NO votes). 4. Complete the DPU (Data Path Unit) after completing the state diagram in the next part of this question x63 CLK CLR LD ENP ENT A QA B QB C QC D QD RCO S-COUNTER LAST_OVER LAST V0 V V2 V3 V4 V5 V6 V x5 EN A B C D0 D Y D2 Y D3 D4 D5 D6 D7 8-TO- MUX 5 6 V x63 CLK CLR LD ENP ENT A QA B QB C QC D QD RCO FOUR_Y FIVE_Y x63 CLK CLR LD ENP ENT A QA B QB C QC D QD RCO FOUR_N FIVE_N Y-COUNTER N-COUNTER DPU 4.2 4/4/06 EE20L Homework #8 4 / 7

15 4.2. Complete the State diagram by finding the three conditions C, C2, and C3. Write the conditions in the form of boolean expression below. Note: You should transit from COUNTING state to DONE DRAW NOT TRUE state as soon as possible (for example, if you find too many YES votes or too many NO votes). Hint: First figure out C3 and then express C and C2 in terms of C3. C = C2 = C3 = Hint for C3: Is it (FOUR_Y * V + FOUR_N * V)or is it (FIVE_Y + FIVE_N )? ACK DDT ~Reset 0 C =? C2 =? ACK I C C3 =? Do NOT write C, C2, and C3 here as they may be long expressions. ACK ACK DDNT STATE DIAGRAM For the three conditions C, C2, C3 you figured out, check whether they satisfy the two properties, namely "ALL INCLUSIVITY and MUTUAL EXCLUSIVITY. You can refer to pages 56/587 i n the 3rd edition of Wakerly (478/553 in the 2nd edition). Verify ALL INCLUSIVITY Verify MUTUAL EXCLUSIVITY 4.3 Design the control Unit using four D-FFs in a One-Hot method. Separately produce C, C2, and 4/4/06 EE20L Homework #8 5 / 7

16 C3 and use these (C, C2, and C3) in the NSL (next state logic). Your design should include OFL (output function logic) to generate all necessary outputs to control the elements of the datapath unit. Also produce an output called DONE and an output called DRAW. Q DDT D SET Q CLR Q D SET Q Q I D SET Q Q C CLR Q CLR Q Q DDNT D SET Q CLR Q QC V QI QDDT QDDNT EN_S_CTR EN_Y_CTR EN_N_CTR /CLR_S_CTR /CLR_Y_CTR /CLR_N_CTR DONE DRAW C3 C2 C OFL Logic to produce C, C2, C3 4/4/06 EE20L Homework #8 6 / 7

17 4.4 Draw waveforms for a particular set of votes, namely V0 V V2 V3 V4 V5 V6 V7 = No Yes No No Yes No No Yes. Do you spend eight clocks or less-than-eight clocks in the COUNTING state? (all eight / less-than-eight).. Since there are more NO votes, hopefully, you have concluded that it is NOT a draw. Did you increment the S_COUNTER and N_COUNTER at the clock edge which led your state machine to go into the DDNT state. (Yes, No) for the S_COUNTER; (Yes, No) for the N_COUNTER CLOCK RESET STATE I C ACK S_COUNT Y_COUNT N_COUNT V V 0 V V 2 Q I Q C Q DDT Q DONT EN_S_CTR EN_Y_CTR EN_N_CTR DONE DRAW 4/4/06 EE20L Homework #8 7 / 7

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final