# From Sequential Circuits to Real Computers

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 1 / 36 From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2017

2 2 / 36 Introduction What we have done so far is implementing simple automata No (complex) data is manipulated (e.g., integers) because this will require to many states... But digital circuits (and of course full-fledged computers) deal with data We need a methodology that will gather: combinatorial functions, automata, registers, to build functions such as counters, dividers, speedometers... and general computers. Control-Data Separation

3 A Sequential Circuit within the Control-Data Separation Scheme 3 / 36

4 4 / 36 Datapath Offers computational ressources needed for the operations to be implemented Typically includes an ALU (Arithmetic and Logical Unit) and registers connected by buses and multiplexers Exchanges data (in/out) with the outside of the circuit Performs all operations on data But typically doesn t know which operation to perform and when to perform it Clock drives registers (synchronous circuits)

5 A typical (simplistic) Datapath 5 / 36

6 6 / 36 Control Knows which operations to perform and when Doesn t deal with data directly (doesn t no how to do the operations) Typically implemented as a Finite State Machine, i.e., an automaton (see lectures 4 and 5) Input alphabet: Orders (from the outside of the circuit) and Reports (from the datapath) Output alphabet: Acknowledgements (to the outside of the circuit) and Commands (to the datapath) Clock drives automaton state changes (synchronous circuits)

7 Control Control is designed as a classical FSM (remember lectures 4 and 5) 7 / 36

8 Control (cont d) Then control is implemented as a classical FSM (remember lectures 4 and 5) I = Orders Reports O = Acknowledgements Commands Q = set of states T = Q (Orders Reports) Q (transition function) F = Q (Acknowledgements Commands) (output function) 8 / 36

9 Control (cont d) 9 / 36

10 10 / 36 Control (cont d) Control is just about implemeting a Moore machine (no more, no less!!). Biggest difficulty is to not forget any control signal: Between Control and outside world (Orders, Acknowledgments) Between Control and Datapath (Commands, Reports) VERY IMPORTANT Commands will control datapath registers through their enable pin Commands control datapath routing through mutiplexers Control never has access to the data. It only receives Reports computed by the datapath. Reports are used to choose automaton transitions.

11 Conception Methodology 1. Start with: The algorithm describing the expected behavior The general scheme of a sequential circuit 2. Using knowledge about circuit s environment and expected functionalities, identify Orders and Acknowledgements. 3. Build the Datapath: Identify registers and computational resources (ALU) Connect them such that all computations can be performed (including reports computation) 4. Design Datapath/Control interface (Commands and Reports signals). Interface will connect: Outputs of the control automaton to enable signals of datapath registers, or to datapath multiplexers (Commands) Outputs of computations as reports sent to control (used as inputs of the automaton) 5. Transform the (unformal) algorithm into a Moore machine: Identify states and transitions Associate Acknowledges and Commands to each state. 11 / 36

12 12 / 36 Running Example: a telemeter Let s build a telemeter with digital display. Usage: User presses a button Telemeter emits an ultrasound impulse Measures the echo travel time Travel time is translated into a distance Distance is displayed on screen

13 13 / 36 Running Example: definition of input/output signals Inputs are: GO: triggers a new measure. Telemeter waits for GO to be 1 to start a new measure. Receive: 0 when the ultrasound sensor hears nothing, 1 when sensor hears an echo. Outputs are: Emit: Needs to be set to 1 during one clock cycle to emit an ultrasound impulse. Distance: unsigned, 16 bits precision (but maximum value can be different from 65,535) due to time distance convertion); 0 until Receive. OK: 0 whenever the telemeter counts, 1 as soon as Distance is valid. Stays 1 until we ask for a new measure ERR: 1 if echo never comes back, 0 otherwise.

14 Running Example: Circuit interface 14 / 36

15 Running Example: Global architecture 15 / 36

16 Running Example: counting distance 16 / 36

17 17 / 36 Running Example: bonus, dealing with time and overflow Blackboard!

18 Running Example: moore machine 18 / 36

19 Demo Time! 19 / 36

20 20 / 36 Final sprint: building a real (but simple) computer Great, we have all the necessary elements to build a Real computer The only thing we still need is a way to organize things in order to execute any program rather than always the same computation... But executing a program can be simply viewed as a computation (i.e. always the same!) read an instruction execute it go to the next one We will use Control-Data separation to build a sequential circuit which function will be to compute the execution of a sequence of instructions von Neumann architecture

21 Von Neumann s computer 21 / 36

22 Von Neumann and the EDVAC 22 / 36

23 The considerations which follow deal with the structure of a very high speed automatic digital computing system, and in particular with its logical control. An automatic computing system is a (usually highly composite) device, which can carry out instructions to perform calculations of a considerable order of complexity e.g. to solve a non-linear partial differential equation in 2 or 3 independent variables numerically. bold faces added by me :) 23 / 36

24 24 / 36 At any rate a central arithmetical part of the device will probably have to exist, and this constitutes the first specific part: CA. Datapath and ALU

25 25 / 36 If the device is to be elastic, that is as nearly as possible all purpose, then a distinction must be made between the specific instructions given for and defining a particular problem, and the general control organs which see to it that these instructions no matter what they are are carried out. By the central control we mean this latter function only, and the organs which perform it form the second specific part: CC. Control

26 26 / 36 At any rate the total memory constitutes the third specific part of the device: M. Memory

27 27 / 36 The three specific parts CA, CC (together C) and M correspond to the associative neurons in the human nervous system. The First Draft Report on the EDVAC by John von Neumann, Jun 30th, 1945

28 Von Neumann s Architecture 28 / 36

29 What is a program? 29 / 36

30 30 / 36 Programs. s e c t i o n. i n i t 9 main : mov. b #2, &0x32 loop : mov. b #2, &0x31 mov #20000, R4 wait1 : dec R4 j n z wait1 mov. b #0, &0x31 mov #20000, R4 wait2 : dec R4 j n z wait2 jmp loop

31 31 / 36 Executing programs - The Von Neumann Cycle - 1 Programs are executed instruction by instruction: loop { Fetch Current I n s t r u c t i o n Decode I n s t r u c t i o n Execute ( use datapath ) Write Results ( to r e g i s t e r s / memory ) Go to Next I n s t r u c t i o n } The Von Neumann cycle is Implemented in Hardware in the CPU Control component.

32 Executing programs - The Von Neuman Cycle / 36

33 Von Neuman Architecture more details 33 / 36

34 Von Neumann Architecture a real computer 34 / 36

35 Demo Time! 35 / 36

36 36 / 36 That all folks! In this course, we followed a bottom-up approach: How information is coded binary How we can deal with this information to compute other information from it boolean algebra How to build combinatorial circuits implementing simple mathematical functions How to deal with time and describe sequential behaviors How to build a small programmable machine The Computer Architecture course will further this discussion towards real computers.

### Lecture 10: Synchronous Sequential Circuits Design

Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple

### Design at the Register Transfer Level

Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic

### ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code George Mason University Required reading P. Chu, FPGA Prototyping by VHDL Examples

### Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

### NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1

NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 Multi-processor vs. Multi-computer architecture µp vs. DSP RISC vs. DSP RISC Reduced-instruction-set Register-to-register operation Higher throughput by using

### Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation

### State and Finite State Machines

State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register

### Design of Sequential Circuits

Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

### CpE358/CS381. Switching Theory and Logical Design. Summer

Switching Theory and Logical Design - Class Schedule Monday Tuesday Wednesday Thursday Friday May 7 8 9 - Class 2 - Class 2 2 24 - Class 3 25 26 - Class 4 27 28 Quiz Commencement 3 June 2 - Class 5 3 -

### Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits

Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines

### Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming

### Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY

1 McGill University Faculty of Engineering DIGITAL SYSTEM DESIGN ECSE-323 FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Signature: Associate

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,

### Computer Science. 19. Combinational Circuits. Computer Science COMPUTER SCIENCE. Section 6.1.

COMPUTER SCIENCE S E D G E W I C K / W A Y N E PA R T I I : A L G O R I T H M S, M A C H I N E S, a n d T H E O R Y Computer Science Computer Science An Interdisciplinary Approach Section 6.1 ROBERT SEDGEWICK

### Combinational vs. Sequential. Summary of Combinational Logic. Combinational device/circuit: any circuit built using the basic gates Expressed as

Summary of Combinational Logic : Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: www.seas.gwu.edu/~bhagiweb/cs3/ Combinational device/circuit: any circuit

### ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation

### ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

### CS/COE0447: Computer Organization

Logic design? CS/COE0447: Computer Organization and Assembly Language Logic Design Review Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values:

### Finite State Machine. By : Ali Mustafa

Finite State Machine By : Ali Mustafa So Far We have covered the memory elements issue and we are ready to implement the sequential circuits. We need to know how to Deal(analyze) with a sequential circuit?

### Introduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison

Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by

### Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University

### ECE290 Fall 2012 Lecture 22. Dr. Zbigniew Kalbarczyk

ECE290 Fall 2012 Lecture 22 Dr. Zbigniew Kalbarczyk Today LC-3 Micro-sequencer (the control store) LC-3 Micro-programmed control memory LC-3 Micro-instruction format LC -3 Micro-sequencer (the circuitry)

### Outline. policies for the first part. with some potential answers... MCS 260 Lecture 10.0 Introduction to Computer Science Jan Verschelde, 9 July 2014

Outline 1 midterm exam on Friday 11 July 2014 policies for the first part 2 questions with some potential answers... MCS 260 Lecture 10.0 Introduction to Computer Science Jan Verschelde, 9 July 2014 Intro

### Numbers and Arithmetic

Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu

### CE1911 LECTURE FSM DESIGN PRACTICE DAY 1

REVIEW MATERIAL 1. Combinational circuits do not have memory. They calculate instantaneous outputs based only on current inputs. They implement basic arithmetic and logic functions. 2. Sequential circuits

### Homework #4. CSE 140 Summer Session Instructor: Mohsen Imani. Only a subset of questions will be graded

Homework #4 CSE 140 Summer Session 2 2017 Instructor: Mohsen Imani Only a subset of questions will be graded 1) For the circuit shown below, do the following: a. Write a logic equation for the output P

### Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

### Adders, subtractors comparators, multipliers and other ALU elements

CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

### Sequential logic and design

Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by

### State & Finite State Machines

State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Stateful Components Until now is combinatorial logic Output

### Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

### Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.

A Full Adder The half-adder is extremely useful until you want to add more that one binary digit quantities. The slow way to develop a two binary digit adders would be to make a truth table and reduce

### DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:

### From Greek philosophers to circuits: An introduction to boolean logic. COS 116, Spring 2011 Sanjeev Arora

From Greek philosophers to circuits: An introduction to boolean logic. COS 116, Spring 2011 Sanjeev Arora Midterm One week from today in class Mar 10 Covers lectures, labs, homework, readings to date You

### Finite State Machine (FSM)

Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State

### Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information

### Computer Science. Questions for discussion Part II. Computer Science COMPUTER SCIENCE. Section 4.2.

COMPUTER SCIENCE S E D G E W I C K / W A Y N E PA R T I I : A L G O R I T H M S, T H E O R Y, A N D M A C H I N E S Computer Science Computer Science An Interdisciplinary Approach Section 4.2 ROBERT SEDGEWICK

### Digital Design 2010 DE2 1

1 Underviser: D. M. Akbar Hussain Litteratur: Digital Design Principles & Practices 4 th Edition by yj John F. Wakerly 2 DE2 1 3 4 DE2 2 To enable students to apply analysis, synthesis and implementation

### EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?

### Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors

Introduction to Digital Logic Missouri S&T University CPE 2210 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu

### EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS150 - Lec18-counters Page 1 Counters Special sequential circuits (FSMs) that sequence though a set outputs.

Introduction: Computer Science is a cluster of related scientific and engineering disciplines concerned with the study and application of computations. These disciplines range from the pure and basic scientific

### COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the

### EECS150 - Digital Design Lecture 16 Counters. Announcements

EECS150 - Digital Design Lecture 16 Counters October 20, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150 Fall 2011

### LECTURE 28. Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State

Today LECTURE 28 Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State Time permitting, RC circuits (where we intentionally put in resistance

### CPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner

CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections

### L07-L09 recap: Fundamental lesson(s)!

L7-L9 recap: Fundamental lesson(s)! Over the next 3 lectures (using the IPS ISA as context) I ll explain:! How functions are treated and processed in assembly! How system calls are enabled in assembly!

### 6. Finite State Machines

6. Finite State Machines 6.4x Computation Structures Part Digital Circuits Copyright 25 MIT EECS 6.4 Computation Structures L6: Finite State Machines, Slide # Our New Machine Clock State Registers k Current

### Binary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 P Q

Digital Arithmetic In Chapter 2, we have discussed number systems such as binary, hexadecimal, decimal, and octal. We have also discussed sign representation techniques, for example, sign-bit representation

### Digital Electronics Sequential Logic

/5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest

### Register Transfer Level (RTL) Design based on Vahid chap. 5

CSE4: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design based on Vahid chap. 5 Tajana Simunic Rosing RTL Design Method RTL Design example: Laser-Based Distance Measurer

### Random Number Generator Digital Design - Demo

Understanding Digital Design The Digital Electronics 2014 Digital Design - Demo This presentation will Review the oard Game Counter block diagram. Review the circuit design of the sequential logic section

### COVER SHEET: Problem#: Points

EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

### Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec09 Counters Outline.

Review: Designing with FSM EECS 150 - Components and Design Techniques for Digital Systems Lec09 Counters 9-28-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

### UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables

UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1

### Combinational Logic. By : Ali Mustafa

Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

### Logical design of digital systems

21062017 lectures Summer Semester 2017 Table of content 1 Combinational circuit design 2 Elementary combinatorial circuits for data transmission 3 Memory structures 4 Programmable logic devices 5 Algorithmic

### Preparation of Examination Questions and Exercises: Solutions

Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),

### A Second Datapath Example YH16

A Second Datapath Example YH16 Lecture 09 Prof. Yih Huang S365 1 A 16-Bit Architecture: YH16 A word is 16 bit wide 32 general purpose registers, 16 bits each Like MIPS, 0 is hardwired zero. 16 bit P 16

### Contents. Chapter 3 Combinational Circuits Page 1 of 36

Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of

### Computer organization

Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java High-level language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data

### Sequential Logic. Road Traveled So Far

Comp 2 Spring 25 2/ Lecture page Sequential Logic These must be the slings and arrows of outrageous fortune ) Synchronous as an implementation of Sequential 2) Synchronous Timing Analysis 3) Single synchronous

### Boolean Algebra, Gates and Circuits

Boolean Algebra, Gates and Circuits Kasper Brink November 21, 2017 (Images taken from Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.) Outline Last week: Von

### Register Transfer Level

Register Transfer Level CSE3201 RTL A digital system is represented at the register transfer level by these three components 1. The set of registers in the system 2. The operation that are performed on

### UC Berkeley College of Engineering, EECS Department CS61C: Representations of Combinational Logic Circuits

2 Wawrzynek, Garcia 2004 c UCB UC Berkeley College of Engineering, EECS Department CS61C: Representations of Combinational Logic Circuits 1 Introduction Original document by J. Wawrzynek (2003-11-15) Revised

### Learning Objectives:

Learning Objectives: t the end of this topic you will be able to; draw a block diagram showing how -type flip-flops can be connected to form a synchronous counter to meet a given specification; explain

### - Why aren t there more quantum algorithms? - Quantum Programming Languages. By : Amanda Cieslak and Ahmana Tarin

- Why aren t there more quantum algorithms? - Quantum Programming Languages By : Amanda Cieslak and Ahmana Tarin Why aren t there more quantum algorithms? there are only a few problems for which quantum

### Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle

Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory

### CHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5.

CHPTER 9 2008 Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F 7 9-3.* = S + S = S + S S S S0 C in C 0 dder

### Shannon-Fano-Elias coding

Shannon-Fano-Elias coding Suppose that we have a memoryless source X t taking values in the alphabet {1, 2,..., L}. Suppose that the probabilities for all symbols are strictly positive: p(i) > 0, i. The

### FPGA Resource Utilization Estimates for NI PXI-7854R. LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008

FPGA Resource Utilization Estimates for NI PXI-7854R LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your

### Theory of Finite Automata

According to the Oxford English Dictionary, an automaton (plural is automata ) is a machine whose responses to all possible inputs are specified in advance. For this course, the term finite automaton can

### CSCI 2150 Intro to State Machines

CSCI 2150 Intro to State Machines Topic: Now that we've created flip-flops, let's make stuff with them Reading: igital Fundamentals sections 6.11 and 9.4 (ignore the JK flip-flop stuff) States Up until

### Equivalence Checking of Sequential Circuits

Equivalence Checking of Sequential Circuits Sanjit Seshia EECS UC Berkeley With thanks to K. Keutzer, R. Rutenbar 1 Today s Lecture What we know: How to check two combinational circuits for equivalence

### A Quantum von Neumann Architecture for Large-Scale Quantum Computing

A Quantum von Neumann Architecture for Large-Scale Quantum Computing Matthias F. Brandl Institut für Experimentalphysik, Universität Innsbruck, Technikerstraße 25, A-6020 Innsbruck, Austria November 15,

### Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

### Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common

### 1.10 (a) Function of AND, OR, NOT, NAND & NOR Logic gates and their input/output.

Chapter 1.10 Logic Gates 1.10 (a) Function of AND, OR, NOT, NAND & NOR Logic gates and their input/output. Microprocessors are the central hardware that runs computers. There are several components that

### Lecture A: Logic Design and Gates

Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:

### FYSE420 DIGITAL ELECTRONICS

FYSE42 IGITAL ELECTRONICS Lecture 4 [] [2] [3] IGITAL LOGIC CIRCUIT ANALYSIS & ESIGN Nelson, Nagle, Irvin, Carrol ISBN -3-463894-8 IGITAL ESIGN Morris Mano Fourth edition ISBN -3-98924-3 igital esign Principles

### Simplify the following Boolean expressions and minimize the number of literals:

Boolean Algebra Task 1 Simplify the following Boolean expressions and minimize the number of literals: 1.1 1.2 1.3 Task 2 Convert the following expressions into sum of products and product of sums: 2.1

### Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!

### Digital Electronics Final Examination. Part A

Digital Electronics Final Examination Part A Spring 2009 Student Name: Date: Class Period: Total Points: /50 Converted Score: /40 Page 1 of 13 Directions: This is a CLOSED BOOK/CLOSED NOTES exam. Select

### CMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN

### Implementing an analog speedometer in STISIM Drive using Parallax BSTAMP microcontroller

Implementing an analog speedometer in STISIM Drive using Parallax BSTAMP microcontroller J-F Tessier 1,2 M. Kaszap 1 M. Lavallière 1,2 M. Tremblay 1,2 N. Teasdale 1,2 1 Université Laval, Faculté de médecine,

### EECS 579: Logic and Fault Simulation. Simulation

EECS 579: Logic and Fault Simulation Simulation: Use of computer software models to verify correctness Fault Simulation: Use of simulation for fault analysis and ATPG Circuit description Input data for

### Digital Electronics Circuits 2017

JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design

### Synchronous Logic. These must be the slings and arrows of outrageous fortune. Comp 411 Fall /20/15. L15 Synchronous Logic 1

Synchronous Logic 1) Sequential Logic 2) Synchronous Design 3) Synchronous Timing Analysis 4) Single Clock Design 5) Finite State Machines 6) Turing Machines 7) What it means to be Computable These must

### 7 Multipliers and their VHDL representation

7 Multipliers and their VHDL representation 7.1 Introduction to arithmetic algorithms If a is a number, then a vector of digits A n 1:0 = [a n 1... a 1 a 0 ] is a numeral representing the number in the

### Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).

hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove

### CHAPTER1: Digital Logic Circuits Combination Circuits

CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.

### Chapter 6 Flip-Flops, and Registers

Flip-Flops, and Registers Chapter Overview Up to this point we have focused on combinational circuits, which do not have memory. We now focus on circuits that have state or memory. These are called sequential

### CSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing

CSE140L: Components and Design Techniques for Digital Systems Lab FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz 1 FSM design example Moore vs. Mealy Remove one 1 from

### SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL

### Using a Microcontroller to Study the Time Distribution of Counts From a Radioactive Source

Using a Microcontroller to Study the Time Distribution of Counts From a Radioactive Source Will Johns,Eduardo Luiggi (revised by Julia Velkovska, Michael Clemens September 11, 2007 Abstract In this lab

### COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

### ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference)

ECE 3401 Lecture 23 Pipeline Design Control State Register Combinational Control Logic New/ Modified Control Word ISA: Instruction Specifications (for reference) P C P C + 1 I N F I R M [ P C ] E X 0 PC