Unit 1 - Digital System Design

Transcription

1 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 IGITAL SYSTM MOL FSM (CONTROL) + ATAPATH CIRCUIT Uit - igital Sytem eig ATAPATH CIRCUIT Iput FINIT STAT MACHIN CONTROL CIRCUIT Output XAMPLS CAR LOT COUNTR photo receptor If A = No light received (car obtructig L A) If B = No light received (car obtructig L B) B A If car eter the lot, the folloig equece (A B) mut be folloed: If car leave the lot, the folloig equece (A B) mut be folloed: A car might tay i a tate for may cycle ice the car peed i very large compared to that of the frequecy. IGITAL SYSTM (FSM + atapath circuit) Uually, he (aychroou clear) ad are ot dra, they are implied. A B FINIT STAT MACHIN ud ud CONTROL CIRCUIT -bit couter ATAPATH CIRCUIT Itructor: aiel Llamocca

2 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 Fiite State Machie (FSM): A B/ ud = / / / / / / / / /,,/ S S3 S S5 / / / / / / / / / / / / / / / S6 / / S7 S8 / / / Algorithmic State Machie (ASM) chart: S = AB= o ye AB S3 S6 AB AB S S7 AB AB S S8, ud AB AB 2 Itructor: aiel Llamocca

3 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 BOUNCING CIRCUIT Mechaical boucig lat approximately 2 m. The, e have to make ure that the iput igal i table ( ) for at leat 2 m before e aert _db. The, to deaert _db, e have to make that the i table ( ) for at leat 2 m. IGITAL SYSTM (FSM + atapath circuit) Couter to N-: = = +. clr: Sychroou clear. The ay it i deiged, if clr = ad =, the =. If T i the period of the igal, the N = 2m. T For example, for MH iput, T =. The N = 2m = m 2 m FSM clr _db _db <2 m <2 m clr couter to N- comparator =N-? Algorithmic State Machie: S = S, clr ait for the firt '' clr for _db=, mut be for at leat 2 m S3 _db S _db, ait for the firt '' clr for _db=, mut be for at leat 2 m 3 Itructor: aiel Llamocca

4 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 BIT-COUNTING CIRCUIT (COUNTING S) Thi circuit cout the umber of bit i regiter A hoe value i. xample: A = C =. The equetial algorithm (peudo-code) i available. I thi cae, e ca follo thi procedure to deig a digital ytem: Sketch the block diagram: We eed tart ad doe igal to idicate he the proce tart ad fiihe. We alo iclude iput (ata for the Regiter A) ad output data (Cout). Sketch the high-level cotrol mechaim (tate machie) for the Bit-coutig circuit. Here, you ca iclude combiatioal block a ell a commo ychroou block (regiter, hift regiter, couter). With the block diagram ad high-level cotrol mechaim, e ca tart icludig the compoet ad their igal i the datapath. Baed o the high-level tate machie, e ca deig the actual tate machie that iclude pecific igal cotrollig the compoet. High-level FSM S Reet Sequetial Algorithm C C hile A if a = the C C + ed if right hift A ed hile Load A A Bit-coutig circuit C doe S3 doe y e A=? o Shif t right A a C C+ IGITAL SYSTM (FSM + atapath circuit) The digital ytem i depicted belo: FSM + atapath. xample: For = 8: if A =, the C =. m-bit couter: If = clr =, the cout i iitialied to ero. If =, clr =, the cout i icreaed by. Parallel acce hift regiter: If = : _l = Load, _l = Shift. A S = C, clrc LA A di _l Parallel Acce _l = Load _l = Shift A Shift-Right C clrc clr C A, LA couter: m bit a = 2 A FINIT STAT MACHIN doe S3 doe a C Itructor: aiel Llamocca

5 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 Timig diagram ( = 8, = ): A A 36 B tate S S S3 S S3 C clrc C doe A LA INTGR BAS-2 LOGARITHM Thi circuit compute 2 A. ata (uiged iteger) i cotaied i regiter A ( bit) The equetial algorithm (peudo-code) i available. We follo the procedure pecified i the previou example. Note that itead of performig a right hift to A to get A 2, e ill get A 2 by created a hifted verio of A. xample (=): A = a 3 a 2 a a A 2 = a 3 a 2 a. Alo akig A = i the ame a akig hether A 2 =. High-level FSM S Reet Sequetial Algorithm L L hile A A A - A/2 L L + ed hile Load A A Bit-coutig circuit L doe S3 doe y e A= o update A L L + 5 Itructor: aiel Llamocca

6 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 IGITAL SYSTM (FSM + atapath circuit) The digital ytem i depicted belo. For bit, 2 A [, ]. Thu, the reult eed 2 ( ) bit. m-bit couter: If = clr =, the cout i iitialied to ero. If =, clr =, the cout i icreaed by. Regiter: If = : clr = Clear, clr = Load. A A clr A A a -a -2 a = 2 L clrl clr L = S L, clrl A, A uiged ubtractor - A FSM Couter to doe S3 doe A L A A A 35 B tate S S S3 S L clrl L doe A A 6 Itructor: aiel Llamocca

7 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 LAING ZRO TCTOR (ITRATIV) A equece of N bit i fed to the circuit erially. The circuit geerate the umber of that exit before the firt. xample (N=5): If the umber i: Output: 2 If the umber i: Output: 5 If the umber i: Output: X tart LAING- TCTOR R doe = 2 N tart x doe R IGITAL SYSTM (FSM + atapath circuit) Iput: X (erial data, MSB firt), tart. Output: (leadig detected), doe (N bit proceed), ad R (umber of before the firt ). The proce beig ith the aertio of tart. Whe the firt i detected, the = (for cycle) ad R i froe. Whe all the bit of the equece have bee proceed, doe=. We ca re-tart the proce after thi. Note that if X i jut, i ever. Couter R ad : modulo-(n+): cout from to N. x tart doe FSM b eb db clr R clrr clr db eb clr couter to N b R clrr clr couter to N R S = R, clrr, clr eb, db tart b x eb db R o =N- y e S3 doe,, clr R, clrr tart 7 Itructor: aiel Llamocca

8 _G O_G _ext _R O_R _R O_R _R2 O_R2 _R3 O_R3 op _A LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 SIMPL PROCSSOR IGITAL SYSTM (FSM + atapath circuit) Thi ytem i a baic Cetral Proceig Uit (CPU). For completee, a memory ould eed to be icluded. Here, the Cotrol Circuit could be implemeted a a State Machie. Hoever, i order to implify the State Machie deig, the Cotrol Circuit i partitioed ito a datapath circuit ad a FSM. ata_i ata BUS R R R2 R3 A B ALU G fu 7 CONTROL CIRCUIT doe OPRATION very time = '', e grab the itructio from fu ad execute it. Itructio = f 2 f f Ry Ry Rx Rx. Thi i called machie laguage itructio or Aembly itructio: f 2 f f : Opcode (operatio code). Thi i the portio that pecifie the operatio to be performed. Rx: Regiter here the reult of the operatio i tored (e alo read data from Rx). Rx ca be R, R2, R3, R. Ry: Regiter here e oly read data from. Ry ca be R, R2, R3, R. f = f 2f f Operatio Fuctio Load Rx, ata Rx ata Move Rx, Ry Rx Ry Add Rx, Ry Rx Rx + Ry Sub Rx, Ry Rx Rx - Ry Not Rx Rx NOT (Rx) Ad Rx, Ry Rx Rx AN Ry Or Rx, Ry Rx Rx OR Ry Xor Rx, Ry Rx Rx XOR Ry 8 Itructor: aiel Llamocca

9 _fu _A _G op O_G _ext LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 Cotrol Circuit: Thi i made out of ome combiatioal uit, a regiter, ad a FSM: x: very time e at to eable regiter Rx, the FSM oly aert x (itead of cotrollig _R, _R, _R2, _R3 directly). The decoder take care of geeratig the eable igal for the correpodig regiter Rx. o, o: very time e at to read from regiter Ry (or Rx), the FSM oly aert o (itead of cotrollig O_R, O_R, O_R2, O_R3 directly) ad o (hich igal hether to read from Rx or Ry). The decoder take care of geeratig the eable igal for the correpodig regiter Rx or Ry. fu _fu 7 7 fuq Rx Rx x COR ith eable 2 3 _R _R _R2 _R3 Ry Rx o o COR ith eable 2 3 O_R O_R O_R2 O_R3 fuq = f 2 f f Ry Ry Rx Rx x o o f 3 FSM doe Arithmetic-Logic Uit (ALU): op Operatio Fuctio Uit y <= A y <= A + y <= A - Trafer A Icremet A ecremet A y <= B Trafer B y <= B + Icremet B Arithmetic y <= B y <= A + B y <= A B ecremet B Add A ad B Subtract B from 'A' y <= ot A y <= ot B y <= A AN B y <= A OR B y <= A NAN B y <= A NOR B y <= A XOR B y <= A XNOR B Complemet A Complemet B AN OR NAN NOR XOR XNOR Logic 9 Itructor: aiel Llamocca

10 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 Algorithmic State Machie (ASM): very brach of the FSM implemet a Aembly itructio. S = _fu _ext, x doe f o, x doe o, o _A o, o _A o, o _A o, o _A o, o _A o, o _A S3a Sa S5a S6a S7a S8a o, _G op o, _G op _G op o, _G op o, _G op o, _G op S3b Sb S5b S6b S7b S8b O_G, x doe O_G, x doe O_G, x doe O_G, x doe O_G, x doe O_G, x doe Itructor: aiel Llamocca

11 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 BINARY TO BC CONVRSION OUBL ABBL ALGORITM Give a N-bit uiged biary umber, e left hift every oe of the N bit ito a e regiter (that hold the BC digit). We thu have N iteratio. If after hiftig, ay of the BC digit (oe or more) i greater tha, e icremet it by 3. The exceptio i o the lat iteratio, here after hiftig, e do ot icremet ay ibble. For N bit, e eed N 3 BC digit. So the BC regiter i N 3 bit ide. Number of bit Biary rage Number of BC digit [-5] 2 7 [-27] 3 [-23] [-6383] 5 N [, 2 N ] N 3 Why doe it ork? Thik of BC hiftig: e at to hift the bit of a BC umber, but preervig the BC repreetatio. If a umber loer or equal tha i hifted, e get at mot 8, till repreetable i BC. If a umber greater tha i hifted, the miimum umber e get i =2, hich i ot i BC. If e add 3 to the umber ad the hift, e ill get the proper BC reult ith 2 BC digit. xample: 5=2. If e hift, e get 2. 2 ould be i BC. To get thi, e ca add 3 to 2, reultig i 2. After hiftig, e get. The ame happe for umber 6, 7, 8, ad 9. xample: 255 = 2 (N=8). We eed N 3 = 3 BC digit. Note that there are N = 8 iteratio. The table ho the tate after a operatio ha bee applied. I the example, oly a ibble get icremeted at a time. BC umber Biary umber Procedure jut applied Procedure to apply Iitialiatio Left hift Left hift Left hift Left hift Left hift Left hift. >. The e add 3 to Add 3 to Left hift Left hift. >. The e add 3 to Add 3 to Left hift Left hift Left hift Left hift. >. The e add 3 to Add 3 to Left hift Left hift >. The e add 3 to Add 3 to Left hift Left hift. Noe. We do ot add 3 i the lat iteratio xample: 72 = (N=8). We eed N 3 = 3 BC digit. Note that there are N = 8 iteratio. The table ho the tate after a operatio ha bee applied. I geeral, more tha a ibble ca be icremeted at a time. BC umber Biary umber Procedure jut applied Procedure to apply Iitialiatio Left hift Left hift Left hift Left hift Left hift Left hift >. The e add 3 to Add 3 to Left hift Left hift Left hift Left hift Left hift Left hift Left hift Left hift >, >. The e add 3 to ad Add 3 to ad Left hift Left hift Note. We do ot add 3 i the lat iteratio Itructor: aiel Llamocca

12 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 IGITAL SYSTM (FSM + atapath circuit) tart doe i_bi clrb B FSM K _A L_A _LB clr_b _C clr_c _CB clr_cb B _C _CB CB F _C clr_c clr couter to N- _C _CB clr_cb clr couter to K- _CB CB _LB COR 2... K- LB() LB() LB(2) LB(K-) N pb(k) o o LFT SHIFT clr pb(k-) pb(2) LFT SHIFT clr pb() LFT SHIFT clr pb() _L _L _L RGISTR B(K-) RGISTR B() RGISTR B() LB(K-) LB() LB() o B(K-) B() B() o LFT SHIFT RGISTR _L A LA F... K- + B o_bcd(k-)... o_bcd() CB o_bcd() Algorithmic State Machie (ASM) Chart: S = clrb, B ".." _C, clr_c, _CB, clr_cb tart LA, A B "..", A S3 F > & _C= o ye _LB B(CB) _CB _CB _CB, clr_cb _C _C _C, clr_c S doe tart 2 Itructor: aiel Llamocca

13 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 XTRA TOPICS LINAR FBACK SHIFT RGISTRS (LFSRS) LFSR have a imple ad fairly regular tructure. Typical compoet: -type flip flop, ad logic gate. Advatage: very little hardare ad high peed operatio. Iput to flip flop are liear fuctio of the previou tate. epite the imple appearace, LFSR are baed o rather complex mathematical theory ad have iteretig applicatio i the area of digital ytem tetig, cryptography, ad fault-tolerat computig. Typical applicatio: rror correctio/detectio, peudo radom umber geerator, fat couter. A geeric -bit LFSR i depicted belo: 3 2 x clk LINAR FUNCTION APPLICATION: CYCLIC RUNANCY CHCK (CRC) Thi error-detectio code i ued i digital commuicatio (e.g.: theret, CAN), ad torage device (e.g.: RAM). Commuicatio ytem k-bit meage: M = k k 2. CRC code: R = r r 2 r r. Stream et: k k 2 r r 2 r r CRC Geerator Tramitted bit CRC Checker error Aociated polyomial: M(x) = k x k k 2x k 2 x x. Order: k R(x) = r x r 2 x 2 r x r x. Order: The CRC code i calculated a a remaider: R(x) = re aider ( x M(x) G(x) G(x) = g x g x g x g x. Thi i the geeratig polyomial of order. G = g g g g Here, he dealig ith polyomial operatio, e ue modulo-2 polyomial arithmetic (Galoi field of to elemet: GF(2)). The coefficiet of the polyomial ca oly be or. The multiplicatio operatio ca be implemeted a a imple AN gate, ad the additio (or ubtractio) operatio ca be implemeted by a XOR gate: a ± b = a b, a {,}. xample: x x = x x =. CRC geerator: It compute R(x). It iput i x M(x) k k 2. CRC checker: O the receiver ide, both the meage ad CRC code might be corrupted by the chael: M (x) ad R (x). So, e mut check if re aider ( x M (x) ) = R (x). If o, e ay that the ytem paed the CRC check. G(x) Note that thi implie: x M (x) = (x)g(x) R (x) x M (x) R (x) = x M (x) R (x) = (x)g(x). I modulo-2 arithmetic, R (x) = R (x). It follo that x M (x) R (x) hould be diviible by G(x). The CRC checker tet if re aider ( x M (x)+r (x) ) =. If the remaider i ero, e ay that it paed the CRC check. It G(x) i till poible for R (x) ad M (x) to make the remaider equal to ero but thi i far le likely. The iput to the CRC checker i x M (x) R (x) k k 2 r r 2 r. 3 Itructor: aiel Llamocca

14 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 xample: CRC- ( = ): M =, G = M(x) = x 7 x 6 x 5 x 2 x x M(x) = x (x 7 x 6 x 5 x 2 x) = x x x 9 x 6 x 5 G(x) = x x 3 R(x) = x 2 x CRC circuit The folloig LFSR implemet -bit CRC. Compoet: flip flop, AN, XOR gate. Note that g = i ot ued. Thi i becaue it i commo i CRC to have g =. Thi i already coidered i the deig of the circuit. xample ith M =, G = : Whe itegrated ito the CRC geerator, the iput i give by: x M(x). The output reult i R =. Whe itegrated ito the CRC checker, the iput i give by: x M (x) R (x). The reult of the circuit i re aider =, idicatig a valid tramiio. R R R 2 R 3 x clk G G G 2 G 3 clk x R clk x R Applicatio: The circuit above ca be implemeted for ay umber of bit. For example: CRC-32 (theret), CRC-5 (CAN), ad CRC- (trivial eve parity geerator ith G(x) = x ). Thi i a erial implemetatio, i.e., each bit i fed to the circuit at a time. Other implemetatio proce ome bit i parallel (for CRC-, the parity geerator i C27: Note Uit procee all the bit at oce). The deig of the geeratig polyomial G(x) i outide the cope of thi cla. Thee circuit are better implemeted i hardare for high peed ad lo reource utiliatio. x clk G R Itructor: aiel Llamocca

15 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 MOULO-N COUNTR SIGN A modulo-n couter could be deiged by the State Machie method, but thi ca be very cumberome if N i a large umber. For example, if N=, e eed tate. The figure ho a couter modulo-2 that ue a regiter, ad adder, a comparator, ad logic gate. : cout. : output igal aerted oly he the maximum cout (99) i reached. Thi ca be eaily decribed i VHL uig the tructural decriptio. You ca alo ue the behavioral decriptio, here the cout i icreaed by every cycle ad i aerted he the cout reache N a 7 b 7 + a 6 b 6 a 5 b 5 clr clr 8 B a b a 3 b 3 A=B clr: ychroou clear If =clr=, the = 8 A = 99? A=B a 2 b 2 a b a b MMORY COING Phyical implemetatio of memory i ot homogeeou: ifferet portio of memory are ued for differet purpoe: RAM, ROM, I/O device. A proceor ca uually addre a memory pace that i much larger tha the memory pace covered by a idividual memory chip. ve if all the memory a of oe type, e till have to implemet it uig multiple IC. For a give valid addre, oe ad oly oe memory-mapped compoet mut be acceed. Addre ecodig: Proce of geeratig chip elect (CS, C) igal from the addre bu for each device i the ytem. The Addre bu lie (N+M bit) i plit ito to ectio: The N mot igificat bit are ued to geerate the CS igal for the differet device. The M leat igificat bit are paed to the device a addree. XAMPL A 2-bit addre lie i a proceor hadle up to 2 2 = MB of addree, each addre cotaiig oe-byte of iformatio. We at to coect four 256KB memory chip to the proceor. The 2 MSB of the addre lie are ued to geerate the CS igal. The 8 LSB are paed to the device a addree. The pik-haded circuit: i) addree the memory chip, ad ii) eable oly oe memory chip (via C: chip eable) he the addre fall i the correpodig rage. xample: if addre = x5ffff, oly memory chip 2 i eabled (C=). If addre = x23, oly memory chip i eabled KB 256KB 256KB 256KB FFFF 7FFFF 8 BFFFF C FFFFF Memory pace Memory device addre KB 256 KB 256 KB 2 3 C C C addre(7..) addre(8) addre(9) y y y 2 y KB C 5 Itructor: aiel Llamocca

16 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare eig Witer 29 FLIP FLOPS: PRACTICAL ASPCTS Reducig rate of chage of a ychroou circuit: Here, e ue FSM a a example of a ychroou circuit. But e ca apply thi techique to ay ychroou circuit. We uually ould like to reduce the rate at hich FSM traitio occur. A traightforard optio i to reduce the frequecy of the iput. But thi i a very complicated problem he a high preciio i required. Alteratively, e ca reduce the rate at hich FSM traitio occur by icludig a eable igal i our FSM: thi mea icludig a eable to every flip flop i the FSM. For ay FSM traitio to occur, the eable igal ha to be. The e aert the eable igal oly he e eed it. The effect i the ame a reducig the frequecy of the iput. The figure belo depict a couter modulo-n (from to N-) coected to a comparator that geerate a pule (output igal ) of oe period every time e hit the cout N-. The umber of bit the couter i give by = 2 N. The effect i the ame a reducig the frequecy of the FSM to f N, here f i the frequecy of the. Iput FSM Output comparator couter to N- =N-? xample: Timig diagram of a modulo- couter. Notice that i oly aerted he the cout reache. Thi igal cotrol the eable of a FSM, o that the FSM traitio oly occur every cycle, thereby havig the ame effect a reducig the frequecy by. clk We ca apply the ame techique ot oly to FSM, but alo to ay equetial circuit. Thi ay, e ca reduce the rate of ay equetial circuit (e.g. aother couter) by icludig a eable igal of every flip flop i the circuit. Flip flop timig parameter: Propagatio elay. Setup Time: Iterval of time before the edge here the data mut be held table. Hold Time: Iterval of time after the here the data mut be held table. If etup time or hold time are violated, the output may become upredictable, or eve ore it might eter ito metatability. clk clk retricted regio 6 Itructor: aiel Llamocca