SIMPLIFIED ADDRESSING SCHEME FOR MIXED RADIX FFT ALGORITHMS

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1 IEEE Iteratioal Coferece o Acoutic, Speech ad Sigal Proceig (ICASSP) SIMPLIFIED ADDRESSING SCHEME FOR MIXED RADIX FFT ALGORITHMS Cuimei Ma, Yizhuag Xie, He Che, Yi Deg, We Ya Beijig Ititute of Techology, Beijig,, Chia; Virgiia Polytechic Ititute ad State Uiverity, Arligto, VA USA ABSTRACT A algorithm for the i-place fat Fourier traform (FFT), which i broadly ued i mot embedded igal proceig field, ca be explicitly expreed by a iterative equatio baed o the Cooley-Tukey algorithm. The expreio ca be applied to either decimatio-i-time (DIT) or decimatio-i-frequecy (DIF) FFT with ordered iput. For may ewly emergig low power portable computig applicatio, uch a mobile high defiitio video compreig, mobile fat ad accurate atellite locatio, etc., the exitig method perform either reource coumig or o-flexible. I thi paper, we propoe a ew addreig cheme for efficietly implemetig mixed radix FFT. I thi cheme, we elaborately deig a accumulator that ca geerate acceig addree for the operad, a well a the twiddle factor. The aalytical reult how that the propoed cheme reduce the algorithm complexity meawhile help the deiger to efficietly chooe a arbitrary FFT to deig the i-place architecture. Idex Term Fat Fourier Traform,, addre geeratio, i place, arithmetical complexity.. INTRODUCTION Fat Fourier traform (FFT) algorithm play a key role i improvig the feaibility of dicrete Fourier traform (DFT), which i broadly ued i mot digital proceig applicatio. For practical FFT ue, there are radix-, radix- ad plit-radix [] FFT. Meawhile, the reearch o radix- k [] FFT ha reulted i the itatiatio of uch method a radix- [], radix- [], ad eve radix- FFT []. Although the derivatio ad programmig are ituitive for radix- k FFT, the drawback i that the umber of poit ha to be retricted to power of two or four, which retrict it applicatio i reource-limited portable computig ceario. Recetly, a optimal choice for the FFT ize i i demad ad may o-power-of-two FFT, uch a! ad! - poit FFT, have bee tudied [,]. However, thoe method are all i radix-q k FFT [], where q i prime, uch a,, ad, et al. Becaue the FFT ca be ued i geeral ceario, it become practical ad ueful. Some FFT algorithm are tudied, uch a radix-/ [,] ad radix-/! FFT. They are baed o radix- FFT. However, if the paddig-zero method i ued to atify the radix-! FFT, it will coume a larger amout of memory tha the FFT. Sice the memory cot i a igificat part of the FFT proceor, miimizig the eceary ize i a effective way for the area reductio. Therefore, arbitrary FFT problem are dicued i [, ]. Two method, the pipelied ad memory-baed architecture [, ], have bee propoed for differet applicatio i variou FFT proceor. Although much higher throughput tha memory baed deig, the pipelie architecture have a larger area cot. Therefore, the i-place trategy [] i take ad oly oe memory with N complex word i eeded. However, the i-place trategy ha a complex deig circuit, which ha to geerate addree for both operad ad twiddle factor. Demuth [] propoed a eted loop idex geeratio algorithm to idex iput ad output of FFT ad aother way to idex twiddle factor expoet. Thi method eed may parameter to get the addre, which i difficult to implemet uig hardware. Hiao [] gave the idex mappig method for the geeralized algorithm with ome complex modulo operatio. A bit-level repreetatio of the acceig rule wa metioed by Soroki [], which i ued i differet proceig for a radix-/ FFT. I thi paper, we will exted it to a arbitrary FFT. A iterative expreio that i applied to radix-r! /r! iplace architecture i derived. The N data are tored i RAM ad the N twiddle factor are i ROM. A accumulator i et to make the acceig addre map eaily to the hardware circuit ad there i o modulo operatio. The illutrative example i baed o radix-/ decimatio-itime (DIT) i-place -poit FFT. By thi method, a appropriate FFT ize i choe to miimize the memory ize ad a implified addre cotrol i deiged.. REVIEW OF MIXED-RADIX ALGORITHM ----//$. IEEE

2 The N-poit DFT of a N-poit equece { x( )}, Table. Variable digit with cycle i each. N X ( k ) = x( )WNk, k N () = where WNk = exp( j π k / N ), ad j =. Suppoe that the FFT ize atifie N = r r, where r ad r are two radice, ad are the correpodig repreetatio Variable digit m < ( k k k m m m ) km iteger power, ad a parameter i = +. We aume that the algorithm ue radix- r followed algorithm, the time ad frequecy idice, i.e. ad k, are aalyzed. The expreio for both ad k with digit i term of r, r, ad are obtaied a follow. m ( m ) m ( < m ) if i, ki [, r ], ele i [, r ]. For brevity, aume that ci = ri whe i =,,,, c + i = r ri whe i =,,. c 'i = ri whe i =,,, c ' + i = r ri whe i =,,,. Therefore, Eq.() i rewritte a = c + c + + c + c, k = c ' k + c ' k + + c ' k + c ' k. () where if i, i [, r ], ele i [, r ] ; () k Table. Differet radix of Ci i each. by radix- r. Accordig to Cooley-Tukey = r r + + r r + + r + r + + r +, k = r r k + + r r k + + r k + r k + + r k + k, ( kkk k ) Ci (i =,, ) Radix C, C,C r C, C +, C +,, C r C,, C, C r C, C +, C +,, C, C r Furthermore, W k ( c m m ) i the correpodig twiddle factor. We tore the twiddle factor W i = exp( j π i / N ) i a lookup table equetially, where i rage from to N-. We ca get them from the lookup table by aalyzig the expoet part, i.e. k (c m m ). The followig ectio will preet the addreig cheme by the iteratio repreetatio of ad k i the mth.. THE PROPOSED ADDRESSING SCHEME For otatioal coveiece, Eq. () ca be writte a = ( ), () k = ( k k k kk ). Whe Eq. () i ubtituted ito Eq. (), we decompoe N-poit DFT ito iteratio ad the mth ( m ) iteratio i a follow. xm ( k k km m m ) r ' () = xm ( k k km m m )WNk ( c m m ) m = where r ' (r, r ). Whe m atifie m, r ' = r, otherwie r ' = r. From Eq. (), xm (k k km m m ) deote oe of r ' operad for radix- r ' butterfly i the mth ad xm (k k km m ) repreet the butterfly output. Becaue the i-place algorithm i ued, we ca aalyze Addr(m) = (k k km m m ) to explore the.. geeratio for operad The r ' coecutive addree for the r ' operad of radixr ' butterfly ca be obtaied i r ' clock cycle. For every, we hould fid which digit i variable from to r ' ad the other digit are cotat i ( k k km m m ). The variable digit for every i lited i Table. Aume a accumulator, which i repreeted by = (C C C CCC ) for mappig the data addree. Ci i the ith digit, C i the mot igificat digit ad C the leat igificat digit. Oly C keep varyig with cycle, imilar to km at the mth, jut a how i Table. Becaue each digit i Addr i either r or r, Ci i addre geeratio i order to get the operad. i either r or r. Therefore, there lit the value of Ci i Table. The relatiohip betwee Addr ad

3 C C C m C m C m C m (m) C C C C m C m C m C m k k Addr(m) km m m m m Table. The expreio of β i each. C C C Fig.. e geeratig for N-poit FFT uig i the mth. (CCC ) (CCC ) () () (CCC ) ( C C C ) () (C CC ) (C CC ) () () W Acceig addre, ((-)-digit) () m( m < ) (C m +C m + C ) (CCC C ) ( r r k ++r k +r k ++r k+k )(c m m ) () m c m m c'i ki c'i ki c c' k i=m m m m m i= =W!#"## $W!# #"## $W!#"## $ c m m Part Part Part There are three part of the expreio. We decribe them eparately ad aalyze which part i ued to get the addre of twiddle factor. c m m c 'i ki i =m Part : We obtai that W = i each. c m m c 'i ki Part : W deote r ' -poit DFT matrix, for example, [; ] i a -poit DFT matrix. Differet Fig.. Acce for operad of -poit radix- FFT. i the mth i illutrated i Fig.. Fig. how that the addre of the mth of FFT i obtaied from. The third row i the addre, which i repreeted uig time ad frequecy idice, i.e. ad k. Fig. illutrate the addreig cheme for -poit FFT, i.e. r =, r =, =, =. I the firt colum, repreet the umber of the memory depth from to ad alo mea the time equece. Whe the of the FFT i the firt, () = (CCC ) = (). Accordig to Fig., C i hifted to the left of the C, ad we obtai that Addr() = (CCC ) = (). Addr () i variable a how i colum ad the addree of the operad i memory are achieved by the coverio the mixed-radix umber to the decimal repreetatio ad the value of are lited i colum. For example, the firt radix- butterfly computatio, the addree of the two operad are ad eparately. The output are tored i the ame addree. For the ext two, () = (CCC ) = () ad () = (CCC ) = (). Addr() = (CCC ) = () by hiftig C to the left of C ad Addr () = (). Therefore, we ca get the right addree of the operad accordig to Fig.. ue differet r ' -poit DFT matrix. Whe m, it i a r -poit DFT matrix; otherwie, it i a r -poit DFT matrix. The firt two part have othig to do with the addre of twiddle factor, o we ca get the addre from part. We a parameter m β ' = c 'i ki whe i = m =,,,, ad β ' = whe m =. β ' ca be expreed by (C m+c m+ C C ) mixed radix accordig to whe m =,,,. Let β = c m β '. The Table lit the expreio β i each. Suppoe revere = (CCC C C C ) ad it mea the digit revere of the. Table how that the expreio of β i related to revere. β ca be repreeted i VHDL whe m =,,, a follow : β (m) <= [ revere ((m ) dowto )& zero(( ) dowto (m ))], where zero deote a zero vector. Becaue m =,,, r ' i part, the addree of the r ' twiddle factor for a butterfly uit i m ca be acquired by m multiplicatio with β ( m), a Eq.(). The acceig addree of twiddle factor are obtaied... geeratio for twiddle factor Subtitute the expreio k i Eq.() ito W k ( c m m ), ad the followig expreio i obtaied. uppoe m = ;, β ( m ), m = ; Addrtwi ( m) = ( r ' ) β ( m), = r '. m () Fig. how the acceig addre for twiddle factor of -poit FFT. The colum i the ame meaig a that i i the firt colum i Fig.. For each butterfly

4 β () Addr twi β Addr ( CC C ) twi C ( CC β ) ( ) ( C ) ( ) ( C C ) Addrtwi Fig.. Accee for twiddle factor of radix-/ FFT. computatio, the left addree of it i Fig. are for the iput operad the oe i Fig. are for the twiddle factor. Therefore, we eaily get the addree of the operad ad the twiddle factor uig oe accumulator for the mixed radix FFT. The atifie the coditio lited i Table. Figure give the relatio betwee the addree of operad ad the accumulator. Table lit the relatio betwee the addree of the twiddle factor ad the ame accumulator.. COMPARISONS The architecture of the i-place algorithm are geerally coitet. The key compario part i the addre geeratio. Meawhile, becaue the twiddle factor i ot coidered i [], oly a compario o the addre geeratio for the operad betwee the method i [] ad the propoed cheme i give. The itermediate value i [] are hard to be implemeted i hardware, o there i o compario with the cheme i []. For implicity, a -poit radix-/ FFT i take a the illutrative example. Fig. (a) how the propoed cheme ad Fig. (b) how the cheme i []. By compario, the ovel cheme ha two characteritic: (I) It keep the architecture of FFT coitet for every. Thu, we oly deig oe architecture to get the acceig addre by the. For the method i [], the architecture of addre geeratio for each i differet. We have to deig three differet architecture to obtai the correpodig acceig addree for the each. If the FFT poit become larger, more reource are eeded for the addre geeratio. (II)It require o complex modulo operatio. The larger the FFT ize i, the more modulo operatio are eeded i []. Table lit the umber of mathematical operatio for the -poit FFT. Therefore, the propoed cheme implifie the complexity of geeratig addree.. CONCLUSIONS AND DISCUSSION = () C C C C C C C C C C = () C C C (a) = () C C C C = () C C = () C C C (b) mod = () C C C C C mod Fig.. geeratio for -poit radix-/ FFT by (a) the propoed method, ad (b) the method i []. Table. Mathematical operatio compario of Hiao deig ad our Scheme Our Scheme Hiao Deig [] -iput additio -iput multiplicatio Modulo operatio A iterative approach ca be applied to aalyze the addre geeratio for mixed-radix i-place FFT with ordered iput. The acceig addree for the operad ad the twiddle factor ca be achieved from oe accumulator. It i eay to implemet thi accumulator i hardware circuit. With repect to the tradeoff, FFT cot more tha oe butterfly uit compared with fixed radix FFT. However, a uified architecture, jut like that decribed i [], ca be achieved to compute arbitrary two butterflie. Therefore, the icreaed reource of the butterfly uit with uified architecture have mall impact o the overall reource.. REFERENCES [] T.Z. Sug, H.C. Hi, et al, Low-power ad high-peed CORDIC-baed plit-radix FFT proceor for OFDM ytem, Digit. Sigal Prog, vol., o., pp. -,. [] M. Garrido, J. Grajal, M.A. Sachez, et al, Pipelied radix- k feedforward FFT architecture, IEEE Tra. Very Large Scale Itegr. (VLSI) Syt, vol., o., pp. -,. [] J. Li, F. Liu, T. Log, et al, Reearch o Pipelie RSDF FFT, IET It. Radar Cof,, Guili, Chia, Apr. -, pp.-.

5 [] K. Maharata, E. Gra, ad U. Jagdhold, A -Poit Fourier Traform Chip for High-Speed Wirele LAN Applicatio Uig OFDM, IEEE J. Solid-State Circuit, vol. o., pp.-,. [] H. Liu ad H. Lee, A high performace four parallel /- poit radix- FFT/IFFT proceor for MIMO-OFDM ytem, IEEE Aia Pacific Cof. Circuit Syt. (APCCSA), Macao, Chia, Nov. -Dec., pp.-. [] E. Duboi ad A. Veetaopoulo, A ew algorithm for the radix- FFT, IEEE Tra. Acoutic, Speech, Sigal Prog, vol., o., pp. -,. [] D. Takahah, A ew radix- FFT algorithm uitable for multiply-add itructio, IEEE It. Cof. Acoutic, Speech, Sigal Prog., Itabul, Turkey, Ju. -, vol., pp.-. [] S.S. Deg, Y. Su, L.S. Zhag, et al, Deig of High-Speed FFT Proceor for Legth N=q m, J. Comput. Re. Dev., vol., o., pp. -,. [] A.T. Jacobo, D.N. Truog, ad B.M. Baa, The deig of a recofigurable cotiuou-flow mixed-radix FFT Proceor, IEEE It. Sym. Circuit Syt., Taipei, Chia, May -, pp.-. [] H. Xiao, A Pa, Y. Che, et al, Low-cot recofigurable VLSI architecture for fat Fourier traform, IEEE Tra. Coum Electro, vol., o., pp.-,. [] G.L.Demuth, Algorithm for defiig FFT flow graph, IEEE tra. acoutic, peech, igal prog, vol., o., pp. -,. [] C.F.Hiao, Y.Che, C.Y.Lee, A geeralized mixed-radix algorithm for memory-baed FFT proceor, IEEE tra. circuit yt.-ii, vol., o., pp.-,. [] C. Yu, M.H.Ye, P.A. Hiug, et al, A Low-Power -poit Pipelie FFT/IFFT Proceor for OFDM Applicatio, IEEE Tra. Coum. Electro., vol., o., pp.-,. [] C.L. Wey, S.Y. Li, ad W.C. Tag, Efficiet Memorybaed FFT Proceor for OFDM Applicatio, IEEE It. Cof. Electro/Iformatio Techol,, Chicago, US, May -, pp. -. [] B.G. Jo ad M.H. Suwoo, New Cotiuou-Flow Mixed- Radix (CFMR) FFT Proceor Uig Novel I-Place Strategy, IEEE Tra. Circuit Syt.-I, vol., o., pp. -,. [] H. Soroki, J. Takala, Coflict-free parallel acce cheme for mixed-radix FFT upportig I/O permutatio, IEEE Cof. Acotic, Speech, Sigal Prog (ICASSP), Prague, C.Z., May -, pp. -. [] F. Qurehi, M. Garrido ad O. Gutafo, Uified architecture for,,,, ad -poit DFT baed o Wigrad Fourier traform algorithm, Electro. Lett., vol., o., pp. -,.