ECEN620: Network Theory Broadband Circuit Design Fall 2014

Transcription

1 ECE60: etwork Theory Broadbad Circuit Deig Fall 04 Lecture 3: PLL Aalyi Sam Palermo Aalog & Mixed-Sigal Ceter Texa A&M Uiverity

2 Ageda & Readig PLL Overview & Applicatio PLL Liear Model Phae & Frequecy Relatiohip PLL Trafer Fuctio PLL Order & Type Readig Chapter, 3, 5, & of Phaelock Techique, F. Garder, Joh Wiley & So, 005.

3 Referece M. Perrott, High Speed Commuicatio Circuit ad Sytem Coure, MIT Ope Coureware Chapter of Phae-Locked Loop, 3 rd Ed., R. Bet, McGraw-Hill, 997. Chapter, 3, 5, & of Phaelock Techique, F. Garder, Joh Wiley & So,

4 PLL Block Diagram [Perrott] A phae-locked loop (PLL) i a egative feedback ytem where a ocillator-geerated igal i phae AD frequecy locked to a referece igal 4

5 PLL Applicatio PLL applicatio Frequecy ythei Multiplyig a 00MHz referece clock to 0GHz Skew cacellatio Phae aligig a iteral clock to a I/O clock Clock recovery Extract from icomig data tream the clock frequecy ad optimum phae of high-peed amplig clock Modulatio/De-modulatio Wirele ytem Spread-pectrum clockig 5

6 Forward Clock I/O Circuit TX PLL TX Clock Ditributio Replica TX Clock Driver Chael Forward Clock Amplifier RX Clock Ditributio De-Skew Circuit DLL/PI Ijectio-Locked Ocillator 6

7 Embedded Clock I/O Circuit TX PLL TX Clock Ditributio CDR Per-chael PLL-baed Dual-loop w/ Global PLL & Local DLL/PI Local Phae-Rotator PLL Global PLL require RX clock ditributio to idividual chael 7

8 Liear PLL Model Phae i geerally the key variable of iteret Liear mall-igal aalyi i ueful for udertad PLL dyamic if PLL i locked (or ear lock) Iput phae deviatio amplitude i mall eough to maitai operatio i lock rage 8

9 Phae Detector φ ref φ e φ fb Detect phae differece betwee feedback clock ad referece clock The loop filter will filter the phae detector output, thu to characterize phae detector gai, extract average output voltage (or curret for charge-pump PLL) 9

10 Loop Filter VDD I Chargig Cotrol Voltage I VSS Dichargig C R C F() Lowpa filter extract average of phae detector error pule 0

11 Voltage-Cotrolled Ocillator ω 0 0 VDD/ VDD Time-domai phae relatiohip ( t) ( t) dt v ( t) φ out ω out c dt ω ( t) ω ω ( t) v ( t) out 0 out ω 0 Laplace Domai Model c φ out (t)

12 Loop Divider φ out (t) φ fb (t) [Perrott] Time-domai model ω fb ω ( t) ( t) out φ fb out ( t) ω ( t) dt φ ( t) out

13 Phae & Frequecy Relatiohip Agular Frequecy i the firt derivative (rate of chage v time) of phae dφ dt ( t) ω ( t) Coider a iuoid u Phae Step u φ ( t) Φu( t) ( t) ( ω ( t) Φu( t) ) i φ t ( t) ω( ) o d ( t) with agular frequecy ω ( t) ad phaeφ ( t) u ( t) i( ω ( t) t φ ( t) ) [Bet] o chage i frequecy Φ 3

14 Phae & Frequecy Relatiohip Frequecy Step ω( t) u ( t) i( ω t ωt) i( ω t φ ( t) ) 0 where ω ω φ 0 ( t) ωt 0 A frequecy tep produce a ramp i phae [Bet] φ ( t) t ω 4

15 Phae & Frequecy Relatiohip Frequecy Ramp u ( t) ω0 ω t t ( t) i 0 d i 0t t ω ω ω ω i( ω0t φ( t) ) 0 ω [Bet] where φ ( t) ω t A frequecy ramp produce a quadratic chage i phae ω0 ω 0 ω t φ ω t ( t ) 5

16 Udertadig PLL Frequecy Repoe Liear mall-igal aalyi i ueful for udertad PLL dyamic if PLL i locked (or ear lock) Iput phae deviatio amplitude i mall eough to maitai operatio i lock rage Frequecy domai aalyi ca tell u how well the PLL track the iput phae a it chage at a certai frequecy PLL trafer fuctio i differet depedig o which poit i the loop the output i repodig to Iput phae repoe output repoe [Fichette] 6

17 Ope-Loop PLL Trafer Fuctio G ( ) Φ Φ ( ) ( ) out e F ( ) Ope-loop repoe geerally decreae with frequecy 7

18 Cloed-Loop PLL Trafer Fuctio Sytem Determiat l Forward Path Gai G Loop Gai F Forward Path Determiat ( ) ( ) G( ) G 0 ( ) G( ) 0 H ( ) Φ Φ out ref ( ) ( ) G G ( ) F( ) ( ) F ( ) Low-pa repoe whoe overall order i et by F() 8

19 PLL Error Trafer Fuctio l Sytem Determiat Forward Path Gai Loop Gai F Forward Path Determiat ( ) G( ) G 0 ( ) G( ) 0 E ( ) Φ Φ e ref ( ) ( ) G( ) F( ) Ideally, we wat thi to be zero Phae error geerally icreae with frequecy due to thi high-pa repoe 9

20 PLL Order ad Type The PLL order refer to the umber of pole i the cloed-loop trafer fuctio Thi i typically oe greater tha the umber of loop filter pole The PLL type refer to the umber of itegrator withi the loop A PLL i alway at leae Type due to the itegrator ote, the order ca ever be le tha the type 0

21 Firt-Order PLL F ( ) Simple firt-order lowpa trafer fuctio Cloed-loop badwidth i equal to the DC loop gai magitude Forward Path Gai : G DC Loop Gai Magitude : Trafer Fuctio : H Error Fuctio : E ( ) ( ) ( ) DC 3dB Cloed - Loop Badwidth : ω G lim 0 ( ) ω ω ω 3dB 3dB 3dB DC DC DC DC DC

22 Firt-Order PLL Trackig Repoe The PLL trackig behavior, or how the phae error repod to a iput phae chage, varie with the PLL type Phae Step Repoe [Bet] u φ ( t) Φu( t) ( t) ( ω ( t) Φu( t) ) i o chage i frequecy The fial value theorem ca be ued to fid the teady-tate phae error Φ lim 0 ( E( ) ) lim 0 0 Φ All PLL hould have o teady-tate phae error with a phae tep error ote, thi aume that the frequecy of operatio i the ame a the ceter frequecy (V ctrl 0). Workig at a frequecy other tha the ceter frequecy i coidered havig a frequecy offet (tep). DC

23 Firt-Order PLL Trackig Repoe Frequecy Offet (Step) u ω ( t) ( t) i( ω t ωt) i( ω t φ ( t) ) 0 where ω ω φ 0 ( t) ωt 0 [Bet] A frequecy tep produce a ramp i phae The fial value theorem ca be ued to fid the teadytate phae error ω lim ( E( ) ) 0 0 ω lim DC ω With a frequecy offet (tep), a firt-order PLL will lock with a teady-tate phae error that i iverely proportioal to the loop gai DC 3

24 Firt-Order PLL Iue The DC loop gai directly et the PLL badwidth o degree of freedom I order to have low phae error, a large loop gai i eceary, which implie a wide badwidth Thi may ot be deired i applicatio where we would like to filter iput referece clock phae oie Firt-order PLL offer o filterig of the phae detector output Without thi filterig, the may ot be well approximated by a imple factor Multiplier have a ecod-harmoic term Digital output quare pule that eed to be filtered 4

25 Secod-Order Type- PLL w/ Paive Lag-Lead Filter Paive Lag-Lead Loop Filter [Alle] F ( ) ( ) R C R C 5

26 ( ) ( ) R C R C F Secod-Order Type- PLL w/ Paive Lag-Lead Filter ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 0 Error Fuctio : : Dampig Factor Frequecy : atural Trafer Fuctio : lim DC Loop Gai Magitude : Forward Path Gai : DC DC DC DC DC E H G G ω ζω ω ω ζ ω ω ζω ω ω ζ ω 6

27 Secod-Order Type- PLL Trackig Repoe Phae Step Repoe ω Φ Φ lim ( ( )) lim E 0 0 ζω ω 0 Agai, phae error hould be zero with a phae tep Frequecy Offet (Step) ω lim ( E( ) ) ω ω lim ζω 0 0 ω ω DC A ecod-order type- PLL will till lock with a phae error if there i a frequecy offet! 7

28 Secod-Order Type- PLL Propertie While the ecod-order type- PLL will till lock with a phae error with a frequecy offet, it i much more ueful tha a firt-order PLL There are ufficiet deig parameter (degree of freedom) to idepedetly et ω, ζ, ad DC The loop filter coditio the phae detector output for proper cotrol Loop tability eed to be coidered for the ecod-order ytem 8

29 Secod-Order Type- PLL w/ Paive Serie-RC Lag-Lead Filter Paive Serie-RC Loop Filter F ( ) R RC ote, thi type of loop filter i typically ued with a chargepump drivig it. Thu, the filter trafer fuctio i equal to the impedace. 9

30 Secod-Order Type- PLL w/ Paive Serie-RC Lag-Lead Filter F ( ) R RC DC Loop Gai Magitude : Forward Path Gai : G ( ) DC (ideally) R RC Trafer Fuctio : H ( ) R RC R C ω ζω ζ ζω ω atural Frequecy: ω ω Dampig Factor : ζ RC Error Fuctio : E ζω ω ( ) C 30

31 Secod-Order Type- PLL Trackig Repoe Phae Step Repoe Φ Φ lim ( E( ) ) lim 0 0 ζω ω 0 Agai, phae error hould be zero with a phae tep Frequecy Offet (Step) ω ω lim 0 0 ζω ω ( E( ) ) lim 0 A ecod-order type- PLL will lock with o phae error with a frequecy offet! 3

32 Secod-Order Type- PLL Propertie A big advatage of the type- PLL i that it ha zero phae error eve with a frequecy offet Thi i why type- PLL are very popular A type- PLL require a zero i the loop filter for tability. ote, thi i ot required i a type- PLL Thi zero ca caue extra peakig i the frequecy repoe Importat to miimize thi i ome applicatio, uch a cacaded CDR ytem 3

33 ext Time PLL Sytem Aalyi PLL Stability oie Trafer Fuctio Traiet Repoe 33