We start by describing a one bit memory circuit built of a couple of two inputs NAND gates.

Transcription

1 Chapter 4: Sequetial Logic ( copyright by aiel Seider) Util ow we discussed circuits that are combiatioal. This meas that their outputs were fuctios of the iputs, ad oly the iputs, at all times. For each combiatio at the iputs of the circuit, we got a certai output. Wheever that iput combiatio is chaged, the output chages accordigly. There is aother kid of circuits i which the outputs do ot deped solely o the iputs but also o the previous values of the outputs. This kid of circuits icludes closed loops, sometimes called feedback coectios. These circuits have the ability of rememberig their state uder some coditios ad ca therefore be used to build memory devices. These circuits are called sequetial logic. I this chapter we discuss sequetial logic. We start by describig a oe bit memory circuit built of a couple of two iputs NAN gates. 4.) SR latch A Set-Reset latch (SR latch) is a bit memory device which is built of two NAN gates. The output of the upper NAN gate is coected to oe of the iputs of the lower NAN gate. The output of the lower NAN gate is coected to oe of the iputs of the upper NAN gate, thus, closig a loop. These coectios are the feedback coectios. We will immediately see that this circuit has two stable states. We mark the upper output by ad the lower by, sice as we ll soo see, i most of the cases is the NOT of. These two NAN gates with the feedback coectios cosist a latch. Latches are sometimes mistakely referred to as Flip-Flops i literature. The differece betwee Latches ad Flip-flops will be explaied later i this chapter. S R Figure 4. SR latch We deoted the two iputs of the latch as S ad R. Let us first aalyze the behavior of this latch whe we put a logical level of 0 i the two iputs S ad R. Let s assume that =. Therefore, the lower NAN gate has i both iputs ad we must have = 0. This 0 forces to stay. So, we coclude that the combiatio of = ad = 0 is a stable combiatio.

2 Chapter 4: Sequetial Logic 2 ( copyright by aiel Seider) Let us assume ow that = 0. Therefore, the lower NAN gate must output a. This meas that we have i both iputs of the upper NAN ad so we still force to stay 0. This meas that the combiatio of = 0 ad = is also a stable combiatio. Let us assume that we have a 0 i ad i. We immediately see that both of the NAN gates have 0 i their iputs. This meas that they both wat to chage their output to. Let us suppose that the upper gate is a little bit faster tha the lower gate. So, the becomes before the is chagig. We therefore reached oe of the two stable states metioed above, i.e., the latch remais i the state of = ad = 0. I case the lower gate is faster, the latch will reach the other stable state. We coclude that 0 i both, ad, is a ustable situatio. A similar behavior is see whe we start with i ad i. Both NAN gates have s i both their iputs. Both outputs wish to become 0. The faster gate wis this race ad so we will evetually fid the latch i oe of the stable states. We ow wat to use this latch as a bit memory device. The output will have the value remembered by this device. Whe we wat to set to be we eed to put i the S iput for a short time. The forces the to be sice after the iverter we have a 0 as a iput to the upper NAN gate, which forces i its output. We already kow that i causes 0 i the sice both iputs of the lower NAN gate are. Note that this sequece of evets took some time. The i the S iput propagated through the iverter ad the through the upper NAN gate ad the through the lower NAN gate. I case all those gates has the same propagatio delay t pd the after 3t pd we have 0 i the output of the latch. This meas that we ca ow remove the from the S iput, sice the is already 0 ad will keep the i the. (Oe might wait a extra t pd just to be sure that the 0 of the holds the i, but o more tha that). This process is described i Figure 4.2 below. S After iverter t pd Sim ilarl t pd t pd Figure 4.2 Settig the

3 Chapter 4: Sequetial Logic 3 ( copyright by aiel Seider) y, i order to reset the to be 0, we eed to put i the R iput for a short time. Sice the circuit is symmetric, the same process causes to become which, i tur, causes to become 0. Figure 4.3 describes the waveforms whe we set the latch twice ad the reset it ad set it agai: S R set set reset set Figure 4.3 Settig ad resettig the We call the situatio i which S = R = 0, the idifferet iput combiatio. I this situatio the iputs of the latch do ot force the value of the outputs. The outputs determie their ow state i such case, i.e., their state remais the same as it was before we reached the idifferet iput combiatio. Let us ow describe the truth table of the SR-latch: S R ?

4 Chapter 4: Sequetial Logic 4 ( copyright by aiel Seider) This table tells us what is the value of the after the + evet of settig or resettig it. The case of S=R= 0 is the idifferet situatio i which the latch stays i its previous state. Thus, + i this case is the same as. Whe S= 0 ad R= we reset the latch therefore causig to be 0. Whe S= ad R= 0 we set the latch therefore causig to be. What about havig both S ad R to be? Lookig at Figure 4. we see that i this case both outputs, ad are. We already discussed such a case ad decided that it is a ustable situatio. But this is oly ustable whe the two iputs are 0. I our case we claim that they are. So, why did we put the questio mark there? It is correct that both the outputs are whe both iputs are. However, we eed to remember how we used the latch. We issued pulses i the iputs. We should have used pulses as iputs to the truth-table: S R ? So what will the be after issuig such a pulse to the two iputs at the exact same time? Whe the pulse eds, we have = = but ow the two iputs are 0. Sice = = is a ustable state, we would get to oe of the two stable states of the latch. But, which oe? No oe kows. Therefore, we put the questio mark i the table. Therefore this combiatio of the iputs is called forbidde ad should be avoided. 4.2) Addig a gate to the SR latch Let us ow cosider the followig circuit: S R G Figure 4.4 A gated SR latch

5 Chapter 4: Sequetial Logic 5 ( copyright by aiel Seider) Its truth table is: G S R + 0 X X ? Whe G is 0, we are i the idifferet situatio, sice it is idetical to the case i which S=R= 0. Whe we issue a pulse i G, we eable the S ad R iputs to ifluece o the latch the way they did i the regular SR latch. We ca imagie ow a system i which we issue a pulse i G every so ad so secods. The umber we attached to i the truth-table, makes more sese ow. is the value of followig the -th pulse i G. S R G Figure 4.5 Settig ad resettig the

6 Chapter 4: Sequetial Logic 6 ( copyright by aiel Seider) Notice that here, the chace of havig ukow output still exists sice if S=R=, a pulse i G defiitely brigs us ito the doubtful temporary situatio of havig both output i ad, whe the pulse eds, two iputs i 0. Figure 4.5 describes the whe R ad S have the 4 possible combiatios. I each G pulse the output follows the truth-table. So we first set to sice we have S= ad R= 0. The, stays uchaged although we issued a pulse at G, sice we had S=R= 0. The, S= 0 ad R= chages to 0. Evetually, we issue a pulse i G whe S=R=. From the time this pulse eds, we do ot kow what is util Aother pulse i G with S R. 4.3) A -latch We saw that the SR latch is capable of storig oe bit of data. However, it seems a little bit complicated to set it ad reset it usig two iputs. We probably would prefer to use a simpler versio of that latch which gets a sigle bit at its iput ad stores it wheever G is. A additioal iverter will do this miracle: G Figure 4.6 latch This ew latch, called a -latch is simpler to use.

7 Chapter 4: Sequetial Logic 7 ( copyright by aiel Seider) From its truth-table G + 0 X 0 0 we see that the -latch is trasparet whe G=, i.e., the output follows the iput (with a small delay). Whe G is chaged to 0 the circuit becomes locked. It latches the data that was i the iput (ad therefore also at the output) at the miute of chagig the G from to 0. G locked locked locked trasparet trasparet Figure 4.7 -latch waveforms Istead of drawig the 4 NAN gates formig the -latch, we have a special drawig for - latch: G Figure latch

8 Chapter 4: Sequetial Logic 8 ( copyright by aiel Seider) We ca build a shift register usig -latches. A 3 bits shift register is built of 3 -latches coected i series. The output of the st -latch is coected to the iput of the ext -latch ad so o, as draw below: ata i 0 0 ata out G G G GF Figure A shift register made of latches Let us assume that the data iside the shift register is 00 as i Figure 4.9. We wat to eter a to the first (the left had side) latch. The we wat the data i the register to move or to shift oe positio to the right. Whe issuig a short pulse i G, the latches become trasparet. So each iput data goes through the latch to the output as we desired. However, there is a chace that the 2d latch reacts so fast that the data propagates through 2 latches durig the same pulse i G. There are several solutios to avoid this disastrous behavior. The simplest way is to add delay elemets betwee the latches, each havig a delay larger tha the width of the pulse give at G. This esures that the old data at the iput of a latch, stays there durig the period of time i which G is ad the latch is trasparet. The data i the iput will therefore chage oly after the latch becomes locked ad so there is o dager of propagatio of the data through two or more stages. ata i tpd tpd G G G G t pulse < t pd Figure A shift register made of latches ad delay elemets This way of hadlig the race betwee the data propagatig through the register ad the pulse i G, is ot the cosidered as good practice owadays. The preferred solutio is to covert the

9 Chapter 4: Sequetial Logic 9 ( copyright by aiel Seider) latches ito a Master-Slave Flip Flops. Before turig to explai that solutio we would like to discuss oe or two last examples of latches. 4.4) The JK-latch The JK latch behaves similarly to the SR-latch with oe exceptio. Here a i both iput is allowed. J K G Figure 4. A JK latch The aalysis of this latch is similar to the aalysis doe for the SR-latch. We see that havig G= 0 is equal to havig J=K= 0 which is idetical to havig S=R= 0 i the SR-latch. We ca see that o matter what is the iitial state of the latch, havig J= ad K= 0 causes to become which i tur causes to become 0. The oly chage here is that this 0 i the eutralizes the i the J iput. But this happes after the chage, i.e., whe the is already i its correct state. Whe J=K= we ca cosider the feedback lies we added as coectig the to the S iput of a SR-latch ad coectig the to the R iput of a SR-latch. This meas that the latch will ivert its state sice whe we have = ad = 0 we force 0 to S ad to R ad vice versa. So we get the followig truth-table:

10 Chapter 4: Sequetial Logic 0 ( copyright by aiel Seider) G J K + 0 X X A latch that chages its state i every pulse i G is called a T-latch where T stads for toggle. Whe we have J=K=, the JK-latch behaves as a regular T-latch. It is uderstood that we ca create a T-latch easily by coectig the of a SR-latch to the R iput ad the to the S iput. We otice that T-latch or a JK-latch with i the J ad K iputs have also a race problem. Whe G= the latch chages its state. Now, whe this chage is completed, the feedback to the iputs is also iverted. Therefore, if the pulse i G is too log, there might be aother toggle of the latch, back to its origial state! Agai, we ca solve this problem by addig delay elemets i the two feedback lies. Agai, the preferred solutio is to use the Master-Slave method. 4.5) A Master-Slave -FF As we will see i a miute, the memory device we itroduce ow will be edge sesitive ad ot level sesitive. By that we mea that the -latch was trasparet whe the level at the G iput was. A Mater-Slave -FF (MS -FF), will acquire, or sample, the data i its iput at the risig edge of the Clock iput (). We cosider all memory devices which are level sesitive as latches ad all the memory devices that are edge sesitive as Flip-Flops. Latches are trasparet at certai times, Flip-Flops are ever trasparet.

11 Chapter 4: Sequetial Logic ( copyright by aiel Seider) The followig drawig describes a Master-Slave -FF: P R Figure 4.2 A Master-Slave -FF This circuit is actually two -latches i series as show below: G G Figure MS -FF as two -latches The priciple of operatio is simple. Whe the clock sigal () is 0 the left had side latch, called the Master, is trasparet. Therefore follows the iput. At this time, the right had side latch, called the slave, is locked ad stays without a chage. Whe the chages from 0 to, i.e., exactly at the risig edge of the, the Master latch gets locked, keepig its output,, as it was exactly before the risig edge of the. At the same time, the slave becomes trasparet. Therefore, we get the value of i. The result is that we have a bit memory device which is loaded at the risig edge of the, with the data that was i its iput just before the risig edge of the. Chagig the data at the iput whe the is has

12 Chapter 4: Sequetial Logic 2 ( copyright by aiel Seider) o ifluece o the output sice at that time the master latch is locked. Whe is chaged to 0, the Master latch becomes trasparet, but the output still does ot chage eve if the iput is chagig sice at that exact time, the Slave latch gets locked ad so it keeps the output util the ext risig edge of the. This is show i Figure 4.4 below: Master is trasparet. follows the iput Master is locked does t chage. Slave is trasparet so gets Figure MS -FF behavior Note that we could have built the FF to be sesitive to the fallig edge by just movig the iverter from the Master latch to the Slave latch. We cosider a Master-Slave -FF as a device lookig at the data at its iput at the time of the risig edge of the sigal. That data appears at the output immediately after the risig edge of the. This is the exact way we should aalyze ay system havig MS -FFs. The P ad R iputs are sometimes used to Preset or Reset the -FF asychroously, i.e., with o relatio to the, e.g., at system iitializatio.

13 Chapter 4: Sequetial Logic 3 ( copyright by aiel Seider) Before we go ito some timig issues i detail, we would like to show that this ew setup eables us to build a shift register. We use a special drawig for -FFs. It is very similar to the -latch except that the iput is marked by a small triagle. (I FFs which are sesitive to the fallig edge of the we also add a circle to the iput). Figure 4.5a - A risig edge triggered -FF Figure 4.5b - A fallig edge triggered -FF A shift register will therefore look like this: ata i 0 0 Figure Shift register made of FFs Whe is, the outputs of the masters, i.e., the s, are trasferred to the FFs outputs. Let us assume that i this case we see the combiatio of 00 i the register (i the 3 outputs), as i Figure 4.6 above. Whe goes low, the slaves get locked, so the 3 outputs do ot chage. However, the masters become trasparet, so ew data goes ito the s, i.e., ito the middle of the FFs, as is described by the arrows i Figure 4.7 below. The data stays there, waitig for the risig edge of the. ata i 0 0 = Figure Shift register with = 0

14 Chapter 4: Sequetial Logic 4 ( copyright by aiel Seider) Whe the risig edge of the comes, the masters get locked right away. The slaves the become trasparet, ad trasfer the data that was i the middle of the FFs to the outputs: ata i 0 = Figure Shift register with = Although the data propagated through oe FF, it caot cotiue to propagate through the ext FF sice the masters are locked. This meas that i every risig edge of the, the data will be shifted oe positio to the right, which is exactly what we wat. Note that we ca use groups of flip-flops arraged as a shift register, but we ca also arrage those as a register gettig separate bits at its iput, thus keepig a bits umber. Sice all FFs are coected to the sigal, wheever the risig edge of the arrives, this register will sample its iput lies ad will update the umber it keeps. We usually draw such a register as a sigle box as show i the right had side of Figure 4.9 below. 0 0 [-:0] [-:0] - - Figure 4.9 A bits register

15 Chapter 4: Sequetial Logic 5 ( copyright by aiel Seider) 4.6) Timig issues i MS FFs We uderstad that the data at the iput of a MS -FF is sampled at the risig edge of the. What if we chage the data exactly at that time? We, ad the FF, caot decide which is the right value to be sampled ito the FF. So, a iterestig questio is: How log before the risig edge of the should the data be valid at the iput of the FF? The aswer is that we have to set to its fial value, i.e., the value we wat to be stored i the FF by the risig edge of the, leavig eough time for the delays of the iverter ad the 2 NAN gates at the iput of the Master latch, ad for the delays of the two NAN gates cosistig the Master latch, so the value is updated to the fial value before we are allowed to give the risig edge of the. If we will ot leave the iput data hagig there for eough time, we might issue the risig edge at a time i which both outputs of the Master are equal (which happes oly for a short time). I such a case we caot be sure that the output of the Master will have the value we meat it to have, sice we just did ot let the circuit eough time to stabilize. The requited time we eed to keep the data valid ad stable at the iput prior to the risig edge of the is called the setup time. Aother iterestig questio is: Whe ca we remove the data from the iput after the risig edge of the? The aswer to this questio is that we also eed to wait some time. At least, we have to wait util the 2 NAN gates at the iputs of the Master latch are blocked so a chage i will ot pass through ito the Master before it becomes locked. The required time we have to keep the data valid ad stable at the iput after the risig edge of the is called the hold time. The third ad last questio is; How log will it take to the data to appear at the output of the FF after the risig edge of the? This time depeds of the speed of the propagatio through the Slave latch. We call this time as the FF delay or to delay. These 3 importat time itervals are show i Figure t hold t setup Valid data t to Figure 4.20 Timig defiitios i MS FFs

16 Chapter 4: Sequetial Logic 6 ( copyright by aiel Seider) We had draw the two possible values of ad o the same drawig. The may trasitios of followig the risig edge of the oly mea that we do ot really kow whe the chage had occurred. The maufacturer of the -FF assures us that the maximum time that will take the trasitio to happe, for the etire temperature rage to which this FF was desiged, is t Ckto. We should always meet the setup ad hold time requiremets, otherwise we are riskig ourselves with systems which will sometimes store the data ad some times wo t, ad worse tha that, with systems that will eter a metastable situatio i which the FF does ot kow to which fial state it really should chage to, ad might get stuck i a ivalid state (ot havig valid logic levels at its output) for a log time, or oscillate. 4.7) Cotrol the writig ito a FF From ow ad o, we oly cosider MS -FFs i our desigs. The -FF loads ew data i every risig edge of the. As we will evetually see, the sigal is coected to all the FFs i the computer. Everythig happeig i the computer happes betwee the risig edge of the ad the ext risig edge of the. It is reasoable that sometimes, we would like to keep data i a certai FF without chagig (i.e., loadig) it i every. How ca we do that? The simple solutio we ca thik of is to add a AN gate o the as draw i Figure 4.2, with a sigal called the Write_Eable (WE). Whe WE is, the gets to the FF, whe the WE is 0, it is blocked, so the FF is ot clocked ad therefore keeps its data uchaged. However, this is ot a good practice. First, we make it difficult to satisfy the setup ad hold requiremets ad to assure proper operatio of the circuit. That FF receives the risig edge of the later tha other FFs i the circuit due to the delay of the AN gate we added. There is a chace that the output of aother FF which feeds the iput of our FF, will chage fast eough so it will be loaded ito our FF oe cycle too soo. Furthermore, the WE sigal itself, also depeds o the risig edge of the, i.e., it rises ad falls some time after the risig edge of the. This might cause a glitch at the ed of the WE sigal. The ed of WE follows the risig edge of, i.e., oly after gets to, the WE sigal becomes 0. This meas that for a short period of time, we have = ad WE= ad so we might get a short i. This is ot allowed, sice we caot kow what will be the FF s reactio to a very short pulse i its clock iput. (By the way, whe we use FFs which are triggered by the fallig edge of the, we do ot have such a sceario, but a glitch still may occur due to skew. What is a skew? sigals do have some skew, i.e., a slight differece i timig due to differet legths of the physical paths i the circuit. This is why we might get the WE sigal before the edge of which had created it, thus, causig a glitch i ). Sice the sychroizes the operatio of all parts i the computer, ad sice as we saw, it is difficult to touch it without havig complicatios, we always try to avoid temperig aroud with the. It is difficult eough to make all s i the system with miimal skew. We prefer to leave the utouched. This solutio is therefore ot the oe we choose.

17 Chapter 4: Sequetial Logic 7 ( copyright by aiel Seider) WE WE A glitch Figure ANig the Istead, we choose to cotrol the iput data of the FF. We add a Multiplexer at the iput of the FF. The WE sigal cotrols the Mux. Whe it is 0 the output is fed back to the -iput. Therefore, whe the risig edge of the arrives, the FF will load itself with the same data, i.e., o chage will occur. Whe the WE is, the Mux feeds the -iput directly from the ata_i iput (deoted i Figure 4.22). Therefore, after the risig edge of the, we ll have the ata_i value stored i the FF.

18 Chapter 4: Sequetial Logic 8 ( copyright by aiel Seider) Also draw as: 0 WE WE d0 d d2 d3 d4 d5 WE d0 d d4 Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Figure 4.22 The right solutio: WE operates o the data As ca be see from Figure 4.22, the WE iflueces at the ed of the cycle i which it was issued, i.e., the risig edge of the which caused the WE to chage to is ot the oe which samples the data ito the FF. The ext risig edge of the, i.e., the oe which occurs whe the WE is already, samples the data ito the FF. The red arrows show the depedecy of the WE o the. They coect the risig edge of the which caused the WE to chage to that chage.

19 Chapter 4: Sequetial Logic 9 ( copyright by aiel Seider) Thus, the FF behaves like that: Whe the risig edge of the arrives, the FF checks whether the WE is or 0. If it is 0, o chage occurs i the FF, if it is, the iput data is writte ito the FF. We will use this rule from ow o, wheever our FFs have WE iputs. A register built of -FFs each havig a WE iput, is a register which samples its data iputs at the risig edge of the if the WE sigal was at the time of the risig edge. Otherwise, the register keeps its data uchaged. We draw a register with a WE iput as a sigle box as show i Figure 4.23 below. Note that is it made of FFs havig a WE which is idetical to a regular register with a x(2 ) mux [-:0] 0 [-:0] [-:0] [-:0] WE WE WE Figure 4.23 A register with a Write_Eable (WE) iput

20 Chapter 4: Sequetial Logic 20 ( copyright by aiel Seider) Let us ow demostrate the usage of registers with ad without WE iputs. We cosider the circuit depicted i Figure The data o the.in iputs starts with 0 ad chages to ad the to 2 ad the to 3 ad so o, o every risig edge of the. reg A reg.in[-:0] [-:0] A[-:0] B reg B[-:0] Figure registers coected by a BUS Let us first draw the sigals at the iput of the left-had side register, we called the reg. We prefer to draw all those sigals o top of each other so we get a sigle drawig of the BUS. A BUS is a buch of wires coectig several registers. Here the iput bus is deoted.in[(- ):0]. This is show i Figure 4.25 below.

21 Chapter 4: Sequetial Logic 2 ( copyright by aiel Seider).IN 0.IN.IN 2 0 Istead of specifyig each sigal separately, we draw all lies.in[-:0] or just.in together. We eed therefore to specify their value:.in = [0] 4 5 Figure 4.25 rawig of sigals o a bus So, the waveforms, i.e., the drawigs of the sigals at.in,, A ad B should be as show i Figure IN ? A ad B??? Figure 4.26 Waveforms without WE iputs

22 Chapter 4: Sequetial Logic 22 ( copyright by aiel Seider) Now we chage the circuit as depicted i Figure The -FF o the bottom creates alteratig WE_A ad WE_B sigals. WE_B is actually the NOT of WE_A. reg A reg.in[-:0] [-:0] A[-:0] WE_A B reg B[-:0] WE_B Figure 4.27 Usig registers with WE iputs So ow the waveforms resultig from the same.in are totally differet. Whe we aalyze the circuit, we remember that a register with a WE iput samples ew data oly at the risig edge of the whe the WE iput is. Sice the WE_A ad WE_B iputs alterate betwee 0 ad, chagig at each risig edge of the, the registers will sample ew data at every 2d risig edge of the. Sice WE_A is the NOT of WE_B, register A will sample the eve data ad register B will sample the odd data. This is show i Figure 4.28 below.

23 Chapter 4: Sequetial Logic 23 ( copyright by aiel Seider).IN ? WE_A WE_B A?? B???? 3 5 Figure 4.28 Waveforms with the WE iputs It is clear that by cotrollig the WE sigals we ca cotrol the data flow i the circuit. If both WE_A ad WE_B are at the risig edge of the, the both registers are loaded with ew data. If oly oe of them is, the correspodig register is loaded. If both of them are 0, oe of the two registers is loaded. The processor we will desig, as most machies, is build of two differet parts: the ata Path ad the Cotrol. The data path has registers, ALU, adders, muxes, ad memories. The cotrol uit produces all cotrol lies which determie what will be the flow of the data iside the ata Path. Now, we ca guess that this is doe usig the WE sigals of the registers. Let us give aother example of cotrollig a register. Here we would like to desig a smart Shift- Register. First we ll describe the coectios required for a shift register i which each risig edge of the shifts the data oe positio to the right. The we ll modify the coectio so the data will be shifted to the left at each. The we ll add a iput R which will determie the directio of the shift. Whe R=, the data is shifted to the right. Whe R=0, the data is shifted to the left. This is depicted i Figure 4.29.

24 Chapter 4: Sequetial Logic 24 ( copyright by aiel Seider) A Shift register which shifts to the right A Shift register which shifts to the left R A Shift register which shifts to the right whe R= ad to the left whe R=0 Figure 4.29 A smart shift register

25 Chapter 4: Sequetial Logic 25 ( copyright by aiel Seider) Istead of drawig the shift register we could have writte its equatio. The -th FF, which stores the bit of the register has a iput marked by ad its equatio is: = R + R + I a similar maer we ca desig a eve more sophisticated shift register which has 2 cotrol lies, S ad S 0. There are 4 possible combiatios to these two lies. Whe (S,S 0 )=(0,0) we wat the register to perform a left shift. Whe (S,S 0 )=(0,) we wat the register to perform a right shift. Whe (S,S 0 )=(,0) we wat the register to hold ad whe (S,S 0 )=(,) we wat the register to be loaded from a.in bus. The equatio is:. IN = S S + S S + S S + S S A exercise: esig a 8 addresses 6 bits wide sychroous memory. The memory should be built of 8 registers with WEs. The memory has 3 address lies. We put the address from which we wat to read, or to which we wat to write, o these 3 lies. The memory has 6 ata I lies o which we put the data to be writte ito the memory. The memory has also 6 ata Out lies o which we fid the data read from the memory. Make sure that you ca always read from the memory. We write ito the memory at the risig edge of the, (that is why we called it sychroous memory), ad oly if the Memory_Write (MW) sigal is.

26 Chapter 4: Sequetial Logic 26 ( copyright by aiel Seider) 4.0) State machies So far we used the sequetial devices, the FFs, to build memories. This is ot the oly usage of FFs. We ca use FFs to build State-Machies. A state machie is a system havig some predefied states. At all times the machie is i oe of these states. It may chage its state accordig to some rule that we defie. We use state-machies i the cotrol part of computers. The basic structure of a state machie is very simple. We have a State-register, keepig the curret state, ad a combiatioal system calculatig the ext state. At the risig edge of the clock (), the state-machie goes to the ext state (the state-register is loaded with that state) ad the calculatio of a ew ext state begis. state-register ext state calculatio Figure 4.30 The basic structure of a State-Machie

27 Chapter 4: Sequetial Logic 27 ( copyright by aiel Seider) A simple example of a State-Machie is a biary couter. Let us look at a 3 bits biary couter. It is a machie, built of 3 FFs, which goes from state to state at the risig edge of the. Its State- iagram, i.e., the diagram describig the states ad the trasitios betwee the states, is quite simple: S 0 S S 2 S 3 S 4 S 5 S 6 S 7 Figure 4.3- A State-iagram of a biary couter Buildig such a state machie is easy. First, we choose a biary represetatio for the 8 states. I biary couters, the most atural choice is to represet S i with the biary umber i. So we choose to represet S 0 with (0,0,0), S with (0,0,) ad so o. Now we would like to build the system which chages its states accordig to the State-iagram of Figure 4.3. We use a 3 bits register to keep the curret state. Three bits are eough, sice i this case, we have oly 8 states ad 8=2 3. The 3 bits biary couter looks therefore like that: Next state calc Figure A 3 bits biary couter

28 Chapter 4: Sequetial Logic 28 ( copyright by aiel Seider) The 3 FFs keeps the curret state. The combiatioal system which gets 0, ad 2 at its iputs, ad produces 0, ad 2 at its outputs, just calculates the ext state accordig to the curret state. This is a system from the kid we dealt with i chapter. We ca write dow its truth-table ad fid its equatios: iputs of the combiatioal system outputs of the combiatioal system We ca easily see that the equatios describig this feedback system are: = 0 0 = + = = 2 2 ( ) + ( ) = ( ) We could have foud the equatio describig the -th iput of a biary couter by ivestigatig the special behavior of Biary couters. We are goig to do just that i the followig pages. However, the method described above, i.e., writig the truth table of the i -s as a fuctio of the state register j -s, will always work.

29 Chapter 4: Sequetial Logic 29 ( copyright by aiel Seider) The mathematical calculatio we actually do i a biary couter is X=X+. The bit X will chage oly if we have carry from the additio of X[-:0]=[X -,,X 0 ] ad. This happes oly if all the bits X -, X -2,, X 2, X, X 0 are s. So the equatio of is simple: Chage polarity if all the bits lower tha are s. Stay as before, i.e., do ot chage polarity, if Not. Thus, = (... ) + (... ) This ca also be writte as = (... ) 2 0 Let us ow fid the equatio of the iput of a dow couter. I a dow couter we calculate X-. Similarly to the case of additio, X chages its polarity oly if we have borrow from the calculatio of X[-:0]-. Thus, all bits i X[-:0] must be 0 s i order to have borrow. So the equatio of will follow: Chage polarity if all the bits lower tha are 0 s. Stay as before, i.e., do ot chage polarity, if ot. or = (... ) + (... ) = ( ) + ( ) This ca also be writte as = ( ) 2 0 or = ( ) 2 0 Now we would like to add some fuctioality to the couters. The first thig is to add a Eable iput deoted E. The couter should cout oly if E=. If E= 0, the couter holds. This is simple to do. If E= ad the coditio to chage polarity is also, the we chage polarity, i ay other case we do t:

30 Chapter 4: Sequetial Logic ( copyright by aiel Seider) 30 or We ca also add a CLR cotrol lie to a couter. Wheever we have a i the CLR lie, we wat the couter to chage to zero i the ext risig edge of the. Whe CLR= 0, we wat the couter to cout regularly. The ext equatio does that by makig sure that all the iputs are 0 whe CLR=, ad so the couter becomes zero Now, we wat to have the eable lie E ad the CLR lie as well: I this equatio, CLR beats the E iput. Thus, the fuctio of the couter is: If CLR=, it clears, else if E= it couts up, else it holds. We could ask that the E iput will have the priority, i.e., that the fuctio of the couter is differet: If E= 0, the couter holds, else if CLR=, it clears, else it couts up. For this we eed to arrage the equatio somewhat differetly: Here the CLR is coditioed o E=. If E= 0, we ca disregard the CLR. We could also write: If E= 0, we have =, i.e., the couter holds. If E= ad CLR=, we have = 0, i.e., we clear the couter. If E= ad CLR= 0, we have the regular equatio of a up couter, so the couter couts up (i.e., the appropriate -s will chage their polarities). E E + + = )... ( )... ( )... ( )... ( E E + = CLR + = ] )... ( )... ( [ CLR E E + = ] )... ( )... ( [ E CLR E E + = ] )... ( )... ( [ )... ( )... ( E CLR E CLR E + + =

31 Chapter 4: Sequetial Logic 3 ( copyright by aiel Seider) The last example of a couter equatio is that of a up/dow couter who has a cotrol lie deoted UP. Whe UP=, the couter couts up. Whe UP= 0, the couter couts dow. We build its equatio from the equatio of a up couter coditioed o UP= ad the equatio of a dow couter coditioed o UP= 0 : =... ) UP + ( ( ) UP We could also request to add a CLR, Eable or Load lies with ay priority that we desire. Note that these equatios are correct for biary couters that have bits ad 2 states. It does ot work whe the couter has less tha 2 states, sice is such a case the rule that a bit chages its polarity whe all the lower bits are s, is ot correct. Let us examie the case of a biary couter that couts up to 2. We first write dow its truth-table ad the fid its equatios: iputs of the combiatioal system Outputs of the combiatioal system Note that we chose to clear the couter if for some reaso, say after power-up, we reach the state of [,]. We ca easily see that the equatios describig this feedback system are: = 0 0 = 0 This is described i Figure 4.33 below. We also added a CLR iput (draw i dashed lies).

32 Chapter 4: Sequetial Logic 32 ( copyright by aiel Seider) Next state calc. 0 0 CLR Figure A biary couter from 0 to two The rule accordig to which we chaged states i the biary couters was very simple. We always wet to the ext state. We could asks for some exteral sigal to ifluece the trasitios from state to state. Actually, we already did that i biary couters havig the Eable or CLR iputs. Followig, we see a state diagram i which we chage the state accordig to some coditios. Whe we are i state S 0, the if A= 0 we stay i state S 0. If A= we go to state S. From state S we go to S 2 if B= ad retur to S 0 if B= 0. From S 2 we go to S 0 if A= ad stay i S 2 if ot. A ad B are the iputs of the state-machie. This is very similar to a flow chart describig a computer program. Note that the OR of all coditios goig out from a certai state, must be. Otherwise, it meas that uder some coditio we wo t be able to decide where to go.

33 Chapter 4: Sequetial Logic 33 ( copyright by aiel Seider) A=0 S 0 A= S B=0 A= B= S 3 S 2 A=0 Figure 4.34 A State iagram with iput coditios I order to support iput coditios, the oly chage we eed to do i the structure of the State- Machie of Figure 4.30, is to add the sigals A ad B as iputs to the Next state calculatio part of the system, as i Figure 4.35 below. state-register ext state calculatio iputs m Figure 4.35 A State-Machie with m iputs For our example, we eed at least 2 bits to represet the 3 states S 0, S ad S 2. We choose the represetatio, i.e., the codig of the states to be: S 0 =(0,0), S =(0,) ad S 2 =(,0). We otice that two bits have 4 possible combiatios. Thus, we have to make sure that the 4-th combiatio, (,), ever occurs. Otherwise, it is possible that whe the system is powered up, the state register will have this 4-th state as its iitial state. I case we do ot iitialize the State-Machie with a RESET sigal (which could be asychroous, i.e, coected to the R or P iputs described i sectio 4.5), there is a chace that we get stuck i this 4-th state. I some cases, there are more

34 Chapter 4: Sequetial Logic 34 ( copyright by aiel Seider) tha a sigle u-used state ad we could loop iside those states forever. To avoid such a case, we add the 4-th state, called S 3, to out diagram, ad force the State-Machie to go from that state to S 0. So here we have the truth-table of the ext state calculatio system: iputs Outputs A B X X X X X 0 0 X X X 0 0 We see that the equatios describig this feedback system are: = A 0 0 = + B A 0 0 Note that we have arbitrarily chose a certai represetatio of the states. We could have chose other represetatios such as S 0 =(0,), S =(,0) S 2 =(,) or eve a Oe-hot represetatio of S 0 =(0,0,), S =(0,,0) S 2 =(,0,0). Some represetatios are easier to decode, some require less gates, etc. We choose whatever represetatio we like. I case we would have chose the Oe-hot represetatio, the truth-table would have bee: Iputs Outputs A B X X X X X X X X All other states 0 0

35 Chapter 4: Sequetial Logic 35 ( copyright by aiel Seider) Ad the equatios: = A B A ( ) = A 2 0 = B A We ow wish to modify the structure of the State-Machie so that we could issue output sigals at certai states. Suppose we wat to issue i the output lie called Z wheever we are i state S 0 or S. Suppose we also wat to have i aother output, called Y, wheever we are i states S ad S 2. We update the state diagram to show us our requested outputs: A=0 S 0 Z= A= B=0 S Z=,Y= A= B= S 3 S 2 Y= A=0 Figure 4.36 A State iagram with iputs ad outputs We usually write the active outputs iside the states i which they are active. All other outputs have their default value which is cosidered 0 uless otherwise specified.

36 Chapter 4: Sequetial Logic 36 ( copyright by aiel Seider) I order to support this by our state-machie we have to add a output decoder with the truthtable of: iputs outputs 0 Y Z ?? We have chose that Y ad Z are 0 whe [, 0 ]=[,]. The equatios describig this decoder are: Z = Y = + = (Note that i case of a Oe Hot represetatio, the output decoder is made of OR gates oly). So we have reached the complete structure of a Moore State-Machie give i Figure 4.37 below. state-register ext state calculatio output decoder k m Figure 4.37 A complete Moore State-Machie

37 Chapter 4: Sequetial Logic 37 ( copyright by aiel Seider) A good example demostratig the relatio betwee the states, the iputs ad the outputs is a state machie of a traffic sigal. It has oe iput, a butto that is pressed by the policema operatig the sigal. It has three outputs, the Gree Yellow ad Red lights. It has may states as described i the ext diagram: Butto ot pressed Butto ot pressed Red (R= ) Butto pressed YellowRed (Y=R= ) Gree (G= ) Butto pressed Off Gree2 (G= ) Off2 Gree3 Off3 Yellow (G= ) (Y= ) Figure 4.38 A State-iagram of a traffic sigal I this example, we see clearly that the outputs deped o the states. The red output is o i two states. There are states i which o output is o, etc. We see that the decoder that produces the outputs should oly cosider the curret state ad ot the iput. The iput oly determies the trasitio from certai states to some other states, ad so it has to be cosidered i desigig the ext state calculatio block.

38 Chapter 4: Sequetial Logic 38 ( copyright by aiel Seider) We will use State-Machie to build the cotrol part of computers. Their iputs will be the istructio bits ad their outputs will be the cotrol sigals. We should kow that i some cases we would like to avoid decodig o output sigals, e.g., whe it is importat to keep a certai output at also durig the trasitio betwee states ad to avoid glitches. Such outputs will have their ow FF, i.e., o decodig. I the example of Figure 4.36, Z is such a output while Y may have a glitch if durig the trasitio from S (0,) to S 2 (,0) we temporarily have (0,0) or (,). We also should kow that sometimes the iputs should ifluece the outputs directly, i.e., immediately ad ot at the ext risig edge of the. This caot be doe by a Moore State- Machie demostrated i Figure I order to support such requiremet, we must used aother structure of a State-Machie called a Meally State-Machie, which is described i Figure 4.39 below. state-register ext state calculatio output decoder k m Figure 4.39 A complete Meally State-Machie Meally state-machie ca be more efficiet tha Moore state-machie, i.e., less logic is required to produce the same behavior. However, whe two Meally stste-machies are coected i series, the miimal clock cycle is decreased, while the Moore state-machie has o such limitatio. Now we have all the ecessary kowledge to build a computer. We will defie its laguage, i.e., its istructio set. From that we will build the ata-path, i.e., the registers, ALU, Memories ad all other data storig ad maipulatig devices which perform the istructios we defied, ad the, we ll add the proper cotrol circuit which is implemeted usig a state machie.