DESCRIPTION OF THE SYSTEM

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1 Sychroous-Serial Iterface for absolute Ecoders SSI 1060 BE 10 / 01 DESCRIPTION OF THE SYSTEM TWK-ELEKTRONIK GmbH D-001 Düsseldorf PB 1006 Heirichstr. Tel +9/11/6067 Fax +9/11/ ifo@twk.de

2 Page 0. Table of cotets Advatage of the SSI over parallel iterfaces.... Mode of fuctioig ad block diagram of the SSI.... Savigs i lies with SSI.... Trasmissio protocol.... Trasmissio example for a ecoder with 1 bits Sigle trasmissio Multiple trasmissio.... SSI cotrol electroics Iput ad output circuits Selectio of the clock frequecy ad of the mooflop time Maximum data trasmissio rate Precoditios Trasmissio lik Delay times of the idividual uits Sigificace of the time by which the evaluatio (readig-i) of the data as trasmitted should be delayed...

3 1. Advatage of the SSI over parallel iterfaces Sigificatly less expediture for cablig: I the case of bit ecoders, oly lies are eeded for the trasmissio of data istead of. Expediture for cablig ad iterface compoets does ot deped o the legth of the data word. Screeig out of oise is achieved through the clock ad data sigals beig trasmitted sychroously ad symmetrically via twisted pair lies. Multiple trasmissio of each data word provides a automatic plausibility check. Absolute Ecoder ad receptio electroics are separated with opto-couplers rederig earthig loops uecessary.. Mode of fuctioig ad block diagram of the SSI The parallel iformatio i the ecoder is coverted by a iteral parallel-serial coverter (shift register) ito serial form ad is trasmitted to a receptio electroics uit sychroously with a clock. Block diagram of a multitur absolut ecoder GaAlAs Diodes Photo trasistors + V S Multi-fuctioal ASIC clock + clock - data + data - Opto Array Aalog Asic code sese - V S (0 V) The sychroized trasmissio of each data word is iitiated ad cotrolled by the receptio electroics with the aid of a clock sigal. The legth of the clock sequece (sequece of clock sigals) determies the legth of the data word so that data words of ay desired legth ca be trasmitted with this SSI system. A clock sequece of + 1 cycles is eeded to trasmit a data word with bits. The speed of trasmissio is determied by the clock frequecy.. Savigs i lies with SSI I the case of a multitur ecoder with parallel output ad, for example, 096 positios/revolutio ad 096 revolutios ( bit), wires are eeded to trasmit the data. The SSI, o the other had, requires oly oe twisted pair lie for the data (data+, data-) ad oe twisted pair lie for the clock (clock+, clock-). The lie requiremets for operatig voltage ad additioal fuctios (e.g. code sese) are the same i both cases. As a miimum a cable with 6 wires (clock, data ad supply voltage) is required.. Trasmissio protocol The logic levels as metioed i the text relate to the clock + or, as the case may be, data + sigal. I the idle or iitial state of the SSI, both clock ad data lies (clock +, data +) are Log 1. The receptio electroics iitiates the trasmissio of data by chagig the clock sigal from Log 1 to Log 0. This chage causes a retriggerable mooflop i the ecoder to be set. I tur the output from the latter switches over a shift register from parallel to serial whereby the data, which is preset i parallel form i Gray code is stored. The ext time the clock chages from Log 1 to Log 0, the most sigificat bit of the agular positio iformatio is trasferred to the data output of the ecoder. Each further positive edge the causes the ext highest bit i each case to be trasferred util the least sigificat bit is at the output. At the same time the mooflop is retriggered with each egative edge of the clock. The mooflop time (e.g. 0 µs) determies the iterval betwee two trasmissios ad the miimum clock frequecy.

4 SSI iterface profile - bit Example: Absolute Ecoder with 096 positios / 60, 096 revolutios ad Gray tree as output code Idle state 1 CLOCK IN Waittime Idle state Idle state DATA OUT M9 M MSB Multitur bits Sigle-tur bits LSB sigificat data bits Total data word = bits = shift register legth The data lie is set to Log 0 with the last positive edge of the clock sequece. This termiates the trasmissio of the complete data word. If the clock sigal remais set at Log 1 (ed of the clock sequece), the mooflop is o loger retriggered so that the data sigal switches to Log 1 o the expiratio of the mooflop time. This state idicates the readiess to trasmit a ew data word (simple trasmissio of oe data word). If the clock sequece is ot termiated after the trasmittig of the least sigificat data bit, the stadard situatio is that a Log 0 is issued o the data lie with the ext positive edge. This itermediate clock sigal separates oe data word from a idetical data word that it follows. The positive edge followig the itermediate clock sigal edge geerates the most sigificat bit of the data word (repeat trasmissio of the same data word). This process ca be repeated as ofte as desired (multiple trasmissio of oe data word). Alteratively the SSI ca be arraged i such a way that the data sigal remais at Log 0 after the data word has bee trasmitted oce eve if further clock sigals follow.. Trasmissio example for a ecoder with 1 bits Ecoder with 10 positios/revolutio (10 bits i the sigle-tur part) ad 6 revolutios ( bits i the multitur part). I the stadard versio, the trasmissio protocol is set up for a data word with bits. Of these 1 bits are for the revolutios ad 1 for the resolutio (positios/revolutio). Sice trasmissio always starts with multitur bit whereby however i our example the multitur part is oly desiged for bits, blaks are first trasmitted with Log 0 ad the the loaded bits of the multitur part are trasmitted. The follow the sigletur bits startig with 0 ad goig to. Fially Log 0 is also trasmitted for the last three bits which are ot loaded. MSB < Data word with = Bit No. i data word > LSB M9 M M9 M M9 M M9 M S M Number of revs B its / rev. Multitur bits Sigle-tur bits Positio / rev. B its / rev.

5 6. Sigle trasmissio I the case of a sigle trasmissio, i.e. whe the curret positio data is read out oce, the clock sequece ca be termiated after the trasmissio of the LSB sice oly zeroes will follow this. Clock sequece Wait time Idle state Idle state Clock + P / S (Parallel / serial coverter) Data + Data word Most sigificat bit () Least sigificat bit () Bit (S 1) 7. Multiple trasmissio I the case of multiple trasmissio, i.e. whe the curret positio data is read out a umber of times, the clock sequece is desiged i accordace with the schematic below. Clock sequece 1st trasmissio Itermediate clock cycle ed trasmissio Wait time Clock + P / S (Parallel / serial coverter) Data + Most sigificat bit () Least sigificat bit (). SSI cotrol electroics The cotrol electroics geerate the clock sequece with which the trasmissio of the data word from the ecoder is regulated. I this uit the serial data ca be coverted back ito parallel form ad, if ecessary, Gray code ca be coverted ito atural biary code. Clock lie Ecoder 1 Data lie Driver Optocoupler P/ S P/ S G B Clock geerator Shift register Parallel output G/B - Gray-biary coverter Ecoder P/ S G B Shift register 9. Iput ad output circuits Parallel output The iput (opto-coupler) ad output (lie driver) circuits i the ecoder ad i the cotrol electroics ca be idetical.

6 Iput circuit +V +V 100R 1K TTL / HCMOS Logik / Logic 100R 6N17 (Optokoppler/ Optocoupler ) LED z.b. LR60 (rot) Siemes oder ähliche LED e.g. LR60 (red) Siemes or similar 1F 91R Takt IN+/ Clock IN+ Takt IN-/ Clock IN- +V Output circuit 7F TTL / HCMOS Logik / Logic 100pF Data OUT+/ Data OUT+ Data OUT-/ Data OUT- +V LTC (RS-/RS- Trasceiver) The output circuit is i the form of a differetial lie driver which fulfils complayig with RS / RS. The differetial, symmetrical desig esures a high degree of reliability i respect of oise. The use of opto-coupler iputs meas that earth loops are ot required ad this i tur reduces the sesitivity to oise still further. This is especially importat for situatios where a umber of ecoders are coected to oe cotrol electroics uit. 10. Selectio of the clock frequecy ad of the mooflop time The mooflop, which is set by the first egative edge of the clock sequece, keeps the parallel/serial coverter of the ecoder i its active phase. For this reaso it must remai set durig the trasmissio phase ad must be retriggered by each succeedig egative edge of the clock sequece. Accordigly the cycle time of the clock t T must be shorter tha the mooflop time t M. The cycle time is the reciprocal of the clock frequecy f T. t T = 1 f T < t M (mi) I the stadard versio, the mooflop time t M is set to 1 µs t M µs. The time t M determies the miimum clock frequecy f T ad the maximum wait time after the ed of trasmissio t W. t W is calculated from the last egative flak of the clock ad is idetical with t M. t W = t M Example t M = 10 µs to 0 µs Accordigly: cycle time f T ³ 1 / 10 µs = 100 khz Maximum wait time t W = t M (max.) = 0 µs 6

7 11. Maximum data trasmissio rate 11.1 Precoditios The maximum achievable data trasmissio rate (clock frequecy) is set for the drivers ad receptio electroics used as well as for the trasmissio protocol i accordace with the RS stadard. It must be oe half of the values stated i the stadard for the Baud rate. Both limit curves are show i the adjoiig graph. It is show below how the maximum data trasmissio rate ca be achieved by meas of measures o the receptio electroics side by takig ito accout the differet trasit times. F [MHz] khz maximum Baud rate i acc. with RS maximum clock frequecy ad data trasmissio rate for SSI 00 m Limit 100 m l CA [m] 11. Trasmissio lik The figure o the right shows i schematic form a SSI trasmissio lik. It cosists of ecoder, trasmissio cable ad clock sequece / receptio electroics. Naturally each of these uits has its ow delay or trasit time which delays the sigals. This leads to the situatio that the data reaches the receptio side i time with the clock sigals but delayed by the sum of the above-metioed delay times. Ecoder ( t c ) I K ( t K ) Cable Driver Clock sequece Receptio ad = t E clock logic > Data Clock Receiver 11. Delay times of the idividual uits I terms of delays, the complete SSI ca be subdivided ito three uits: o o o Ecoder electroics Clock ad data lies Receptio ad clock logic The delay time of the first is costat ad is specified for the ecoder. The delay times for the last two deped o the particular applicatio. The trasit time i the cable varies with the legth of the cable ad the delay i the electroics depeds o the logical uits used. Accordigly the followig applies for the total delay (TD): t TD = t C + x t CA + t E The cable delay has to be applied twice sice ot oly the clock sigal but also the data sigal must pass alog its full legth. The idividual items i the above formula are: t TD : total delay time betwee clock ad data sigal. t C : delay brought about by the electroics i the ecoder: for all TWK ecoders it is specified as maximum 10 s. t CA : cable delay; this delay depeds o the legth of the cable ad also o the cable used. It is defied as the product of the cable legth (l CA ) ad the specific trasit time for the cable. For the cable used by TWK, amely LIYCY-OB x x 0. mm², the specific trasit time is approx. 6. s/m. t E : delay time of the clock driver ad of the data receiver (opto-coupler). For the TWK serial/parallel coverter board SPC, it is specified to be maximum 10 s. 7

8 Accordigly the above values ca be iserted ito the formula Example: For a cable of legth 00 m the total delay is t TD (s) = 00 s + x 6. s/m x l CA (m) t TD = 00 s + x 6. s/m x 00 m = 900 s =.9 µs I the schematic below the sigificace of the total delay time t for trasmissio is represeted for the above example. The clock TD frequecy selected is 00 khz, amely the maximum permitted for a cable legth of 00 m. This clock frequecy is equivalet to a clock cycle time (t T ) of. µs. 11. Sigificace of the time by which the evaluatio (readig-i) of the data as trasmitted should be delayed As has bee show above, the total delay time for the trasmissio of the data is of the same order of magitude as the maximum possible legth of the clock sigal cycles. If the data is to be processed correctly, it must be read i by the receptio electroics at the right momet i time. Sice the period of time durig which the idividual data bits are preset ad stable o the receptio side is idetical with the clock cycle time, the readig i of the data must also take place durig the same time period (see schematic below). I order to balace out toleraces i a optimum maer, the middle of this time period should be selected. 00 KHz = ^, µs Period t T =, µs, µs Clock + Data + without delay Data + delayed t GV total delay time t =,9 µs t + t GV T stable data bits GV Readig-i clock t EV, µs Readig-i poits Delay applied to the readig-i clock,9 µs + ½ x, µs, µs t EV I order to maitai sychroism, the readig-i clock sequece should be the same as the data-trasmissio clock sequece but delayed relative to the latter by a suitable amout t EV : t TD < t EV < t TD + t T I this rage the data will be read i correctly with the positive edge. If readig i should take place i the middle of the time period, the followig applies: t EV = t TD + 1/ x t T This case is show i the schematic above for the example give i 11..

EE260: Digital Design, Spring n MUX Gate n Rudimentary functions n Binary Decoders. n Binary Encoders n Priority Encoders

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