Design of Digital Circuits Lecture 7: Sequential Logic Design. Prof. Onur Mutlu ETH Zurich Spring March 2018

Transcription

1 Desig of Digital Circuits Lecture 7: Seuetial Logic Desig Prof. Our Mutlu ETH Zurich Sprig March 2018

2 Readigs Please study Slides from Lecture 6 o your ow This week Seuetial Logic P&P Chapter 3.4 util ed + H&H Chapter 3 i full Hardware Descriptio Laguages ad Verilog H&H Chapter 4 i full Timig ad Verificatio H&H Chapters 2.9 ad Chapter 5 Next week Vo Neuma Model, LC3, ad MIPS P&P Chapter H&H Chapter 6 Digital Buildig Blocks H&H Chapter 5 2

3 What We Will Lear Today Circuits that ca store iformatio R-S Latch Gated D Latch D Flip-Flop Register Fiite State Machies (FSM) Moore Machie Mealy Machie Verilog implemetatios of seuetial circuits 3

4 Circuits that Ca Store Iformatio 4

5 Itroductio Combiatioal circuit output depeds oly o curret iput We wat circuits that produce output depedig o curret ad past iput values circuits with memory How ca we desig a circuit that stores iformatio? iputs Seuetial Circuit Combiatioal Circuit outputs Storage Elemet 5

6 Basic Storage Elemet: The R-S Latch 6

7 The R-S (Reset-Set) Latch The simplest implemetatio of the R-S Latch Two NAND gates with outputs feedig ito each other s iput Data is stored at Q (iverse at Q ) S ad R iputs are held at 1 i uiescet (idle) state S (set): drive S to 0 (keepig R at 1) to chage Q to 1 R (reset): drive R to 0 (keepig S at 1) to chage Q to 0 S ad R should ever both be 0 at the same time S Q Iput Output R S Q 1 1 Q prev R Q 0 0 Ivalid 7

8 Why ot R=S=0? S If R=S=0, Q ad Q will both settle to 1, which breaks our ivariat that Q =!Q 2. If S ad R trasitio back to 1 at the same time, Q ad Q begi to oscillate betwee 1 ad 0 because their fial values deped o each other (metastability) R Q 01 Q Iput This evetually settles depedig o variatio i the circuits (more metastability to come i Lecture 8) Output R S Q 1 1 Q prev Ivalid 8

9 The Gated D Latch 9

10 The Gated D Latch How do we guaratee correct operatio of a R-S Latch? S Q R Q 10

11 The Gated D Latch How do we guaratee correct operatio of a R-S Latch? Add two more NAND gates! D S Q Write Eable R Q Q takes the value of D, whe write eable (WE) is set to 1 S ad R ca ever be 0 at the same time! 11

12 The Gated D Latch D S Q Write Eable R Q Iput Output WE D Q 0 0 Q prev 0 1 Q prev

13 The Register 13

14 The Register How ca we use D latches to store more data? Use more D latches! A sigle WE sigal for all latches for simultaeous writes Write Eable D 3 D 2 D 1 D 0 Here we have a register, or a structure that stores more tha oe bit ad ca be read from ad writte to Q 3 Q 2 Q 1 Q 0 This register holds 4 bits, ad its data is refereced as Q[3:0] 14

15 The Register How ca we use D latches to store more data? Use more D latches! A sigle WE sigal for all latches for simultaeous writes Here we have a register, or a D 3:0 structure that 4 stores more tha oe bit ad ca be read from ad WE writte to Register x (Rx) Q 3:0 4 This register holds 4 bits, ad its data is refereced as Q[3:0] 15

16 Memory 16

17 Memory Memory is comprised of locatios that ca be writte to or read from. A example memory array with 4 locatios: Addr(00): Addr(01): Addr(10): Addr(11): Every uiue locatio i memory is idexed with a uiue address. 4 locatios reuire 2 address bits (log[#locatios]). Addressability: the umber of bits of iformatio stored i each locatio. This example: addressability is 8 bits. The full set of uiue locatios i memory is referred to as the address space. Typical memory is MUCH larger (billios of locatios) 17

18 Addressig Memory Let s implemet a simple memory array with: 3-bit addressability & address space size of 2 (total of 6 bits) D WE 1 Bit Q 6-Bit Memory Array Addr(0) Addr(1) Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 18

19 Readig from Memory How ca we select the address to read? Because there are 2 addresses, address size is log(2)=1 bit 19

20 Readig from Memory How ca we select the address to read? Because there are 2 addresses, address size is log(2)=1 bit Addr[0] Wordlie D[2] D[1] D[0] 20

21 Readig from Memory How ca we select the address to read? Because there are 2 addresses, address size is log(2)=1 bit Addr[0] Wordlie Address Decoder D[2] D[1] D[0] 21

22 Readig from Memory How ca we select the address to read? Because there are 2 addresses, address size is log(2)=1 bit Addr[0] Wordlie Address Decoder Multiplexer D[2] D[1] D[0] 22

23 Writig to Memory How ca we select the address ad write to it? 23

24 Writig to Memory How ca we select the address ad write to it? Iput is idicated with D i Addr[0] D i [2] D i [1] D i [0] WE 24

25 Puttig it all Together Eable readig ad writig to a memory array Addr[0] D i [2] D i [1] D i [0] WE D[2] D[1] D[0] 25

26 A Bigger Memory Array Addr[1:0] D i [2] D i [1] D i [0] WE D[2] D[1] D[0] 26

27 A Bigger Memory Array Addr[1:0] D i [2] D i [1] D i [0] WE Address Decoder Multiplexer D[2] D[1] D[0] 27

28 Seuetial Logic Circuits 28

29 Seuetial Logic Circuits We have looked at desigs of circuit elemets that ca store iformatio Now, we will use these elemets to build circuits that remember past iputs Combiatioal Oly depeds o curret iputs Seuetial Opes depedig o past iputs

30 State I order for this lock to work, it has to keep track (remember) of the past evets! If passcode is R13-L22-R3, seuece of states to ulock: A. The lock is ot ope (locked), ad o relevat operatios have bee performed B. Locked but user has completed R13 C. Locked but user has completed L22 D. Locked but user has completed R3 E. The lock ca ow be opeed The state of a system is a sapshot of all relevat elemets of the system at the momet of the sapshot To ope the lock, states A-E must be completed i order If aythig else happes (e.g., L5), lock returs to state A 30

31 Aother Simple Example of State A stadard Swiss traffic light has 4 states A. Gree B. Yellow C. Red D. Red ad Yellow The seuece of these states are always as follows A B C D 31

32 Chagig State: The Notio of Clock (I) A B C D Whe should the light chage from oe state to aother? We eed a clock to dictate whe to chage state Clock sigal alterates betwee 0 & 1 CLK: 1 0 At the start of a clock cycle ( ), system state chages Durig a clock cycle, the state stays costat I this traffic light example, we are assumig the traffic light stays i each state a eual amout of time 32

33 Chagig State: The Notio of Clock (II) Clock is a geeral mechaism that triggers trasitio from oe state to aother i a seuetial circuit Clock sychroizes state chages across may seuetial circuit elemets Combiatioal logic evaluates for the legth of the clock cycle Clock cycle should be chose to accommodate maximum combiatioal circuit delay More o this later, whe we discuss timig 33

34 Fiite State Machies 34

35 Fiite State Machies What is a Fiite State Machie (FSM)? A discrete-time model of a stateful system Each state represets a sapshot of the system at a give time A FSM pictorially shows the set of all possible states that a system ca be i how the system trasitios from oe state to aother A FSM ca model A traffic light, a elevator, fa speed, a microprocessor, etc. A FSM eables us to pictorially thik of a stateful system usig simple diagrams 35

36 Fiite State Machies (FSMs) Cosist of: Five elemets: 1. A fiite umber of states State: sapshot of all relevat elemets of the system at the time of the sapshot 2. A fiite umber of exteral iputs 3. A fiite umber of exteral outputs 4. A explicit specificatio of all state trasitios How to get from oe state to aother 5. A explicit specificatio of what determies each exteral output value 36

37 Fiite State Machies (FSMs) Each FSM cosists of three separate parts: ext state logic state register output logic CLK iputs M ext state logic k ext state k state output logic N outputs state register At the begiig of the clock cycle, ext state is latched ito the state register 37

38 Fiite State Machies (FSMs) Cosist of: Seuetial circuits State register(s) Store the curret state ad Load the ext state at the clock edge Next State CLK S S Curret State Combiatioal Circuits Next state logic Determies what the ext state will be Next State Logic C L Next State Output logic Geerates the outputs Output Logic C L Outputs 38

39 Fiite State Machies (FSMs) Cosist of: Seuetial circuits State register(s) Store the curret state ad Load the ext state at the clock edge Next State CLK S S Curret State Combiatioal Circuits Next state logic Determies what the ext state will be Next State Logic C L Next State Output logic Geerates the outputs Output Logic C L Outputs 39

40 State Register Implemetatio How ca we implemet a state register? Two properties: 1. We eed to store data at the begiig of every clock cycle 2. The data must be available durig the etire clock cycle CLK: 0 1 Iput: Output: 40

41 The Problem with Latches Recall the Gated D Latch D CLK = WE Q Curretly, we caot simply wire a clock to WE of a latch Whe the clock is high, Q will ot take o D s value AND Whe the clock is low, the latch will propagate D to Q CLK: 0 1 Iput: Output: 41

42 The Problem with Latches Recall the Gated D Latch D CLK = WE Q Curretly, we caot simply wire a clock to WE of a latch Whe the clock is high, Q will ot take o D s value AND Whe the clock is low, the latch will propagate D to Q CLK: 0 1 Iput: Output: 42

43 The Problem with Latches Recall the Gated D Latch D CLK = WE Q Curretly, we caot simply wire a clock to WE of a latch Whe the clock is high Q will ot take o D s value AND How ca we chage the latch, so that Whe the clock is low the latch will propagate D to Q 1) D (iput) is observable at Q (output) oly at the begiig of ext clock cycle? CLK: 0 1 Iput: 2) Output: Q is available for the full clock cycle 43

44 The D Flip-Flop 1) state chage o clock edge, 2) data available for full cycle D D Latch (Master) D Latch (Slave) Q CLK CLK: 1 0 Whe the clock is low, master propagates D to the iput of slave (Q uchaged) Oly whe the clock is high, slave latches D (Q stores D) At the risig edge of clock (clock goig from 0->1), Q gets assiged D 44

45 The D Flip-Flop 1) state chage o clock edge, 2) data available for full cycle D CLK Q Q D Flip-Flop CLK: 1 0 At the risig edge of clock (clock goig from 0->1), Q gets assiged D At all other times, Q is uchaged 45

46 The D Flip-Flop How do we implemet this? D CLK Q We ca use these Flip-Flops D Flip-Flop to implemet the state register! CLK: At the risig edge of clock (clock goig from 0->1), Q gets assiged D At all other times, Q is uchaged 1 0 Q 46

47 Risig-Edge Triggered Flip-Flop Two iputs: CLK, D Fuctio The flip-flop samples D o the risig edge of CLK (positive edge) Whe CLK rises from 0 to 1, D passes through to Q Otherwise, Q holds its previous value Q chages oly o the risig edge of CLK D Flip-Flop CLKSymbols D Q Q A flip-flop is called a edge-triggered device because it is activated o the clock edge 47

48 Register Multiple parallel flip-flops, each of which store 1 bit CLK D 0 D Q Q 0 CLK D 1 D Q Q 1 D 3:0 4 4 Q 3:0 D 2 D Q Q 2 This lie represets 4 wires D 3 D Q Q 3 This register stores 4 bits 48

49 Fiite State Machies (FSMs) Next state is determied by the curret state ad the iputs Two types of fiite state machies differ i the output logic: Moore FSM: outputs deped oly o the curret state Moore FSM iputs M ext state logic k ext state CLK k state output logic N outputs Mealy FSM iputs M ext state logic k ext state CLK k state output logic N outputs 49

50 Fiite State Machies (FSMs) Next state is determied by the curret state ad the iputs Two types of fiite state machies differ i the output logic: Moore FSM: outputs deped oly o the curret state Mealy FSM: outputs deped o the curret state ad the iputs Moore FSM iputs M ext state logic k ext state CLK k state output logic N outputs Mealy FSM iputs M ext state logic k ext state CLK k state output logic N outputs 50

51 Fiite State Machie Example Smart traffic light cotroller 2 iputs: Traffic sesors: T A, T B (TRUE whe there s traffic) 2 outputs: Lights:, (Red, Yellow, Gree) Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms 51

52 Fiite State Machie Black Box Iputs: CLK, Reset, T A, T B Outputs:, CLK T A T B Traffic Light Cotroller Reset 52

53 Fiite State Machie Trasitio Diagram Moore FSM: outputs labeled i each state States: Circles Trasitios: Arcs Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms Reset S0 : gree 53

54 Fiite State Machie Trasitio Diagram Moore FSM: outputs labeled i each state States: Circles Trasitios: Arcs Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms Reset S0 : gree S3 : yellow T A TA T B T B S1 : yellow S2 : gree 54

55 Fiite State Machie Trasitio Diagram Moore FSM: outputs labeled i each state States: Circles Trasitios: Arcs Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms Reset S0 : gree S3 : yellow T A TA T B T B S1 : yellow S2 : gree 55

56 Fiite State Machie Trasitio Diagram Moore FSM: outputs labeled i each state States: Circles Trasitios: Arcs Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms Reset S0 : gree S3 : yellow T A TA T B T B S1 : yellow S2 : gree 56

57 Fiite State Machie Trasitio Diagram Moore FSM: outputs labeled i each state States: Circles Trasitios: Arcs Academic Labs T A Bravado Blvd. T B T B Diig Hall T A Fields Ave. Dorms Reset S0 : gree S3 : yellow T A TA T B T B S1 : yellow S2 : gree 57

58 Fiite State Machies State Trasitio Table 58

59 FSM State Trasitio Table Reset S0 : gree T A TA S1 : yellow Curret State Iputs Next State S T A T B S' S0 0 X S0 1 X S1 X X S2 X 0 S3 : yellow T B S2 : gree S2 X 1 S3 X X T B 59

60 FSM State Trasitio Table Reset S0 : gree T A TA S1 : yellow Curret State Iputs Next State S T A T B S' S0 0 X S1 S0 1 X S0 S1 X X S2 S2 X 0 S3 S3 : yellow T B S2 : gree S2 X 1 S2 S3 X X S0 T B 60

61 FSM State Trasitio Table Reset S0 : gree T A TA S1 : yellow Curret State Iputs Next State S T A T B S' S0 0 X S1 S0 1 X S0 S1 X X S2 S2 X 0 S3 S3 : yellow T B T B S2 : gree S2 X 1 S2 S3 X X S0 State Ecodig S0 00 S1 01 S2 10 S

62 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S1 01 S2 10 S

63 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S 1 =? S1 01 S2 10 S

64 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S 1 = (S 1 S 0 ) + (S 1 S 0 T B ) + (S 1 S 0 T B ) S1 01 S2 10 S

65 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S 1 = (S 1 S 0 ) + (S 1 S 0 T B ) + (S 1 S 0 T B ) S 0 =? S1 01 S2 10 S

66 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S 1 = (S 1 S 0 ) + (S 1 S 0 T B ) + (S 1 S 0 T B ) S 0 = (S 1 S 0 T A ) + (S 1 S 0 T B ) S1 01 S2 10 S

67 FSM State Trasitio Table Reset T A TA Curret State Iputs Next State S0 : gree S1 : yellow S 1 S 0 T A T B S 1 S X X X X X S3 : yellow S2 : gree 1 0 X X X 0 0 T B T B State Ecodig S0 00 S 1 = S 1 xor S 0 (Simplified) S 0 = (S 1 S 0 T A ) + (S 1 S 0 T B ) S1 01 S2 10 S

68 Fiite State Machies Output Table 68

69 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S gree red 0 1 yellow red 1 0 red gree 1 1 red yellow S3 : yellow S2 : gree T B T B 69

70 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S gree red 0 1 yellow red 1 0 red gree 1 1 red yellow S3 : yellow S2 : gree T B T B Output Ecodig gree 00 yellow 01 red 10 70

71 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S S3 : yellow S2 : gree T B T B Output Ecodig 1 = S 1 gree 00 yellow 01 red 10 71

72 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S S3 : yellow S2 : gree T B T B Output Ecodig 1 = S 1 0 = S 1 S 0 gree 00 yellow 01 red 10 72

73 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S S3 : yellow S2 : gree T B T B Output Ecodig 1 = S 1 0 = S 1 S 0 1 = S 1 gree 00 yellow 01 red 10 73

74 FSM Output Table Reset T A TA Curret State Outputs S0 : gree S1 : yellow S 1 S S3 : yellow T B T B S2 : gree Output Ecodig gree 00 1 = S 1 yellow 01 0 = S 1 S 0 L red 10 B1 = S 1 0 = S 1 S 0 74

75 Fiite State Machies Schematic 75

76 FSM Schematic: State Register 76

77 FSM Schematic: State Register CLK S' 1 S 1 S' 0 r Reset S 0 state register 77

78 FSM Schematic: Next State Logic CLK S' 1 S 1 T A T B S' 0 r Reset S 0 S 1 S 0 iputs ext state logic state register S 1 = S 1 xor S 0 S 0 = (S 1 S 0 T A ) + (S 1 S 0 T B ) 78

79 FSM Schematic: Output Logic CLK 1 S' 1 S 1 0 T A S' 0 r S 0 1 T B Reset S 1 S 0 0 iputs ext state logic state register output logic outputs 1 = S 1 0 = S 1 S 0 1 = S 1 0 = S 1 S 0 79

80 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 80

81 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 81

82 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 82

83 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 83

84 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 84

85 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 85

86 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 86

87 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 87

88 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 88

89 FSM Timig Diagram Reset S0 : yellow T A T A S1 : yellow S3 : yellow T B TB S2 : gree Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) 1:0?? Gree (00) Yellow (01) Red (10) Gree (00) 1:0?? Red (10) Gree (00) Yellow (01) Red (10) t (sec) 89

90 FSM State Ecodig 3 commo state biary ecodigs with differet tradeoffs 1. Fully Ecoded 2. 1-Hot Ecoded 3. Output Ecoded Let s see a example Swiss traffic light with 4 states Gree, Yellow, Red, Yellow+Red 90

91 FSM State Ecodig 1. Fully Ecoded: Miimizes # flip-flops, but ot ecessarily output logic or ext state logic Use log 2 (um_states) bits to represet the states Example states: 00, 01, 10, Hot Ecoded: Maximizes # flip-flops, miimizes ext state logic Simplest desig process very automatable Use um_states bits to represet the states Example states: 0001, 0010, 0100,

92 FSM State Ecodig 3. Output Ecoded: Miimizes output logic Oly works for Moore Machies Each state has to be ecoded uiuely, but the outputs must be directly accessible i the state ecodig For example, sice we have 3 outputs (light color), ecode state with 3 bits, where each bit represets a color Example states: 001, 010, 100, 110 Bit 0 ecodes gree light output, Bit 1 ecodes yellow light output Bit 2 ecodes red light output 92

93 FSM State Ecodig 3. Output Ecoded: Miimizes output logic Oly works for Moore Machies Each state has to be ecoded uiuely, but the outputs must be directly accessible i the state ecodig For The example, desiger sice we must have carefully 3 outputs (light choose color), ecode state with 3 bits, where each bit represets a color Example states: uder 001, give 010, 100, costraits 110 a ecodig scheme to optimize the desig Bit 0 ecodes gree light output, Bit 1 ecodes yellow light output Bit 2 ecodes red light output 93

94 Moore vs. Mealy Machies 94

95 Moore vs. Mealy FSM Alyssa P. Hacker has a sail that crawls dow a paper tape with 1 s ad 0 s o it. The sail smiles wheever the last four digits it has crawled over are Desig Moore ad Mealy FSMs of the sail s brai. Moore FSM iputs M ext state logic k ext state CLK k state output logic N outputs Mealy FSM iputs M ext state logic k ext state CLK k state output logic N outputs 95

96 Moore vs. Mealy FSM Alyssa P. Hacker has a sail that crawls dow a paper tape with 1 s ad 0 s o it. The sail smiles wheever the last four digits it has crawled over are Desig Moore ad Mealy FSMs of the sail s brai. Moore FSM iputs M ext state logic k ext state CLK k state output logic N outputs Mealy FSM iputs M ext state logic k ext state CLK k state output logic N outputs 96

97 State Trasitio Diagrams Moore FSM 1 reset S0 0 0 S1 0 S2 0 S S4 1 Mealy FSM What are the tradeoffs? reset 1/0 1/0 0/0 1/1 0/0 S0 S1 S2 S3 0/0 1/0 0/0 97

98 FSM Desig Procedure Determie all possible states of your machie Develop a state trasitio diagram Geerally this is doe from a textual descriptio You eed to 1) determie the iputs ad outputs for each state ad 2) figure out how to get from oe state to aother Approach Start by defiig the reset state ad what happes from it this is typically a easy poit to start from The cotiue to add trasitios ad states Pickig good state ames is very importat Buildig a FSM is like programmig (but it is ot programmig!) A FSM has a seuetial cotrol-flow like a program with coditioals ad goto s The if-the-else costruct is cotrolled by oe or more iputs The outputs are cotrolled by the state or the iputs I hardware, we typically have may cocurret FSMs 98

99 Implemetig Seuetial Logic Usig Verilog 99

100 Verilog: Last Week vs. This Week We have see a overview of Verilog Discussed structural ad behavioral modelig Showed combiatioal logic costructs This week Seuetial logic costructs i Verilog Developig testbeches for simulatio 100

101 Combiatioal + Memory = Seuetial Seuetial Circuit iputs Combiatioal Circuit outputs Storage Elemet 101

102 Seuetial Logic i Verilog Defie blocks that have memory Flip-Flops, Latches, Fiite State Machies Seuetial Logic state trasitio is triggered by a CLOCK evet Latches are sesitive to level of the sigal Flip-flops are sesitive to the trasitioig of clock Combiatioal costructs are ot sufficiet We eed ew costructs: always posedge/egedge 102

103 The always Block (sesitivity list) statemet; Wheever the evet i the sesitivity list occurs, the statemet is executed 103

104 Example: D Flip-Flop module flop(iput clk, iput [3:0] d, output reg [3:0] ); (posedge clk) <= d; // proouced gets d edmodule posedge defies a risig edge (trasitio from 0 to 1). Statemet executed whe the clk sigal rises (posedge of clk) Oce the clk sigal rises: the value of d is copied to 104

105 Example: D Flip-Flop module flop(iput clk, iput [3:0] d, output reg [3:0] ); (posedge clk) <= d; // proouced gets d edmodule assig statemet is ot used withi a always block <= describes a o-blockig assigmet We will see the differece betwee blockig assigmet ad o-blockig assigmet soo 105

106 Example: D Flip-Flop module flop(iput clk, iput [3:0] d, output reg [3:0] ); (posedge clk) <= d; // proouced gets d edmodule Assiged variables eed to be declared as reg The ame reg does ot ecessarily mea that the value is a register (It could be, but it does ot have to be) We will see examples later 106

107 Asychroous ad Sychroous Reset Reset sigals are used to iitialize the hardware to a kow state Usually activated at system start (o power up) Asychroous Reset The reset sigal is sampled idepedet of the clock Reset gets the highest priority Sesitive to glitches, may have metastability issues Will be discussed i Lecture 8 Sychroous Reset The reset sigal is sampled with respect to the clock The reset should be active log eough to get sampled at the clock edge Results i completely sychroous circuit 107

108 D Flip-Flop with Asychroous Reset module flop_ar (iput clk, iput reset, iput [3:0] d, output reg [3:0] ); (posedge clk, egedge reset) begi if (reset == 0) <= 0; // whe reset else <= d; // whe clk ed edmodule I this example: two evets ca trigger the process: A risig edge o clk A fallig edge o reset 108

109 D Flip-Flop with Asychroous Reset module flop_ar (iput clk, iput reset, iput [3:0] d, output reg [3:0] ); (posedge clk, egedge reset) begi if (reset == 0) <= 0; // whe reset else <= d; // whe clk ed edmodule For loger statemets, a begi-ed pair ca be used To improve readability I this example, it was ot ecessary, but it is a good idea 109

110 D Flip-Flop with Asychroous Reset module flop_ar (iput clk, iput reset, iput [3:0] d, output reg [3:0] ); (posedge clk, egedge reset) begi if (reset == 0) <= 0; // whe reset else <= d; // whe clk ed edmodule First reset is checked: if reset is 0, is set to 0. This is a asychroous reset as the reset ca happe idepedetly of the clock (o the egative edge of reset sigal) If there is o reset, the regular assigmet takes effect 110

111 D Flip-Flop with Sychroous Reset module flop_sr (iput clk, iput reset, iput [3:0] d, output reg [3:0] ); (posedge clk) begi if (reset == 0 ) <= 0; // whe reset else <= d; // whe clk ed edmodule The process is oly sesitive to clock Reset happes oly whe the clock rises. This is a sychroous reset 111

112 D Flip-Flop with Eable ad Reset module flop_e_ar (iput clk, iput reset, iput e, iput [3:0] d, output reg [3:0] ); (posedge clk, egedge reset) begi if (reset == 0 ) <= 0; // whe reset else if (e) <= d; // whe e AND clk ed edmodule A flip-flop with eable ad reset Note that the e sigal is ot i the sesitivity list gets d oly whe clk is risig ad e is 1 112

113 Example: D Latch module latch (iput clk, iput [3:0] d, output reg [3:0] ); (clk, d) if (clk) <= d; edmodule // latch is trasparet whe // clock is 1 113

114 Summary: Seuetial Statemets So Far Seuetial statemets are withi a always block The seuetial block is triggered with a chage i the sesitivity list Sigals assiged withi a always must be declared as reg We use <= for (o-blockig) assigmets ad do ot use assig withi the always block. 114

115 Basics of always Blocks module example (iput clk, iput [3:0] d, output reg [3:0] ); wire [3:0] ormal; // stadard wire reg [3:0] special; // assiged i always (posedge clk) special <= d; // first FF array assig ormal = ~ special; // simple assigmet (posedge clk) <= ormal; edmodule // secod FF array You ca have as may always blocks as eeded Assigmet to the same sigal i differet always blocks is ot allowed! 115

116 Why Does a always Block Memorize? module flop (iput clk, iput [3:0] d, output reg [3:0] ); (posedge clk) begi <= d; // whe clk rises copy d to ed edmodule This statemet describes what happes to sigal but what happes whe the clock is ot risig? The value of is preserved (memorized) 116

117 A always Block Does NOT Always Memorize module comb (iput iv, iput [3:0] data, output reg [3:0] result); (iv, data) // trigger with iv, data if (iv) result <= ~data;// result is iverted data else result <= data; // result is data edmodule This statemet describes what happes to sigal result Whe iv is 1, result is ~data Whe iv is ot 1, result is data The circuit is combiatioal (o memory) result is assiged a value i all cases of the if.. else block, always 117

118 always Blocks for Combiatioal Circuits A always block defies combiatioal logic if: All outputs are always (cotiuously) updated 1. All right-had side sigals are i the sesitivity list You ca use for short 2. All left-had side sigals get assiged i every possible coditio of if.. else ad case blocks It is easy to make mistakes ad uitetioally describe memorizig elemets (latches) Vivado will most likely war you. Make sure you check the warig messages Always blocks allow powerful combiatioal logic statemets if.. else case 118

119 Seuetial or Combiatioal? wire eable, data; reg out_a, out_b; (*) begi out_a = 1 b0; if(eable) begi out_a = data; out_b = data; ed ed No assigmet for ~eable wire eable, data; reg out_a, out_b; (data) begi out_a = 1 b0; out_b = 1 b0; if(eable) begi out_a = data; out_b = data; ed ed Not i the sesitivity list Seuetial Seuetial 119

120 The always Block is NOT Always Practical/Nice reg [31:0] result; wire [31:0] a, b, comb; wire sel, (a, b, sel) // trigger with a, b, sel if (sel) result <= a; // result is a else result <= b; // result is b assig comb = sel? a : b; Both statemets describe the same multiplexer I this case, the always block is more work 120

121 always Block for Case Statemets (Hady!) module sevesegmet (iput [3:0] data, output reg [6:0] segmets); ( * ) case (data) // * is short for all sigals // case statemet 4'd0: segmets = 7'b111_1110; // whe data is 0 4'd1: segmets = 7'b011_0000; // whe data is 1 4'd2: segmets = 7'b110_1101; 4'd3: segmets = 7'b111_1001; 4'd4: segmets = 7'b011_0011; 4'd5: segmets = 7'b101_1011; // etc etc default: segmets = 7'b000_0000; // reuired edcase edmodule 121

122 Summary: always Block If.. else ca oly be used i always blocks The always block is combiatioal oly if all regs withi the block are always assiged to a sigal Use the default case to make sure you do ot forget a uimplemeted case, which may otherwise result i a latch Use casex statemet to be able to check for do t cares 122

123 No-Blockig ad Blockig Assigmets No-blockig (<=) Blockig (=) (a) (a) begi begi a <= 2 b01; a = 2 b01; b <= a; // a is 2 b01 // all assigmets are made here b = a; // b is ot (yet) 2 b01 // b is ow 2 b01 as well ed ed All assigmets are made at the ed of the block Each assigmet is made immediately All assigmets are made i parallel, process flow is ot-blocked Process waits util the first assigmet is complete, it blocks progress 123

124 Why use (No)-Blockig Statemets There are techical reasos why both are reuired It is out of the scope of this course to discuss these Blockig statemets allow seuetial descriptios More like a programmig laguage If the sesitivity list is correct, blocks with o-blockig statemets will always evaluate to the same result This may reuire some additioal iteratios 124

125 Example: Blockig Assigmet Assume all iputs are iitially 0 ( * ) begi p = a ^ b ; // p = 0 g = a & b ; // g = 0 s = p ^ ci ; // s = 0 cout = g (p & ci) ; // cout = 0 ed If a chages to 1 All values are updated i order 125

126 The Same Example: No-Blockig Assigmet Assume all iputs are iitially 0 ( * ) begi p <= a ^ b ; // p = 0 g <= a & b ; // g = 0 s <= p ^ ci ; // s = 0 cout <= g (p & ci) ; // cout = 0 ed If a chages to 1 All assigmets are cocurret Whe s is beig assiged, p is still 0 126

127 The Same Example: No-Blockig Assigmet After the first iteratio, p has chaged to 1 as well ( * ) begi p <= a ^ b ; // p = 1 g <= a & b ; // g = 0 s <= p ^ ci ; // s = 0 cout <= g (p & ci) ; // cout = 0 ed Sice there is a chage i p, the process triggers agai This time s is calculated with p=1 127

128 Rules for Sigal Assigmet Use clk) ad o-blockig assigmets (<=) to model sychroous seuetial logic (posedge clk) <= d; // o-blockig Use cotiuous assigmets (assig) to model simple combiatioal logic. assig y = a & b; 128

129 Rules for Sigal Assigmet (Cot.) Use (*) ad blockig assigmets (=) to model more complicated combiatioal logic. You caot make assigmets to the same sigal i more tha oe always block or i a cotiuous assigmet (*) a = b; (*) a = b; (*) a = c; assig a = c; 129

130 Recall: Fiite State Machies (FSMs) Each FSM cosists of three separate parts: ext state logic state register output logic CLK iputs M ext state logic k ext state k state output logic N outputs state register 130

131 Recall: Fiite State Machies (FSMs) Comprise Seuetial circuits State register(s) Store the curret state ad Load the ext state at the clock edge Next State CLK S S Curret State Combiatioal Circuits Next state logic Determies what the ext state will be Next State Logic C L Next State Output logic Geerates the outputs Output Logic C L Outputs 131

132 FSM Example 1: Divide the Clock Freuecy by 3 The output Y is HIGH for oe clock cycle out of every 3. I other words, the output divides the freuecy of the clock by

133 Implemetig FSM Example 1: Defiitios module divideby3fsm (iput clk, iput reset, output ); reg [1:0] state, extstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; We defie state ad extstate as 2-bit reg The parameter descriptios are optioal, it makes readig easier 133

134 Implemetig FSM Example 1: State Register CLK S S Next State Curret State // state register (posedge clk, posedge reset) if (reset) state <= S0; else state <= extstate; This part defies the state register (memorizig process) Sesitive to oly clk, reset I this example, reset is active whe it is 1 (active-high) 134

135 Implemetig FSM Example 1: Next State Logic iputs CLK M ext k ext k state logic state state // ext state logic (*) case (state) S0: extstate = S1; S1: extstate = S2; S2: extstate = S0; default: extstate = S0; edcase 135

136 Implemetig FSM Example 1: Output Logic CLK iputs M ext state logic k ext state k state output logic N outputs // output logic assig = (state == S0); I this example, output depeds oly o state Moore type FSM 136

137 Implemetatio of FSM Example 1 module divideby3fsm (iput clk, iput reset, output ); reg [1:0] state, extstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; (posedge clk, posedge reset) // state register if (reset) state <= S0; else state <= extstate; (*) case (state) S0: extstate = S1; S1: extstate = S2; S2: extstate = S0; default: extstate = S0; edcase assig = (state == S0); edmodule // ext state logic // output logic 137

138 FSM Example 2: Smilig Sail Alyssa P. Hacker has a sail that crawls dow a paper tape with 1 s ad 0 s o it. The sail smiles wheever the last four digits it has crawled over are Desig Moore ad Mealy FSMs of the sail s brai. Moore Mealy 138

139 We did ot cover the followig. They are for your preparatio. 139

140 Implemetig FSM Example 2: Defiitios module SmiligSail (iput clk, iput reset, iput umber, output smile); reg [1:0] state, extstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2 b11; umber/smile 140

141 Implemetig FSM Example 2: State Register // state register (posedge clk, posedge reset) if (reset) state <= S0; else state <= extstate; This part defies the state register (memorizig process) Sesitive to oly clk, reset I this example reset is active whe 1 (active-high) 141

142 Implemetig FSM Example 2: Next State Logic // ext state logic (*) case (state) S0: if (umber) extstate = S1; else extstate = S0; S1: if (umber) extstate = S2; else extstate = S0; S2: if (umber) extstate = S2; else extstate = S3; S3: if (umber) extstate = S1; else extstate = S0; default: extstate = S0; edcase 142

143 Implemetig FSM Example 2: Output Logic // output logic assig smile = (umber & state == S3); I this example, output depeds o state ad iput Mealy type FSM We used a simple combiatioal assigmet 143

144 Implemetatio of FSM Example 2 module SmiligSail (iput clk, reg iput reset, iput umber, output smile); [1:0] state, extstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2 b11; // state register (posedge clk, posedge reset) if (reset) state <= S0; else state <= extstate; (*) // ext state logic case (state) S0: if (umber) extstate = S1; else extstate = S0; S1: if (umber) extstate = S2; else extstate = S0; S2: if (umber) extstate = S2; else extstate = S3; S3: if (umber) extstate = S1; else extstate = S0; default: extstate = S0; edcase // output logic assig smile = (umber & state==s3); edmodule 144

145 What Did We Lear? Basics of defiig seuetial circuits i Verilog The always statemet Needed for defiig memorizig elemets (flip-flops, latches) Ca also be used to defie combiatioal circuits Blockig vs No-blockig statemets = assigs the value immediately <= assigs the value at the ed of the block Writig FSMs Next state logic State assigmet Output logic 145

146 Next Lecture: Timig ad Verificatio 146

147 Desig of Digital Circuits Lecture 7: Seuetial Logic Desig Prof. Our Mutlu ETH Zurich Sprig March 2018

148 Backup Slides Differet types of flip flops 148

149 The D Flip-Flop 149

150 Eabled Flip-Flops Iputs: CLK, D, EN The eable iput (EN) cotrols whe ew data (D) is stored Fuctio: EN = 1: D passes through to Q o the clock edge EN = 0: the flip-flop retais its previous state Iteral Circuit Symbol EN CLK D 0 1 D Q Q D EN Q 150

151 Resettable Flip-Flop Iputs: CLK, D, Reset The Reset is used to set the output to 0. Fuctio: Reset = 1: Q is forced to 0 Reset = 0: the flip-flop behaves like a ordiary D flip-flop Symbols D Reset Q r 151

152 Resettable Flip-Flops Two types: Sychroous: resets at the clock edge oly Asychroous: resets immediately whe Reset = 1 Asychroously resettable flip-flop reuires chagig the iteral circuitry of the flip-flop (see Exercise 3.10) Sychroously resettable flip-flop? Iteral Circuit CLK D Reset D Q Q 152

153 Settable Flip-Flop Iputs: CLK, D, Set Fuctio: Set = 1: Q is set to 1 Set = 0: the flip-flop behaves like a ordiary D flip-flop Symbols D Set Q s 153