CHAPTER XI DATAPATH ELEMENTS

Transcription

1 CHAPTER XI- CHAPTER XI CHAPTER XI READ REE-DOC ON COURSE WEBPAGE

2 CHAPTER XI-2 INTRODUCTION -INTRODUCTION So far we have discussed may small compoets ad buildig blocks. Oe fial step i our buildig blocks before we ca start to piece together a microprocessor is various datapath elemets. We have already discussed portios of these datapath elemets i terms of other compoets ad buildig blocks. We will ow cosider some of these compoets ad buildig blocks i ways that will make the desig of a microprocessor a little easier i the ext chapter.

3 CHAPTER XI-3 REGISTER ILES REGISTER LAYOUT -INTRODUCTION A geeral m register file with m registers that are each -bits wide is illustrated below. Data I Register 0 Data Out w 0 Register r 0 w r Register m - w m r m r k w j The ad sigals idicate which register to read/write, respectively.

4 CHAPTER XI-4 REGISTER ILES WRITE DECODER REGISTER ILES -REGISTER LAYOUT or writig to a register, we iclude a write address with decoder. Write Address Write Eable Data I Decoder 0 m- w 0 w Register 0 Register Register m - r 0 r Data Out w m r m A give Write Address (with Write Eable = ) selects which register, 0 through m -, to store the iput from Data I.

5 CHAPTER XI-5 REGISTER ILES READ DECODER REGISTER ILES -REGISTER LAYOUT -WRITE DECODER or readig from a register, we iclude a read address with decoder. Data Data Register 0 I Out Read Address Read Eable Decoder 0 m- r 0 r r m w 0 w w m Register Register m - A give Read Address (with Read Eable = ) selects which register, 0 through m -, to read from ad output to Data Out. Could have multiple data outputs with multiple read address decoders.

6 CHAPTER XI-6 REGISTER ILES 32-BIT WORD, 32 REGISTERS REGISTER ILES -REGISTER LAYOUT -WRITE DECODER -READ DECODER or the upcomig datapath desigs i the ext chapter, we wat to have a 32x32 register file with oe write iput ad two read outputs. X ra - X read address Y ra - Y read address Z wa - Z write address X do - X data out Y do - Y data out Z di - Z data i rwe - register write eable Clk Z di Z wa X ra Y ra X do Y do Note: Two data outputs implemeted with two read address decoders. 32 rwe x32 register file 32 32

7 CHAPTER XI-7 ADDER/SUBTRACTOR GENERAL UNIT DIAGRAM REGISTER ILES -WRITE DECODER -READ DECODER -32X32 REGISTER ILE A -bit adder/subtractor uit is ofte illustrated as follows. Eable uit () or disable uit (0) A B adder/subtrator uit eable a s Select either additio (0) or subtractio () This uit would have full-adders iterally.

8 CHAPTER XI-8 ADDER/SUBTRACTOR OTHER UNIT SIGNALS REGISTER ILES ADDER/SUBTRACTOR -GENERAL UNIT DIAGRAM Other sigals ofte icluded with a adder/subtractor are show below. Carry-i or Borrow-i A C i eable C out Carry-out or Borrow-out a s B lags - Overflow - Negative (<0?) - Zero (=0?)

9 CHAPTER XI-9 LOGICAL UNIT INTRODUCTION REGISTER ILES ADDER/SUBTRACTOR -GENERAL UNIT DIAGRAM -OTHER UNIT SIGNALS A useful uit would be oe that ca take two -bit iputs ad perform some logical operatio betwee each of the bits to get a -bit output. or example, give the 8-bit values ad , we might wat to fid the bit-wise logical OR. bit-wise logical OR Or similarly, the bit-wise logical AND of the two 8-bit values. bit-wise logical AND These types of operatios are ofte used for maskig ad settig bits.

10 CHAPTER XI-0 LOGICAL UNIT GENERAL UNIT DIAGRAM REGISTER ILES ADDER/SUBTRACTOR LOGICAL UNIT -INTRODUCTION Below is a geeral uit diagram for a -bit logical uit. Eable uit () or disable uit (0) A logical uit eable L B 4 Logical uctio (L) o 2 bits Logical operatios, such as AND/OR/NOT/NAND/NOR/etc., are doe for each bit of A ad B to form.

11 CHAPTER XI- LOGICAL UNIT 4-BIT LOGICAL UNCTIONS (L) ADDER/SUBTRACTOR LOGICAL UNIT -INTRODUCTION -GENERAL UNIT DIAGRAM Recall the possible logic fuctios for two bits, A ad B. We ca use the colum as the 4-bit L iput for the logical uit. A B AB A B A + B B A AB Null A B A B Idetity Ihibitio A + B Implicatio

12 CHAPTER XI-2 LOGICAL UNIT BIT SLICE IMPLEMENTATION LOGICAL UNIT -INTRODUCTION -GENERAL UNIT DIAGRAM -4-BIT LOGICAL UNCTIONS A umber of iteral implemetatios exist for the logical uit. The easiest is to use a 4-to- multiplexer for each bit as follows Take colum from previous slide as L iput L 0 L L 2 L 3 Module Eable E 4X MULTIPLEXER S S 0 A B Require of these to form our -bit logical uit. Note: Whe you look at a desig for each bit, it is kow as a bit slice

13 CHAPTER XI-3 LOGICAL UNIT BIT SLICE IMPLEMENTATION LOGICAL UNIT -GENERAL UNIT DIAGRAM -4-BIT LOGICAL UNCTIONS -BIT SLICE IMPLEMENTAT. The followig are example L iputs for a logical uit bit slice. OR fuctio Module Eable E NAND fuctio Module Eable E A+ B X MULTIPLEXER AB X MULTIPLEXER S S 0 S S 0 A B A B

14 CHAPTER XI-4 SHIT UNIT INTRODUCTION LOGICAL UNIT -GENERAL UNIT DIAGRAM -4-BIT LOGICAL UNCTIONS -BIT SLICE IMPLEMENTAT. We have already discussed the bulk about shift uits i previous chapters. As give i the ree-doc, there are differet types of shift uits. Logical shift Arithmetic shift Circular shift (this is just a rotate uit) We wat to discuss a implemetatio, the barrel shifter, that will be useful i our sigle cycle datapath computer we will desig ext chapter.

15 CHAPTER XI-5 SHIT UNIT GENERAL UNIT DIAGRAM LOGICAL UNIT SHIT UNIT -INTRODUCTION Below is a geeral uit diagram for a -bit shift uit. -bit value to shift Eable uit () or disable uit (0) A shift uit eable +log 2 Notice that the -bit value A will be shifted accordig to the distace idicated with siged umber B. ST B 2 Distace of shift (siged #) + ive = right - ive = left Shift type 0 = logical = arithmetic 2 = rotate

16 CHAPTER XI-6 SHIT UNIT P-SHITER BIT SLICE LOGICAL UNIT SHIT UNIT -INTRODUCTION -GENERAL UNIT DIAGRAM Previously, we discussed the p-shifter but ot its implemetatio. A p-shifter shifts the value to the left or right by p-bits. A bit slice view of a p-shifter for th bit could be as follows. A +p s d S S 0 3 A -p A s 0 = o shift = shift 2 0 4X MULTIPLEXER E Notice that this ca ONLY shift by p-bits. It is hardwired to shift p-bits. Module Eable d 0 = left = right

17 CHAPTER XI-7 SHIT UNIT 2 K -SHITER BIT SLICE SHIT UNIT -INTRODUCTION -GENERAL UNIT DIAGRAM -P-SHITER BIT SLICE A useful type of p-shifter is whe p = 2 k for some positive iteger k. s d A +2 k S S 0 3 A -2 k 2 0 4X MULTIPLEXER A E Module Eable s 0 = o shift = shift d 0 = left = right A 2 k -shifter allows use to build a barrel shifter.

18 CHAPTER XI-8 SHIT UNIT BARREL SHITER SHIT UNIT -GENERAL UNIT DIAGRAM -P-SHITER BIT SLICE -2 K -SHITER BIT SLICE We wat to be able to shift a vector by a arbitrary distace istead of hardwired like the p-shifter ad 2 k -shifter. The top level ca shift A by bits, depedig o s. Subsequet levels ca shift result by /2 bits, depedig o their iput s q. s d s s 0 A 2 -shifter 2 -shifter 2 0 -shifter

19 CHAPTER XI-9 SHIT UNIT SAMPLE BARREL SHITER SHIT UNIT -P-SHITER BIT SLICE -2 K -SHITER BIT SLICE -BARREL SHITER We will do some examples with the followig arbitrary -shifter o a 6-bit iput. Note that this barrel shifter ca shift the iput by 5 bits i either directio. s 3 d A 6 s 2 6 s s shifter 2 2 -shifter 6 2 -shifter shifter 6

20 CHAPTER XI-20 SHIT UNIT BARREL SHITER: EXAMPLE # SHIT UNIT -2 K -SHITER BIT SLICE -BARREL SHITER -SAMPLE BARREL SHITER or example, cosider the iput of If we wat to shift this value to the left by 3, we eed the iput d = 0 s = (s 3 s 2 s s 0 ) = 0 Note: This example is for a logical shift. s 3 = d=0 s 2 = s =0 s 0 = shifter shifter shifter shifter

21 CHAPTER XI-2 SHIT UNIT BARREL SHITER: EXAMPLE #2 SHIT UNIT -BARREL SHITER -SAMPLE BARREL SHITER -BARREL SHITER EX. # As aother example, cosider the iput of If we wat to shift this value to the right by 6, we eed the iput d = s = (s 3 s 2 s s 0 ) = 00 Note: This example is for a logical shift. s 3 =0 d= s 2 = s = s 0 = shifter shifter shifter shifter