Generic datapath. Generic datapath architecture. Register file. Register file. Calcolatori Elettronici e Sistemi Operativi.

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1 alcolatori Elettroici e Sistei Operativi Geeric datapath architecture Set of registers Geeric datapath uber, size. addressig R[0], R[1],... Set of operatios arithetic, logic, shift Addressig (uber of operads, uber of results) R[1] <= R[2] op 1 R[3] op 2 R[4] ; R[5] <= R[6] op 3 R[7] R[1] <= R[2] op 1 R[3] Register file Register file D addr_a 4 addr_a 3 D addr_a 2 addr_a 2 R0 addr_a 1 R0 addr_a 1 R1 R1 addr_d DEO R2 4 registers 4 operads 1 result addr_d DEO R2 4 registers 2 operads 1 result write_d R3 write_d R3 A 1 A 2 A 3 A 4 A 1 A 2

2 Register file Fuctio uit Other possible requireets: differet sizes for data store oly load a portio of destiatio register(s) o-uifor register addressig soe register ca have soe other data source Operatios Arithetic su, subtractio,... Logic ad, or, ot, xor,... Shifter Flags typical: : zero : carry : egative : overflow ALU Fuctio uit Fuctio uit ALU vs shifter selectio: MUXF Shifter aout ecodig H1:H0 Op operatio aout ALU Shifter i o shift: 00 right: 01 left: 10 Op Shifter H1:H0 flags MUXF MF

3 Fuctio uit Fuctio uit ALU Logic Arithetic vs Logic selectio: MUXG Aoperatio Loperatio Arith Logic i operatio ecodig L1:L0 ad: 00 or: 01 xor: 10 ot: 11 (ot ) (i) (i) flags:,, MUXG MG L1:L0 =0 (i) Fuctio uit Fuctio uit Arithetic Operatio operatio ecodig A1:A0 o-op: 00 : 01 : 10-1: 11 i out A1:A0 F=0: ALU operatio G=0: Arithetic operatio A1:A0: i 000: = (o operatio) 001: = : = 011: = : = 101: = + 1 = - 110: = : = =

4 Fuctio uit Fuctio uit Operatio F=0: ALU operatio G=1: Logic operatio L1:L0:0 000: = ad 010: = or Operatio F=1: Shifter operatio S1:S0:0: : = 10100: = >> : = << 1 100: = xor 110: = Fuctio uit Datapath structure Other possible requireets: several cocurret operatios paired with ulti-operads ulti-destiatio register file special register to store flags evetually with coditioal storig shiftig applied to soe source operads ulti-operatios e.g., ultiply-accuulate addr_d addr_a 2 write_d addr_a 1 Register D A 1 file A 2 A B Fuctio uit AA BA operatio otrol sigals operad selectio AA, BA destiatio selectio result storig operatio Status sigals flags,,,

5 Datapath structure Datapath structure Other requireets exteral eory access eory address addr_d addr_a 2 write_d addr_a 1 Register D A 1 file A 2 AA BA ostat_i bus A eory datai bus B eory dataout fro eory to register file ultiplexer (MUXD) usig a costat as a operad choose betwee register file data ad exteral costat ultiplexer (MUXB) A Fuctio uit MUXB MB B operatio MUXD MD Me_Address Me_Datai Me_Dataout Operatio exaple Datapath structure R0 <= R1 + R2 AA: 01 - first operad: R1 BA: 10 - secod operad: R2 MB: 0 - use exteral costat: O : MF=0 (ALU) ; MG=0 (arith) ; A1:A0: i = 010 ( ) MD: 0 - use data fro eory: O : 00 - destiatio register: R0 : 1 - write result: YES A arith R0 R1 R2 R3 logic AA BA MUXB MB B shifter ostat_i Me_Address Me_Datai Me_Dataout MUXD MD

6 Operatio exaple Datapath structure R3 <= R2 << 1 AA: 00 - first operad: R0 (do't care) BA: 10 - secod operad: R2 MB: 0 - use exteral costat: O : MF=1 (shifter) ; S1:S0 = 10 ( << 1) MD: 0 - use data fro eory: O : 11 - destiatio register: R3 : 1 - write result: YES A arith R0 R1 R2 R3 logic AA BA MUXB MB B shifter ostat_i Me_Address Me_Datai Me_Dataout MUXD MD otrol Word Operatio exaples AA BA MB MD Operatio otrol Word AA BA MB MD : selectio of the destiatio register AA: selectio of the source register for bus A BA: selectio of the source register for bus B MB: selectio for MUX B : operatio for the fuctioal uit MD:selectio for MUX D :result storig eable operatio F = A F = A F = A+B F = A+B F = A-B F = A-B F = A F = A F = A B F = A B F = A B F = A F = B F = B >> F = B << 1 R1 <= R2+R R1 <= R2-R R0 <= R0 xor R R0 <= sr R R2 <= R R2 <= R R1 <= R1 xor R1 R1 <= ext_cost R1==R2? R1 R2 R3 <= M[R2] M[R2] <= R R3,M[R2]<=R

7 Pipelie Pipelie Register File Fuctio Uit MUX B LK 2 s 3 s 1 s 5 s WB OF EX Register File Fuctio Uit MUX B LK 2 s 3 s 1 s 1 s 1 s 5 s R1 <- R2 - R3 R4 <- sl R6 R7 <- R7 + 1 R1 <- R0 +2 Dout <- R3 R4 <- Di R5 <- 0 clock cycle MUX D 1 s WB MUX D 1 s 1 s 1 s Executio tie: o pipelie: 7*12 s = 84 s pipelie: 9*7 s = 63 s ycle tie MAX(5,7,4) s = 7 s Tiig optiizatios Tiig optiizatios Retiig T LK T RO + MAX(T R1, T R2 ) + T RSU Pipeliig R 1 R 2 D R Q R A T LK T RO + T R + T RSU R B R 1 ' R 1 R 2 T LK T RO + MAX(T R1', T R1 +T R2 ) + T RSU D R1 R2 R3 Q R 1 ' R 1 R 2 R A R 1 R 2 R B T LK T RO + MAX(T R1, T R2, T R3 ) + T RSU

8 Tiig optiizatios Pipeliig RA R1 R2 R3 ycle-0 D(0) ycle-1 D(1) R1(D(0)) ycle-2 D(2) R1(D(1)) R2(R1(D(0))) ycle-3 D(3) R1(D(2)) R2(R1(D(1))) R3(R2(R1(D(0)))) ycle-4 D(4) R1(D(3)) R2(R1(D(2))) R3(R2(R1(D(1)))) ycle-5 D(5) R1(D(4)) R2(R1(D(3))) R3(R2(R1(D(2)))) ycle-6 R1(D(5)) R2(R1(D(4))) R3(R2(R1(D(3)))) ycle-7 R2(R1(D(5))) R3(R2(R1(D(4)))) ycle-7 R3(R2(R1(D(5)))) otrol requires additioal state to load ad to dup the pipelie

Chapter 9 Computer Design Basics

Chapter 9 Computer Design Basics Logic ad Computer Desig Fudametals Chapter 9 Computer Desig Basics Part 1 Datapaths Overview Part 1 Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio Cotrol