Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle
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1 Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle
2 Introduction The 5 classic components of a computer Processor Input Control Memory Datapath Output Chapter 4 discusses the processor Part-a: Datapath Part-b: Control 2
3 Review: Edge-triggered Methodology Input: Values written in a previous clock cycle Output: Values to be used in the following clock cycle Prevents reading the signal in the same time it is written More than one action can take place in the same clock cycle Falling edge Clock period Rising edge 3
4 Review: Timing Methodology Clock cycle(tick/period): Time for one clock period, usually of the processor, which runs at a constant rate Memory Access time: Time between the initiation of a read request and when the desired word arrives Memory Cycle time: Minimum time between requests to memory Should be greater than access time to keep address line stable between accesses 4
5 Review: Timing Methodology Typical execution cycle: Read contents of some state elements, Send values through some combinational logic Write results to one or more state elements Clock period should cover all these activities All signals must propagate from state element1 to state element2 in the time of one clock cycle If the state element is not updated on every clock, an explicit write control signal is required, in which case the state element is changed only when the control signal is asserted and the clock edge occurs 5
6 Review: Timing Methodology Edge triggered methodology allows a state element to be read and written in the same clock cycle The clock must be long enough to allow the stability of input value before the active edge occurs 6
7 Building the Datapath 7
8 Review: 2 x 1 MUX MUX Operation: Selects one of the (A or B) inputs to be the output, based on a control (select) input (S) We need a 2x1 MUX The MUX has 3 inputs Equivalent C-Operation If (s == 0) C:= A; else C = B; A B 0 1 (s) Selector C 8
9 Universal ALU Symbolic representation: (Sometimes used to represent adders as well) Operation a 32 C in to LSB Zero Flag ALU 32 Result b 32 C out from MSB Overflow Flag 9
10 Building the Datapath The major components required to execute each class of MIPS instructions? A memory unit to store the instructions PC to store the address of the current instruction Adder to increment PC to address of next instruction 10
11 Building the Datapath How are these components connected? 11
12 Building the Datapath The major components required to execute R-Format instructions add, sub, and, or, slt Three register operands Two read ports to read two registers from register file One write port to write into one register Data lines 32-bit Register lines ALUOp 12
13 Review: Register File A set of 32 registers 5-inputs 2 read-ports to supply source register numbers 1 write-port to supply destination register number 1 Data bus 1 Register write enable control signal 2-outputs Data from register 1 Data from register 2 1-Control signal RegWrite No need to read-enable 13 Register Selectors Data Bus Read Reg1 Read Reg 2 Write Reg1 Read Data1 Register File Read Data2 Write Data Write Enable RegWrite Data Buses 13
14 Review: Reading from Register File Need to submit: Read register number 1 Register 0 Register # For N-registers we need: Register 1... Register n 2 Register n 1 M u x Read data 1 n x 1 MUX Read register number 2 M u x Read data
15 Review: Writing to Register File Need to submit: Write Register # Data Write control signal Register number n-to-2n decoder 0 1. C D C Register 0 To choose a register, use Decoder To determine when to write, use the clock n 1 n D C Register 1. Note: C means control signal D C Register n 2 D means data lines Register data D Register n 1 15
16 Building the Datapath (lw, sw) Instruction Read register 1 Read Read data 1 register 2 Registers Read Write data 2 register Write data RegWrite ALUSrc M ux 3 ALU operation Zero ALU ALU result Address Write data MemWrite MemtoReg Data memory Read data M ux 16 Sign 32 extend MemRead 16
17 Building the Datapath (beq) For branch instructions, two operations are needed Compare register contents ALU Zero signal returns the result of comparison Compute branch target address A sign-extend unit is required If branch is taken Branch target address becomes the new PC contents If branch is not taken PC+4 is the new value for PC 17
18 Review: MIPS Instruction Format R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 0 I-type op rs rt immediate 6 bits 5 bits 5 bits 16 bits 0 J-type op target address 6 bits 26 bits 0 18
19 Addressing Modes Register addressing Base or displacement addressing Immediate addressing PC-relative addressing Pseudo-direct addressing 19
20 Addressing Modes (1) Register addressing Operand is a register Value is the contents of the register 20
21 Building the Datapath R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 0 21
22 Addressing Modes Register addressing Base or displacement addressing Immediate addressing PC-relative addressing Pseudo-direct addressing 22
23 Addressing Modes (2) Base or displacement addressing Operand location = register + constant (offset) in the instruction 23
24 Building the Datapath (sw) 24
25 Building the Datapath (lw) 25
26 Building Datapath (R-type, lw, sw) Instruction Read register 1 Read data 1 Read register 2 Registers Read Write data 2 register Write data RegWrite ALUSrc M u x 3 ALU ALU operation Zero ALU result Address Write data MemWrite MemtoReg Data memory Read data M u x 16 Sign 32 extend MemRead 26
27 Building Datapath (R-type, lw, sw) 27
28 Datapath Operation for R-Format (add) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 0 Step1: Add $t1, $t2, $t3 Fetch instruction from instruction memory Increment program counter Step2: Decode result is Add operation Read two registers $t2 & $t3 from register file Step 3: ALU operates on data, using funct field code to generate the ALU function Step4: Write result of step 3 from ALU into register $t1 28
29 Datapath Operation for R-Format (add) Add $t1, $t2, $t3 (Fig. 5.19, p. 322) 29
30 Datapath Operation for R-Format (add) Step 1: Fetch instruction & increment PC 0 4 A d d I n s t r u c t i o n [ ] C o n t r o l R e g D s t B r a n c h M e m R e a d M e m t o R e g A L U O p M e m W r i t e A L U S r c R e g W r i t e S h i f t l e f t 2 A d d r e A s u L l U t M u x 1 P C R e a d a d d r e s s I n s t r u c t i o n m e m o r y I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ 15 1 ] I n s t r u c t i o n [ 15 0 ] 0 M u x 1 R e a d r e g i s t e r 1 R e a d d a t a 1 i s t e r 2 R e g i s t e r s R e a d d a t a 2 R e a d r e g W r i t e r e g i s t e r W r i t e d a t a 16 S i g n 32 e x t e n d 0 M u x 1 A L U c o n t r o l Z e r o A L U A L U r e s u l t A d d r e s s W r i t e d a t a D a t a m e m o r y R e a d d a t a 1 M u x 0 I n s t r u c t i o n [ 5 0 ] 30
31 Datapath Operation for R-Format (add) Step2: Read registers from register file 4 A d d I n s t r u c t i o n [ ] C o n t r o l R e g D s t B r a n c h M e m R e a d M e m t o R e g A L U O p M e m W r i t e A L U S r c R e g W r i t e S h i f t l e f t 2 A d d r e A s u L l U t 0 M u x 1 P C R e a d a d d r e s s I n s t r u c t i o n m e m o r y I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ 15 0 ] 0 M u x 1 R e a d r e g i s t e r 1 R e a d R e a d d a t a 1 r e g i s t e r 2 i R e g i s t e r s R e a d W r i t e d a t a 2 r e g i s t e r i W r i t e d a t a S i g n e x t e n d 0 M u x 1 A L U c o n t r o l Z e r o A L U A L U r e s u l t A d d r e s s W r i t e d a t a D a t a m e m o r y R e a d d a t a 1 M u x 0 I n s t r u c t i o n [ 5 0 ] 31
32 Datapath Operation for R-Format (add) Step 3: Perform ALU operation 0 4 A d d I n s t r u c t i o n [ ] C o n t r o l R e g D s t B r a n c h M e m R e a d M e m t o R e g A L U O p M e m W r i t e A L U S r c R e g W r i t e S h i f t l e f t 2 A d d A L U r e s u t M u x 1 P C R e a d a d d r e s s I n s t r u c t o n m e m o r y I n s r u c t o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ 15 1 ] I n s t r u c t i o n [ 15 0 ] 0 M u x 1 R e a d r e g i s t e r 1 R e a d R e a d d a t a 1 r e g i s t e r 2 R e g i s t e r s R e a d W r i e d a t a 2 r e g i s t e r W r i e d a t a 16 S i g n 32 e x t e n d 0 M u x 1 A L U c o n t r o l Z e r o A L U A L U r e s u l t A d d r e s s W r i t e d a t a R e a d d a t a D a t a m e m o r y 1 M u x 0 I n s t r u c t i o n [ 5 0 ] 32
33 Datapath Operation for R-Format (add) Step 4: Write result from ALU into register 4 A d d I n s t r u c t i o n [ ] C o n t r o l R e g D s t B r a n c h M e m R e a d M e m t o R e g A L U O p M e m W r i t e A L U S r c R e g W r i t e S h i f t l e f t 2 A d d r e A s u L l U t 0 M u x 1 P C R e a d a d d r e s s I n s t r u c t i o n m e m o r y I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ ] I n s t r u c t i o n [ 15 0 ] 0 M u x 1 R e a d r e g i s t e r 1 R e a d d a t a 1 i s t e r 2 R e g i s t e r s R e a d d a t a 2 R e a d r e g W r i t e r e g i s t e r W r i t e d a t a S i g n e x t e n d 0 M u x 1 A L U c o n t r o l Z e r o A L U A L U r e s u l t A d d r e s s W r i t e d a t a D a t a m e m o r y R e a d d a t a 1 M u x 0 I n s t r u c t i o n [ 5 0 ] 33
34 Datapath Operation for I-Format (lw) 31 Step 1: lw $t1, offset($t2) Fetch instruction from instruction memory Increment program counter Step 2: op rs rt/rd? offset 6 bits 5 bits 5 bits 16 bits Decode result is lw operation Read register $t2 from register file Step 3: ALU operates on data to build an address Compute sum of $t2 & sign-extended 16-bits (offset) of instruction Step 4: Retrieve data located in the calculate address from memory Step5: Write memory contents into destination register $t1 34
35 Datapath Operation for I-Format (lw) lw $t1, offset($t2) - Exercise: Highlight the steps! 35
36 Datapath Operation for I-Format (sw) sw $t1, 33($t2) Step 1: Fetch instruction from instruction memory Increment program counter Step 2: Decode result is sw operation Read register contents of $t1 and $t2 from register file Step 3: ALU operates on data to build an address Compute sum of $t2 & sign-extended 16-bits (offset) of instruction Step 4: Write data into the computed memory address 36
37 Datapath Operation for I-Format (sw) sw $t1, offset($t2) 37
38 Addressing Modes Register addressing Base or displacement addressing Immediate addressing PC-relative addressing Pseudo-direct addressing 38
39 Addressing Modes (3) Immediate addressing Operand is a constant within the instruction itself 39
40 Addressing Modes (4) PC-relative addressing Address = PC (program counter) + constant in the instruction 40
41 Branch instruction bne $t4,$t5,label # Next instruction is at Label if $t4 $t5 beq $t4,$t5,label # Next instruction is at Label if $t4 = $t5 Formats: I op rs rt 16 bit address Use Instruction Address Register (PC = program counter) 41
42 Datapath Operation for I-Format (beq) beq $t1, $t2, offset (Fig. 5.21, p. 311) Step 1: Fetch instruction from instruction memory Increment PC Step 2: Decode instruction result in beq Read contents of $t1, $t2 registers from register file Step 3: ALU subtract the two values from registers Add PC+4 to sign-extended lower 16-bits of offset Step 4: The zero result from ALU is used to decide which adder result to store into PC 42
43 Branch instruction 43
44 Branch instruction 44
45 Datapath Operation for (beq) beq $t1, $t2, offset 45
46 Datapath Operation for (beq) beq $t1, $t2, offset 46
47 Datapath Operation for (beq) beq $t1, $t2, offset 47
48 Datapath Operation for (beq) beq $t1, $t2, offset 48
49 Addressing Modes Register addressing Base or displacement addressing Immediate addressing PC-relative addressing Pseudo-direct addressing 49
50 Addressing Modes (5) Pseudo-direct addressing Jump address = 26 bits of the instruction + upper bits of the PC 50
51 Jump Instruction (J-Format) Jump instruction uses high order bits of PC address boundaries of 256 MB 2 target 6 bits 26 bits 4 bits 26 bits 2 PC 51
52 Jump Instruction (J-Format) 52
53 Datapath Operation for J-Format (j) j label Step 1: Fetch instruction from instruction memory Increment PC by 4 Step 2: Decode instruction result is j Retrieve value of jump target (label) Step 3: Shift the label 26 bits left by 2 bits (to get byte count instead of word count) Concatenate the upper 4 bits of PC +4 as the high-order bits (to get the complete memory address) Step 4: Store the calculated address into PC 53
54 Datapath Operation for J-Format 54
55 Datapath Operation for J-Format 55
56 Processor Design Control Signals Register selection: Rs, Rt, Rd and Imed16 hardwired into datapath Operation selection: ALU data source (register or immediate address) (ALUsrc) ALU Operation selection (ALUctr) Memory Write (MemWr) MemtoReg (1 => Mem) RegDst (0 => rt ; 1 => rd ) RegWr (write dest. register) 56
57 Processor Design Step 4 Control Unit Analyze implementation of each instruction to determine setting of control points Inst Memory Address Instruction<31:0> <21:25> Op Fun Rt <21:25> Rs <16:20> Rd <11:15> <0:15> Imm16 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH 57
58 Processor Design Control Signals needed by each instruction: inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc=R[rs], ALUctr= add, RegDst=rd, RegWr, npc_sel= +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc=R[rs], ALUctr= sub, RegDst=rd, RegWr, npc_sel= +4 LOAD R[rt] < MEM[ R[rs] + sign_ext(imm16)]; PC < PC + 4 ALUsrc = Im, ALUctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_ext(imm16)] < R[rs]; PC < PC + 4 ALUsrc=Im, ALUctr= add, MemWr, npc_sel= +4 BEQ if(r[rs]== R[rt]) then PC< PC+sign_ext(Imm16)] 00 else PC < PC + 4 npc_sel = EQUAL, ALUctr = sub 58
59 Main Control Unit Effect of the control signals when they are asserted or de-asserted respectively See fig. 4.16, p. 321 Signal name If de-asserted (0) If asserted (1) RegDst Destination register <= rt field (20-16) Destination register <= rd field (15-11) RegWrite None Write data input => Write register ALUSrc Reg Data2 => 2nd ALU operand Sign-extnd 16-bits of instruction => 2nd ALU operand PCSrc PC <= PC + 4 (from adder) PC <= Branch target (from adder) MemRead None Mem[Address] => to Read data output MemWrite None Mem[Address] <= value on Write data input MemtoReg Value to Write data input comes from ALUValue to Write data input comes from data memory 59
60 Main Control Unit The control signals based on different Opcode 60
61 Main Control Unit Control lines needed by each instruction (See Fig 5.18, p. 308) R-Format (add, sub, AND, OR, & slt) Source register : rs & rt Destination register: rd Writes a register (RegWrite = 1) but neither reads nor writes data memory ALUOp for R-Type format = 10 indicating that ALU control should be generated from function field When Branch: Control signal = 0, PC<= PC +4; Otherwise it is replaced by Branch target For lw MemRead = 1, For sw MemWrite = 1 Instruction RegDest ALUSrc MemtoReg RegWrite MemRead MemWrite Banch ALUOp1 ALUOp0 R-Format lw sw X 1 X beq X 0 X
62 CLK Setup Setup 62
63 63
64 64
65 Single Cycle Implementation Exercise: Assuming we have the following instruction mix: Load 25% Store 10% ALU instructions 45% Branch 15% Jump 5% Calculate cycle time and total program (with L instructions) execution time Assuming negligible delays except for the following: memory (200 ps) (ps = Pico Second) ALU and adders (100 ps) Register file access (50 ps) Note: For single-cycle instruction, CPI = 1 Answer: (Complete answer) 65
66 Single Cycle Problems Single cycle instruction is not used in modern computers Disadvantages: Inefficient in both performance and HW cost Clock cycle must have the same length for every instruction Clock cycle determined by the longest possible path For complicated instruction like floating point, it will be harder Functional units must be duplicated, since each can be used only once per cycle 66
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