Microprocessor Power Analysis by Labeled Simulation

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Abel Osborne
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1 Microprocessor Power Analysis by Labeled Simulation Cheng-Ta Hsieh, Kevin Chen and Massoud Pedram University of Southern California Dept. of EE-Systems Los Angeles CA 989 Outline! Introduction! Problem Formulation! Source and Sink! Architecture Patterns! Propagation Rules! Generalizations! Conclusions

2 Macro-Analysis vs. Micro-Analysis! Macro-Analysis can answer the questions:! How long the battery of a notebook computer can last if we run the Internet Explorer?! Is MIPS more power-efficient than Strong ARM for running Windows CE 2.?! Micro-Analysis can answer the questions:! What is the power consumption of a branch instruction, or a compare instruction?! How much power is consumed in some component for a certain instruction? Instruction Level Macro Modeling! Instruction Base Costs! Individual instruction! Effect of Circuit State! Consecutive instruction pair! Inter-Instruction Effects! Pipeline stall, cache misses 2

3 Review of Instruction Level Model Power Macro Model Instruction Base Power Program Consecutive Instruction Pair Power Program Instruction Stall and Cache Miss Power etc. Base Pair Other E = ( B N ) + ( O N ) + E P i i i, j i, j k i i, j k Problem Formulation! Given N gates, g,g 2, g n in a processor and k active instructions,,,i k! For each gate g i, find an instruction set or a labeling, L j ={, I m, such that the energy consumption of the gate in the current clock cycle is caused by instructions in L i! Calculate instruction power consumption by label propagation L j Gate j 3

4 Cycle-Accurate Energy Calculation! Let gates(i) denote the set of label indices that contain instruction I! Energy consumed by instruction I in the current clock cycle is: 2 EI () = CV j ddswj 2 L j gates( I) j An Example Pipeline IF ID EX MEM WB Control Control Control PC. File ALU 4

5 Example (cont d) I 4 I 5 I 4 A Simple Propagation Rule {I x {I x { {I x { { {I x {I x { {I x D SET CLR Q Q SET D Q {I x CLR Q Next Clock Cycle 5

6 Definitions! Source! Set of gates (or wires) from which the labels are originated! Sink! Set of gates (or flip-flops) where the instruction label is dropped! Label Propagation Rule! A description of how the labels are propagated through FSM s, MUX s, FF s, and primitive gates Architecture Pattern! Name! The handle that is used to described the intended architecture effect (e.g., pipeline-flush, pipeline-stall, data-forwarding)! Description! Explanation of how the pattern is caused and how the processor reacts to the pattern! Liable Set! Set of instructions that are responsible for the power dissipation caused by the architecture pattern! Required Rule! Specification of how the propagation rule should work in response to the pattern 6

7 An Architecture Pattern Example! Name! Streamlined Execution.! Description! Each pipeline stage performs the operation specified by the incoming instruction! Liable Set! The instruction being executed in a pipeline stage is responsible for the power dissipation of that stage! Required Rule! The instruction label in a pipeline is transferred to the next stage in the next clock cycle Feasible Labeling Problem! Given a! set of architecture patterns.! Find the! set of sources! setofsinks! set of label propagation rules! that satisfy all the required rules in the set of architecture patterns 7

8 Implication by Domination! An architecture pattern is dominated by a combination of other patterns if its required rules are covered by the required rules of these architecture patterns! A labeling scheme is feasible for a target processor if all of the architecture patterns of that processor are dominated by the architecture patterns that are captured by the labeling scheme Source PC 44 addr 4 : add $,$2,$3 44 : sub $4,$5,$6 48 : sti $8,$7, 52 I 4 : muli $5,$7,4 56 I 5 : lw $24, ($6)... { Instruction Pipeline Label Source 8

9 Sink add $3,$,$3 mov $, write reg number write Write Back mov $, -to-32 decoder write data (imm value : ) Q register D Q register D... Q D Q register 3 D Instruction Decode read reg num M U X M U X read reg num 2 add $3, $, $3 read data read data 2 Journey of a MIPS Instruction PC Write SR Write REG Read ALU MEM Read REG Write MEM Write 9

10 Pipeline-Stall Pattern sub and sub and sub and sub I2 sub $2,$,$3 and $2,$2,$5 and Hazard Detection Circuit src(i 4 ) dst( ) dst( ) dst( ) {I 4 { == == == Hazard Detection {I 5 {I 4 {I 4 {I 4, {I 4 { Credit Both {I 4, Credit Last {I 4 I 5 I 4

11 Data Forwarding Pattern ID. File M U X M U X EX MEM WB { { { ALU Forwarding Control { src(i 3 ) dst(i 2 ) dst( ) == == { { { { Pipeline Flush Pattern 4 beq $,$3,28 44 and $2,$2,$5 48 or $3,$6,$2 52 add $4,$2,$2 72 lw $4, 5($7)

12 Pipeline Flush Control Circuit control control control Flush from prev. stage L 2 L out to next stage hazard detected L hazard L flush =L Flush L predicted condition actual condition L or{ Queuing Pattern L a ={I 4 L c L b queue L b busy wait busy operands not available 2

13 General Propagation Rules " Primitive Gates in in 2 L 2-input gate L out L 2 " OR Gate in in 2 L out L L L 2 L Priority Rule: If L ={I i, L 2 ={I j, then L ={I max(i,j) Union Rule: L =L L 2 Rules for Primitive Gates (cont d) " AND Gate " XOR Gate in in 2 L out L L 2 L L in in 2 L out L L L L 3

14 MUX Propagation Rule L L 2 L out L s select select L s ==φ L ==φ L 2 ==φ L out x x L s x L x (L s +L ) x x L s x L 2 x (L s ) Generalization Pseudo Instruction Cache Miss Inst Cache (nop) {I cache_miss I 4 I 4 (nop) hazard_detected 4

Generalization - Instruction Splitting An ARM arithmetic instruction 3 3 29 28 27 26 25 24 23 22 2 2 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 cond op S Rd Rn shifter_operand Operation if ConditionPassed

15 Generalization - Instruction Splitting An ARM arithmetic instruction cond op S Rd Rn shifter_operand Operation if ConditionPassed (<cond>) then Rd = Rn <op> <shifter_operand> if S == and Rd == R5 then CPSR = SPSR else if S == then NFlag=Rd[3] ZFlag=ifRd==thenelse C Flag = CarryFrom (Rn + <shifter_operand>) V Flag = OverflowFrom (Rn + <shifter_operand>) A Design Example: ZILOG DSP CORE 5

16 Energy Calculation P = E sw + C Vdd sw x y ( ini ini ) ( oni i oni ) n= n= 2 Cell Power Net Power P = power dissipation for current clock cycle (µj); x = number of input pins; E in = energy associated with the n th input pin (µw/mhz) y = number of output pins; C on = external capacitive loading Experimental Results Instruction Class Average Energy( -8 J) Instruction Count NON.53 - SL MAC CTRL. 3 CAS.47 7 ALF

17 Summary! Proposed technique reports cycle-accurate (finegrain) power consumption for each instruction being executed in a pipelined (superscalar) machine! Proposed technique helps identify power problems during the processor design phase! Proposed technique is verified against MIPS, ARM, Pentium microprocessor, and a Zilog DSP! Pseudo instruction and instruction splitting are useful for building a high-level macro-model that accounts for hard-to-capture power effects 7

3. (2) What is the difference between fixed and hybrid instructions?

1. (2 pts) What is a "balanced" pipeline? 2. (2 pts) What are the two main ways to define performance? 3. (2) What is the difference between fixed and hybrid instructions? 4. (2 pts) Clock rates have grown