Circuit Modeling for Practical Many-core Architecture Design Exploration

Transcription

1 Circuit Modeling for Practical Many-core Architecture Design Exploration Redefining design abstractions Dean Truong Bevan Baas VLSI Computation Lab University of California, Davis

2 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

3 Motivation We have the hardware Many-core chip capable of per-core DVFS Inter-core communication through FIFOs We need an accurate and intuitive modeling of the system to find an optimal DVFS scheme Achieved through appropriate analogies Circuit analogy is useful because circuit analysis has well developed CAD and mathematical tools Control analogy is useful because control systems analysis is very mature Model many-core systems like circuits?

4 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

5 Circuit Model of Two Cores Producer Consumer application Charge (Q) = sample Current (I) = samples/sec; data rate Conductance (G) = cycles/sec; (core) frequency Voltage (V) = samples/cycle; (CPI x IC) -1 CPI = cycles per instruction IC = instructions per sample Ohms Law: I = V x G data rate = samples/cycle x cycles/sec Capacitance (C) = Q/V = cycles Time = C/G = seconds! Producer (f p ) Producer Conductance Producer Voltage + i C i P i FIFO GC G P i P U FIFO 1 s i C i FIFO C FIFO C FIFO Consumer (f c ) + + Consumer Conductance + Consumer Voltage U Consumer U FIFO U Producer

6 Circuit Model (cont.) Want U FIFO = 0 U FIFO > 0: FIFO full U FIFO < 0: FIFO empty When U FIFO 0 core(s) are stalling (U FIFO /U Core )% of the time Continuous time model DVFS algorithm only acts over long periods compared to core frequencies T control >> 1/f Core

7 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

8 DVFS Control Strategy Varying the conductance (frequency) makes control nonlinear Approximate: two linear control systems selected by a mux Controller selects High and Low states through the mux Voltage dithering! Controller samples U FIFO every dither period Controller is discrete Modeled in MATLAB and implemented in software using processor DVFS instructions

9 Measured Results Worst case: 46.6 mw at VddHigh = 1.3 V; f H = 1.2 GHz Ideal case: 12.0 mw at VddHigh = 0.9 V; f H = 550 MHz DVFS: 15.6 mw at VddHigh = 1.3 V, VddLow = 0.8 V; f H = 1.2 GHz, f L = 300 MHz Settling time Several hours! P L = 74.4%, P H = 25.6% Ideal: P L = 72.22%, P H = 27.78%

10 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

11 Saturation Modeling So far our circuit model does not saturate the data rate when U FIFO 0 If U FIFO < 0, i P > U Producer G P If U FIFO > 0, i C > U Consumer G C Have to add current limiters G P U Producer G P U Producer U FIFO i P i C G C U Consumer C FIFO G C U Consumer C FIFO

12 Saturation Modeling (cont.) MOSFETs have linear and saturation regions Linear = resistor Saturation = current limiter PMOS: set V th = 0, if U FIFO 0 i P = -I DS = (k/2)v GS2, saturation: V DS V GS V GS = -U P Want: i P = U P G P k = 2G P /U P Else linear: V DS > V GS i P = k(v GS V DS (V DS2 )/2) = -(2G P V DS (V DS2 )/(2U P )) Want: i P = (U P U FIFO )G P = -V DS G P U P IDS Linear S G Saturation V DS i P D U FIFO

13 Improved Model Make a new MOS model in SPICE to accommodate modified linear region Can adjust conductance by changing W/L Switch between two MOSFETs High and Low PMOS (producer) M PH : (W/L) High M PL : (W/L) Low NMOS (consumer) M CH : (W/L) High M CL : (W/L) Low M PH M PL U Producer DVFS Controller U FIFO i P i C C FIFO M CH M CL U Consumer

14 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

15 Tomasulo s Algorithm Used in the IBM 360/91 floating-point unit to allow out-of-order execution Tomasulo s algorithm enables out-of-order execution through register renaming via reservation stations and load/store buffers Let us see if we can model this algorithm How much can be abstracted into a circuit element or logic gate?

16 Tomasulo s Algorithm (cont.) Instruction Queue Instruction Unit Register File Load/Store Address Buffers Memory Address Unit Memory Unit Store Data Buffer Reservation Station Reservation Station X Common Data Bus (CDB)

17 Tomasulo s Circuit Instruction Decode RS_Update Pulse Generators CDB Arbiter Instruction_Type Instruction Unit I Instr U Queue Instruction_Rd U Bias_Half IssueAdd_Qj IssueAdd_Qk IssueMult_Qj IssueMult_Qk IssueLoad_Qj-A IssueStore_Qj-Qk-A FullStore FullLoad FullMult U Mult_Qk FullAdd U Add_Qj U Add_Qk U Mult_Qj C Add_Qj CDBWrBkAdd C Add_Qk C Instr U Issue U Load_Qj-A CDBWrBk Mult U Store_Qj-Qk-A C Mult_Qj C Mult_Qk CDBWrBk Load C Load_Qj-A C Store_Qj-Qk-A CDBWrBk Store

18 Tomasulo s Circuit (cont.) Register Status Register_ID Instruction Unit U Bias_LSB CDBWrBk Register RS_ValueUpdate WrDataAdd_Vj WrDataAdd_Vk WrDataMult_Vj WrDataMult_Vk CDBWrBk Forwarding Pulse Generators WrDataLoad_Vj WrDataStore_Vj-Vk Memory Unit ExecuteStore ExecuteLoad U Add ExecuteAdd L Add_Pipeline U Mult ExecuteMult U Add_Vk WrBk Mem WrBk Add WrBk Mult L Mult_Pipeline U Add_Vj CDBWrBkAdd CDB Arbiter U Mult_Vj C Add_Vj U Mult_Vk C Add_Vk U Reg/CDB U Load_Vj-A CDBWrBk Mult U Store_Vj-Vk C Mult_Vj C Mult_Vk CDBWrBk Load C Load_Vj-A CDBWrBk Store C Store_Vj-Vk

19 Outline Motivation Circuit Model of Two Cores DVFS Control and Results Improved Model Tomasulo s Algorithm Conclusions

20 Conclusions System level modeling with circuit equivalents Reuse circuit design principles and CAD Easily translates into control theory or signals and systems analysis Reuse mixed-signal simulation tools to develop higher level systems Optimal DVFS requires a holistic approach from the circuit layer to application layer Circuit modeling can ease translation between layers The physical world can be modeled as circuits Streamlines development of cyber-physical systems

21 Acknowledgements ST Microelectronics NSF Grant , and CAREER award Intel SRC GRC Grant 1598, 1971 and CSR Grant 1659 Intellasys UC Micro SEM J.-P. Schoellkopf, K. Torki, S. Dumont, Y.-P. Cheng, R. Krishnamurthy and M. Anders